Undervoltage detection circuit

Abstract

A voltage undervoltage detection circuit includes a voltage divider, a voltage-to-current converter, and a current comparator. The voltage divider divides a power supply voltage to generate a divided voltage. The voltage-to-current converter converts the divided voltage into a first current based on a first voltage-to-current conversion function, and converts the divided voltage into a second current based on a second voltage-to-current conversion function. The second voltage-to-current conversion function is different from the first voltage-to-current conversion function. The current comparator compares the first current and the second current to generate a comparison signal. The comparison signal indicates whether the power supply voltage is large enough. By appropriately designing the first voltage-to-current conversion function and the second voltage-to-current conversion function, the voltage undervoltage detection circuit can have little correlation with process and temperature variations.

Description

Technical Field

[0001] The present invention relates to voltage detection, and more particularly to an undervoltage detection circuit. Background Art

[0002] Undervoltage detection circuits are used in chips to detect whether the chip's power supply voltage is large enough. When the power supply voltage is determined to be insufficient, other circuits of the chip will be locked to avoid malfunction and short-circuit current. It is important that the undervoltage detection circuit has little correlation with process and temperature variations.

[0003] The conventional undervoltage detection circuit includes a bandgap circuit and a comparator. The bandgap circuit generates a bandgap voltage that is independent of process and temperature variations. The comparator compares the bandgap voltage with a voltage derived from the power supply voltage to determine whether the power supply voltage is large enough. The bandgap circuit will only work when the power supply voltage is greater than a large start-up threshold, so the conventional undervoltage detection circuit disadvantageously has a large undefined area (i.e., a power supply voltage range in which the undervoltage detection circuit cannot normally provide an output). Summary of the invention

[0004] An object of the present invention is to provide a voltage undervoltage detection circuit which has little correlation with process and temperature variations when the voltage-to-current conversion function of the voltage undervoltage detection circuit is properly designed.

[0005] The voltage under-detection circuit of the present invention comprises a voltage divider, a voltage-to-current converter and a current comparator. The voltage divider receives a power supply voltage and divides the power supply voltage to generate a divided voltage. The voltage-to-current converter is electrically connected to the voltage divider to receive the divided voltage, converts the divided voltage into a first current based on a first voltage-to-current conversion function, and converts the divided voltage into a second current based on a second voltage-to-current conversion function. The second voltage-to-current conversion function is different from the first voltage-to-current conversion function. The current comparator is electrically connected to the voltage-to-current converter to receive the first current and the second current, and compares the first current and the second current to generate a comparison signal. The comparison signal indicates whether the power supply voltage is large enough.

[0006] In the voltage undervoltage detection circuit of the present invention, the voltage-to-current converter includes a first resistor, a second resistor, a first bipolar junction transistor, and a second bipolar junction transistor. The first resistor has a first end and a second end. The first end of the first resistor receives one of the power supply voltage and the ground voltage. The second resistor has a first end and a second end. The first end of the second resistor is electrically connected to the second end of the first resistor. The first bipolar junction transistor has an emitter terminal, a collector terminal, and a base terminal. The emitter terminal of the first bipolar junction transistor is electrically connected to the second end of the second resistor. The collector terminal of the first bipolar junction transistor is electrically connected to the current comparator and provides the first current. The base terminal of the first bipolar junction transistor is electrically connected to the voltage divider to receive the divided voltage. The second bipolar junction transistor has an emitter terminal, a collector terminal, and a base terminal. The emitter terminal of the second bipolar junction transistor is electrically connected to the second end of the first resistor. The collector terminal of the second bipolar junction transistor is electrically connected to the current comparator and provides the second current. The base terminal of the second bipolar junction transistor is electrically connected to the voltage divider to receive the divided voltage. A saturation current of the second bipolar junction transistor is smaller than a saturation current of the first bipolar junction transistor.

[0007] In the undervoltage detection circuit of the present invention, the current comparator includes a first current mirror, a second current mirror and a third current mirror. The first current mirror has an input terminal and an output terminal. The input terminal of the first current mirror is electrically connected to the voltage-to-current converter to receive the first current. The second current mirror has an input terminal and an output terminal. The input terminal of the second current mirror is electrically connected to the voltage-to-current converter to receive the second current. The third current mirror has an input terminal and an output terminal. The input terminal of the third current mirror is electrically connected to the output terminal of the first current mirror. The output terminal of the third current mirror is electrically connected to the output terminal of the second current mirror. The comparison signal is provided at a common node of the second current mirror and the third current mirror.

[0008] In the voltage under-detection circuit of the present invention, the ratio of the divided voltage to the power supply voltage changes with the comparison signal.

[0009] In the voltage under-detection circuit of the present invention, the voltage divider includes a first resistor, a second resistor, a third resistor and a switch. The first resistor has a first end and a second end. The first end of the first resistor receives one of the power supply voltage and the ground voltage. The second end of the first resistor is electrically connected to the voltage-to-current converter. The second resistor has a first end and a second end. The first end of the second resistor is electrically connected to the second end of the first resistor. The third resistor has a first end and a second end. The first end of the third resistor is electrically connected to the second end of the second resistor. The second end of the third resistor receives the other of the power supply voltage and the ground voltage. The switch is connected in parallel with the third resistor and has a control end. The switch is turned on when the comparison signal indicates that the power supply voltage is large enough, and is not turned on when the comparison signal indicates that the power supply voltage is not large enough. The divided voltage is provided at a common node of the first resistor and the second resistor.

[0010] The voltage under-detection circuit of the present invention further includes an undefined region limiter. The undefined region limiter includes a first metal oxide semiconductor field effect transistor, a resistive element and a second metal oxide semiconductor field effect transistor. The first metal oxide semiconductor field effect transistor has a drain terminal, a source terminal and a gate terminal. The source terminal of the first metal oxide semiconductor field effect transistor receives one of the power supply voltage and the ground voltage. The gate terminal of the first metal oxide semiconductor field effect transistor is electrically connected to the current comparator. The first metal oxide semiconductor field effect transistor generates a current, and the current generated by it is a mirror image of one of the first current and the second current. The resistive element has a first terminal and a second terminal. The first terminal of the resistive element receives the other of the power supply voltage and the ground voltage. The second terminal of the resistive element is electrically connected to the drain terminal of the first metal oxide semiconductor field effect transistor. The second metal oxide semiconductor field effect transistor is a low threshold voltage metal oxide semiconductor field effect transistor and has a drain terminal, a source terminal and a gate terminal. The drain terminal of the second metal oxide semiconductor field effect transistor is electrically connected to the current comparator. The source terminal of the second metal oxide semiconductor field effect transistor is electrically connected to the source terminal of the first metal oxide semiconductor field effect transistor. The gate terminal of the second metal oxide semiconductor field effect transistor is electrically connected to the drain terminal of the first metal oxide semiconductor field effect transistor. When the second metal oxide semiconductor field effect transistor is turned on, the current comparator causes the comparison signal to indicate that the power supply voltage is not large enough.

[0011] In the voltage under-detection circuit of the present invention, the resistive element includes a plurality of metal oxide semiconductor field effect transistors. Each metal oxide semiconductor field effect transistor of the resistive element is a low threshold voltage metal oxide semiconductor field effect transistor. The metal oxide semiconductor field effect transistors of the resistive element are connected in series between the first end and the second end of the resistive element. Each metal oxide semiconductor field effect transistor of the resistive element has a gate terminal, and its gate terminal receives the ground voltage.

[0012] The voltage under-detection circuit of the present invention further comprises a capacitor. The capacitor has a first end and a second end. The first end of the capacitor receives the power supply voltage and the ground voltage corresponding to the power supply voltage being insufficient. The second end of the capacitor is electrically connected to a node of the current comparator. The comparison signal is provided at the node.

[0013] The voltage under-detection circuit of the present invention further comprises a first inverter and a second inverter. The first inverter is one of a low-skew inverter and a high-skew inverter, and has an input terminal and an output terminal. The input terminal of the first inverter is electrically connected to the current comparator to receive the comparison signal. The second inverter is the other of the low-skew inverter and the high-skew inverter, and has an input terminal and an output terminal. The input terminal of the second inverter is electrically connected to the output terminal of the first inverter.

[0014] The beneficial effect of the present invention is that by properly designing the first voltage-to-current conversion function and the second voltage-to-current conversion function, the voltage undervoltage detection circuit can have little correlation with process and temperature variations. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a circuit diagram illustrating a first embodiment of a voltage shortage detection circuit of the present invention;

[0016] Figure 2 is a schematic diagram illustrating a first voltage-to-current conversion function and a second voltage-to-current conversion function of the first embodiment;

[0017] Figure 3 is a timing diagram illustrating a power supply voltage, a comparison signal and an output signal of the first embodiment;

[0018] Figure 4 is a circuit diagram illustrating a variation of the first embodiment;

[0019] Figure 5 is a circuit diagram illustrating a second embodiment of the undervoltage detection circuit of the present invention;

[0020] Figure 6 is a circuit diagram illustrating a third embodiment of the undervoltage detection circuit of the present invention; and

[0021] Figure 7 is a circuit diagram illustrating a fourth embodiment of the undervoltage detection circuit of the present invention. DETAILED DESCRIPTION

[0022] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0023] Before the present invention is described in detail, it should be noted that similar elements are denoted by the same reference numerals in the following description.

[0024] See also Figure 1 The first embodiment of the undervoltage detection circuit of the present invention includes a voltage divider 1, a voltage-to-current converter 2, a current comparator 3, an undefined region limiter 4 and two inverters 5 and 6.

[0025] Voltage divider 1 receives a supply voltage V DD , and the power supply voltage V DD Divide the voltage to generate a divided voltage V div .

[0026] The voltage-to-current converter 2 is electrically connected to the voltage divider 1 to receive the divided voltage V div , based on a first voltage-to-current conversion function, the divided voltage V div is converted into a first current I1, and the divided voltage V is converted into a first current I1 based on a second voltage-to-current conversion function. div The second voltage-to-current conversion function is different from the first voltage-to-current conversion function.

[0027] The current comparator 3 is electrically connected to the voltage-to-current converter 2 to receive the first current I1 and the second current I2, and compares the first current I1 and the second current I2 to generate a comparison signal COMP. The comparison signal COMP indicates the power supply voltage V DD Is it big enough?

[0028] The undefined region limiter 4 is electrically connected to the current comparator 3. When the power supply voltage V DD When the current comparator 3 can normally provide the comparison signal COMP, the undefined region limiter 4 makes the comparison signal COMP indicate the power supply voltage V DD Not big enough.

[0029] The inverter 5 has an input terminal and an output terminal. The input terminal of the inverter 5 is electrically connected to the current comparator 3 to receive the comparison signal COMP. The output terminal of the inverter 5 provides an output signal OUT1 complementary to the comparison signal COMP.

[0030] The inverter 6 has an input terminal and an output terminal. The input terminal of the inverter 6 is electrically connected to the output terminal of the inverter 5 to receive the output signal OUT1. The output terminal of the inverter 6 provides an output signal OUT2 complementary to the output signal OUT1.

[0031] In this embodiment, the ratio of the divided voltage to the power supply voltage (that is, V div / V DD ) changes with the comparison signal COMP, and the voltage divider 1 includes three resistors 11-13 and a switch 14. The resistors 11-13 each have a first end and a second end, and their respective resistance values ​​are R3, R4 and R5. The first end of the resistor 11 is electrically connected to a first power rail 8 to receive the power supply voltage V DD . A first end of the resistor 12 is electrically connected to a second end of the resistor 11. A first end of the resistor 13 is electrically connected to a second end of the resistor 12. A second end of the resistor 13 is electrically connected to a second power rail 9 to receive a ground voltage. A switch 14 (e.g., an N-type metal oxide semiconductor field effect transistor (nMOSFET)) is connected in parallel with the resistor 13 and has a control end (e.g., a gate end). The control end of the switch 14 is electrically connected to an output end of the inverter 5 to receive an output signal OUT1. The divided voltage V div is provided at the common node of the resistors 11 and 12. When the comparison signal COMP is in a logic 0 state, the switch 14 is turned on and the ratio V div / V DD =R4 / (R3+R4). When the comparison signal COMP is in a logic 1 state, the switch 14 is not conducting and the ratio V div / V DD Equal to (R4+R5) / (R3+R4+R5).

[0032] In this embodiment, the voltage-to-current converter 2 includes two resistors 21, 22 and two PNP bipolar junction transistors (BJT) 23, 24. The resistors 21, 22 each have a first end and a second end, and their respective resistance values ​​are R1 and R2. The first end of the resistor 21 is electrically connected to the first power rail 8 to receive the power supply voltage V DD The first end of the resistor 22 is electrically connected to the second end of the resistor 21. The PNP bipolar junction transistors 23 and 24 each have an emitter terminal, a collector terminal, and a base terminal. The emitter terminal of the PNP bipolar junction transistor 23 is electrically connected to the second end of the resistor 22. The collector terminal of the PNP bipolar junction transistor 23 provides a first current I1. The base terminal of the PNP bipolar junction transistor 23 is electrically connected to the common node of the resistors 11 and 12 to receive the divided voltage Vdiv The emitter terminal of the PNP bipolar junction transistor 24 is electrically connected to the second terminal of the resistor 21. The collector terminal of the PNP bipolar junction transistor 24 provides a second current I2. The base terminal of the PNP bipolar junction transistor 24 is electrically connected to the common node of the resistors 11 and 12 to receive the divided voltage V div The saturation current of the PNP bipolar junction transistor 24 is I s , and the saturation current of the PNP bipolar junction transistor 23 is k·I s , where k > 1. In other words, the saturation current of the PNP bipolar junction transistor 24 is less than the saturation current of the PNP bipolar junction transistor 23.

[0033] In this embodiment, the current comparator 3 includes three current mirrors 31 to 33. Each of the current mirrors 31 to 33 has an input terminal and an output terminal. The input terminal of the current mirror 31 is electrically connected to the collector terminal of the PNP bipolar junction transistor 23 to receive the first current I1. The input terminal of the current mirror 32 is electrically connected to the collector terminal of the PNP bipolar junction transistor 24 to receive the second current I2. The input terminal of the current mirror 33 is electrically connected to the output terminal of the current mirror 31. The output terminal of the current mirror 33 is electrically connected to the output terminal of the current mirror 32. The comparison signal COMP is provided at the common node of the current mirrors 32 and 33. Each of the current mirrors 31 and 32 includes two N-type metal oxide semiconductor field effect transistors 311 / 321, 312 / 322. The current mirror 33 includes two P-type metal oxide semiconductor field effect transistors (pMOSFETs) 331 and 332. The sizes of the metal oxide semiconductor field effect transistors 311 to 332 of the current mirrors 31 to 33 are designed such that: (1) when n1·I1 > n2·I2, the comparison signal COMP is in the logic 1 state (that is, its voltage is equal to the power supply voltage V DD ); and (2) when n1·I1 < n2·I2, the comparison signal COMP is in the logic 0 state (that is, its voltage is equal to the ground voltage), where n1 and n2 are constants and can be the same or different from each other.

[0034] In this embodiment, the undefined region limiter 4 includes two N-type metal oxide semiconductor field effect transistors 41, 43 and a resistive element 42. The N-type metal oxide semiconductor field effect transistor 41 has a drain terminal, a source terminal and a gate terminal. The source terminal of the N-type metal oxide semiconductor field effect transistor 41 is electrically connected to the second power rail 9 to receive the ground voltage. The gate terminal of the N-type metal oxide semiconductor field effect transistor 41 is electrically connected to the gate terminal of the N-type metal oxide semiconductor field effect transistor 321. The N-type metal oxide semiconductor field effect transistor 41 generates a current, and the current generated by it is a mirror image of the second current I2. The resistive element 42 has a first terminal and a second terminal. The first terminal of the resistive element 42 is electrically connected to the first power rail 8 to receive the power supply voltage V DD . The second end of the resistive element 42 is electrically connected to the drain end of the N-type metal oxide semiconductor field effect transistor 41. The resistive element 42 includes a plurality of P-type metal oxide semiconductor field effect transistors 421. Each of the P-type metal oxide semiconductor field effect transistors 421 of the resistive element 42 is a low threshold voltage metal oxide semiconductor field effect transistor. The P-type metal oxide semiconductor field effect transistors 421 of the resistive element 42 are connected in series between the first end and the second end of the resistive element 42. Each of the P-type metal oxide semiconductor field effect transistors 421 of the resistive element 42 has a gate end, and its gate end is electrically connected to the second power rail 9 to receive the ground voltage. The N-type metal oxide semiconductor field effect transistor 43 is a low threshold voltage metal oxide semiconductor field effect transistor and has a drain end, a source end and a gate end. The drain end of the N-type metal oxide semiconductor field effect transistor 43 is electrically connected to the gate end of the P-type metal oxide semiconductor field effect transistor 332. The source end of the N-type metal oxide semiconductor field effect transistor 43 is electrically connected to the source end of the N-type metal oxide semiconductor field effect transistor 41. The gate terminal of the NMOS 43 is electrically connected to the drain terminal of the NMOS 41. When the NMOS 43 is turned on, the PMOS 332 is also turned on to make the comparison signal COMP at the logic 1 state.

[0035] Figure 2 A first voltage-to-current transfer function and a second voltage-to-current transfer function are described. Figure 1 and Figure 2 , when the voltage across the resistors 21, 22 and the base-emitter junction of the PNP bipolar junction transistor 23 (or the voltage across the resistor 21 and the base-emitter junction of the PNP bipolar junction transistor 24) (that is, V DD -V div ) is less than a corresponding switching threshold V dif,swWhen n1·I1 > n2·I2 and the comparison signal COMP is in the logic 1 state to indicate that the power supply voltage V DD is not large enough. When the voltage V DD -V div is equal to the switching threshold V dif,sw then n1·I1 = n2·I2. When the voltage V DD -V div is greater than the switching threshold V dif,sw then n1·I1 < n2·I2 and the comparison signal COMP is in the logic 0 state to indicate that the power supply voltage V DD is large enough. Thus, in operation, the comparison signal COMP switches when the voltage V DD -V div is equal to the switching threshold V dif,sw .

[0036] The first current I1 and the second current I2 can be expressed by the following formulas respectively:

[0037]

[0038]

[0039] where V BE1 represents the voltage across the base-emitter junction of the PNP bipolar junction transistor 23, V BE2 represents the voltage across the base-emitter junction of the PNP bipolar junction transistor 24, and V T represents the thermal voltage.

[0040] In addition, the first current I1 can be expressed by the following formula:

[0041]

[0042] Based on Formulas 1 to 3, the switching threshold V dif,sw can be derived as follows.

[0043]

[0044] The temperature coefficient of the voltage V BE2 is approximately -1.5 mV / °K. The temperature coefficient of the thermal voltage V T is approximately 0.087 mV / °K. By appropriately selecting the parameters k, n1, n2, R1, R2, the temperature coefficient of the switching threshold V dif,sw can be zero.

[0045] Referring to Figure 1 and Figure 3 when the power supply voltage V DDWhen the current comparator 3 provides the comparison signal COMP normally, the voltage undervoltage detection circuit of the present embodiment operates as follows. At the beginning, the comparison signal COMP is in the logic 1 state, the switch 14 is not turned on, and the divided voltage V div equal Afterwards, when the power supply voltage V DD Equal to a corresponding switching threshold V DD,sw1 (Its value is ), the comparison signal COMP switches to the logic 0 state. When the power supply voltage V DD When the current comparator 3 normally provides the comparison signal COMP, the voltage undervoltage detection circuit of the present embodiment operates as follows. At the beginning, the comparison signal COMP is in the logic 0 state, the switch 14 is turned on, and the divided voltage V div equal Afterwards, when the power supply voltage V DD Equal to a corresponding switching threshold V DD,sw2 (Its value is ), the comparison signal COMP switches to the logic 1 state. The switching threshold V DD,sw2 Different from the switching threshold V DD,sw1 Therefore, the undervoltage detection circuit of this embodiment has a hysteresis phenomenon.

[0046] In an example where the undefined region limiter 4 is omitted, the lower limit of the range in which the current comparator 3 can normally provide the comparison signal COMP is determined by the voltage between the gate terminal and the source terminal of the P-type metal oxide semiconductor field effect transistor 331 and the voltage between the drain terminal and the source terminal of the N-type metal oxide semiconductor field effect transistor 312, and is approximately 0.7V to 0.8V. Therefore, the undefined region (i.e., the power supply voltage V in which the voltage undervoltage detection circuit cannot normally provide the output signals OUT1 and OUT2) is DD In this embodiment, when the power supply voltage V DD Gradually rising, the power supply voltage V DD is greater than the threshold voltage of the N-type metal oxide semiconductor field effect transistor 43 and the threshold voltage of each of the P-type metal oxide semiconductor field effect transistors 421, the power supply voltage V DD Less than the switching threshold V DD,sw1 , the undefined region limiter 4 operates as follows. Initially, the N-type metal oxide semiconductor field effect transistor 41 is not turned on, and the P-type metal oxide semiconductor field effect transistor 421 and the N-type metal oxide semiconductor field effect transistor 43 are turned on, so the P-type metal oxide semiconductor field effect transistor 332 is turned on to make the comparison signal COMP in the logic 1 state. Afterwards, the second current I2 increases with the power supply voltage V DDThe undefined area increases rapidly with the rise of , so the N-type metal oxide semiconductor field effect transistor 41 is turned on, and the N-type metal oxide semiconductor field effect transistor 43 is not turned on. Therefore, the upper limit of the undefined area is equal to the maximum of the threshold voltage of the N-type metal oxide semiconductor field effect transistor 43 and the threshold voltage of each P-type metal oxide semiconductor field effect transistor 421 (about 0.4V to 0.5V). Compared with the previous example, the undefined area is reduced in this embodiment.

[0047] Return to Reference Figure 1 It should be noted that, in other embodiments, the following modifications may be made to this embodiment.

[0048] (1) The resistive element 42 is implemented by an active element other than a P-type metal oxide semiconductor field effect transistor, or by a passive element (such as a resistor).

[0049] (2) Figure 4 As shown, inverter 5 is a low skew inverter, and inverter 6 is a high skew inverter, thereby further reducing the undefined area.

[0050] (3) The undefined region limiter 4 is omitted, the inverter 5 is a low-skew inverter, and the inverter 6 is a high-skew inverter.

[0051] In summary, the undervoltage detection circuit of this embodiment has the following advantages.

[0052] (1) By designing the first voltage-to-current conversion function and the second voltage-to-current conversion function so that the switching threshold V dif,sw The temperature coefficient of the undervoltage detection circuit is zero, and the correlation between the undervoltage detection circuit and the process and temperature variations can be very small.

[0053] (2) Through the undefined region limiter 4, the power supply voltage V DD When the current comparator 3 can normally provide the comparison signal COMP, the comparison signal COMP indicates the power supply voltage V DD Not big enough, you can shrink the undefined area.

[0054] See also Figure 5 The second embodiment of the undervoltage detection circuit of the present invention is similar to the first embodiment, and is different from the first embodiment in that the gate terminal of the N-type metal oxide semiconductor field effect transistor 41 is electrically connected to the gate terminal of the N-type metal oxide semiconductor field effect transistor 311, rather than being electrically connected to the gate terminal of the N-type metal oxide semiconductor field effect transistor 321. Therefore, in the second embodiment, the current generated by the N-type metal oxide semiconductor field effect transistor 41 is a mirror image of the first current I1.

[0055] See also Figure 6 The third embodiment of the voltage under-detection circuit of the present invention is similar to the first embodiment, and is different from the first embodiment in that: (1) the region limiter 4 is not defined (see Figure 1 ) is omitted; and (2) the undervoltage detection circuit also includes five capacitors 71-75.

[0056] In the third embodiment, each of the capacitors 71-75 has a first terminal and a second terminal. The first terminal of the capacitor 71 is electrically connected to the first power rail 8 to receive the power supply voltage V DD . The second end of capacitor 71 is electrically connected to the gate terminal of N-type metal oxide semiconductor field effect transistor 312. The first end of capacitor 72 is electrically connected to the gate terminal of N-type metal oxide semiconductor field effect transistor 322. The second end of capacitor 72 is electrically connected to the second power rail 9 to receive the ground voltage. The first end of capacitor 73 is electrically connected to the gate terminal of P-type metal oxide semiconductor field effect transistor 332. The second end of capacitor 73 is electrically connected to the second power rail 9 to receive the ground voltage. The first end of capacitor 74 is electrically connected to the first power rail 8 to receive the power supply voltage V DD The second end of the capacitor 74 is electrically connected to the common node of the current mirrors 32 and 33. The first end of the capacitor 75 is electrically connected to the output terminal of the inverter 5. The second end of the capacitor 75 is electrically connected to the second power rail 9 to receive the ground voltage. DD When the current comparator 3 is below the range in which the comparison signal COMP can be normally provided, the capacitors 71-75 cooperate to make the comparison signal COMP, the output signal OUT1 and the output signal OUT2 respectively in the logic 1 state, the logic 0 state and the logic 1 state, thereby reducing the undefined area. It should be noted that in other embodiments, some of the capacitors 71-75 can be omitted.

[0057] See also Figure 7 The fourth embodiment of the voltage undervoltage detection circuit of the present invention is similar to the first embodiment, and is different from the first embodiment in that: (1) the first power rail 8 transmits a ground voltage instead of a power supply voltage V DD ; (2) The second power rail 9 is used to transmit the power supply voltage V DD, rather than the voltage at the transmission location; (3) The bipolar junction transistors 23 and 24 are NPN bipolar junction transistors, rather than PNP bipolar junction transistors; (4) The switches 14 and the metal oxide semiconductor field effect transistors 311, 312, 321, 322, 41, and 43 are P-type metal oxide semiconductor field effect transistors, rather than N-type metal oxide semiconductor field effect transistors; (5) The metal oxide semiconductor field effect transistors 331, 332, and 421 are N-type metal oxide semiconductor field effect transistors, rather than P-type metal oxide semiconductor field effect transistors. Therefore, in the fourth embodiment, when n1·I1 > n2·I2, the comparison signal COMP is in the logic 0 state to indicate that the power supply voltage V DD is not large enough, and the switch 14 is not turned on; while when n1·I1 < n2·I2, the comparison signal COMP is in the logic 1 state to indicate that the power supply voltage V DD is large enough, and the switch 14 is turned on.

[0058] It should be noted that the modifications made to the first embodiment to obtain the fourth embodiment can also be made to each of the second and third embodiments.

[0059] It should also be noted that in other embodiments, the following modifications can be made to the fourth embodiment.

[0060] (1) The resistive element 42 is implemented by an active element other than an N-type metal oxide semiconductor field effect transistor, or by a passive element (such as a resistor).

[0061] (2) The inverter 5 is a high-skew inverter, and the inverter 6 is a low-skew inverter, thereby further reducing the undefined region.

[0062] (3) The undefined region limiter 4 is omitted, the inverter 5 is a high-skew inverter, and the inverter 6 is a low-skew inverter.

Claims

1. A voltage under-detection circuit, characterized in that: It contains: A voltage divider receives a power supply voltage and divides the power supply voltage to generate a divided voltage; a voltage-to-current converter electrically connected to the voltage divider to receive the divided voltage, convert the divided voltage into a first current based on a first voltage-to-current conversion function, and convert the divided voltage into a second current based on a second voltage-to-current conversion function, the second voltage-to-current conversion function being different from the first voltage-to-current conversion function; a current comparator electrically connected to the voltage-to-current converter to receive the first current and the second current, and compare the first current and the second current to generate a comparison signal, the comparison signal indicating whether the power supply voltage is large enough; and An undefined region limiter, electrically connected to the current comparator, comprises: a first metal oxide semiconductor field effect transistor having a drain terminal, a source terminal and a gate terminal, wherein the source terminal of the first metal oxide semiconductor field effect transistor receives one of the power supply voltage and the ground voltage, the gate terminal of the first metal oxide semiconductor field effect transistor is electrically connected to the current comparator, and the first metal oxide semiconductor field effect transistor generates a current, and the current generated by the first metal oxide semiconductor field effect transistor is a mirror image of one of the first current and the second current; a resistive element having a first end and a second end, the first end of the resistive element receiving the other of the power supply voltage and the ground voltage, the second end of the resistive element being electrically connected to the drain terminal of the first MOSFET; and The second metal oxide semiconductor field effect transistor is a low threshold voltage metal oxide semiconductor field effect transistor and has a drain terminal, a source terminal and a gate terminal, the drain terminal of the second metal oxide semiconductor field effect transistor is electrically connected to the current comparator, the source terminal of the second metal oxide semiconductor field effect transistor is electrically connected to the source terminal of the first metal oxide semiconductor field effect transistor, and the gate terminal of the second metal oxide semiconductor field effect transistor is electrically connected to the drain terminal of the first metal oxide semiconductor field effect transistor, The voltage-to-current converter comprises: A first resistor having a first end and a second end, wherein the first end of the first resistor receives one of the power supply voltage and a ground voltage; a second resistor having a first end and a second end, wherein the first end of the second resistor is electrically connected to the second end of the first resistor; a first bipolar junction transistor having an emitter terminal, a collector terminal, and a base terminal, wherein the emitter terminal of the first bipolar junction transistor is electrically connected to the second end of the second resistor, the collector terminal of the first bipolar junction transistor is electrically connected to the current comparator and provides the first current, and the base terminal of the first bipolar junction transistor is electrically connected to the voltage divider to receive the divided voltage; and a second bipolar junction transistor having an emitter terminal, a collector terminal and a base terminal, wherein the emitter terminal of the second bipolar junction transistor is electrically connected to the second end of the first resistor, the collector terminal of the second bipolar junction transistor is electrically connected to the current comparator and provides the second current, and the base terminal of the second bipolar junction transistor is electrically connected to the voltage divider to receive the divided voltage; A saturation current of the second bipolar junction transistor is smaller than a saturation current of the first bipolar junction transistor.

2. The undervoltage detection circuit according to claim 1, wherein: The current comparator comprises: A first current mirror having an input terminal and an output terminal, wherein the input terminal of the first current mirror is electrically connected to the voltage-to-current converter to receive the first current; A second current mirror having an input terminal and an output terminal, wherein the input terminal of the second current mirror is electrically connected to the voltage-to-current converter to receive the second current; and a third current mirror, having an input end and an output end, the input end of the third current mirror being electrically connected to the output end of the first current mirror, and the output end of the third current mirror being electrically connected to the output end of the second current mirror; The comparison signal is provided at a common node of the second current mirror and the third current mirror.

3. The undervoltage detection circuit according to claim 1, wherein: The ratio of the divided voltage to the power supply voltage changes with the comparison signal.

4. The undervoltage detection circuit according to claim 3, wherein: The voltage divider comprises: a first resistor having a first end and a second end, the first end of the first resistor receiving one of the power supply voltage and a ground voltage, the second end of the first resistor being electrically connected to the voltage-to-current converter; a second resistor having a first end and a second end, wherein the first end of the second resistor is electrically connected to the second end of the first resistor; a third resistor having a first end and a second end, the first end of the third resistor being electrically connected to the second end of the second resistor, the second end of the third resistor receiving the other of the power supply voltage and the ground voltage; and a switch connected in parallel with the third resistor and having a control terminal, the switch being turned on when the comparison signal indicates that the power supply voltage is large enough, and not turned on when the comparison signal indicates that the power supply voltage is not large enough; The divided voltage is provided at a common node of the first resistor and the second resistor.

5. The undervoltage detection circuit according to claim 1, wherein: When the second MOSFET is turned on, the current comparator causes the comparison signal to indicate that the power supply voltage is not large enough.

6. The undervoltage detection circuit according to claim 5, characterized in that: The resistive element includes a plurality of metal oxide semiconductor field effect transistors; Each of the metal oxide semiconductor field effect transistors of the resistive element is a low threshold voltage metal oxide semiconductor field effect transistor; The metal oxide semiconductor field effect transistor of the resistive element is connected in series between the first end and the second end of the resistive element; Each of the metal oxide semiconductor field effect transistors of the resistive element has a gate terminal, and the gate terminal receives the ground voltage.

7. The undervoltage detection circuit according to claim 1, wherein: It also includes a capacitor having a first end and a second end; The first end of the capacitor receives one of the power supply voltage and the ground voltage corresponding to the power supply voltage being less than that; The second end of the capacitor is electrically connected to a node of the current comparator, and the comparison signal is provided at the node.

8. The undervoltage detection circuit according to claim 1, wherein: It also includes: A first inverter is one of a low-skew inverter and a high-skew inverter and has an input terminal and an output terminal, wherein the input terminal of the first inverter is electrically connected to the current comparator to receive the comparison signal; and The second inverter is the other of the low-skew inverter and the high-skew inverter and has an input terminal and an output terminal, wherein the input terminal of the second inverter is electrically connected to the output terminal of the first inverter.

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