A multiplier and operator circuit

Abstract

The present application provides a multiplier and operator circuit, relating to the field of electronic technology, for reducing the area of the multiplier. The multiplier is used to multiply an M-bit first value by an N-bit second value, and includes: P groups of encoders and W layers of inverse compressors, each of the P groups of encoders including N encoders; each group of encoders is used to encode a portion of the bits in the second value using a positive phase encoding operator or an inverse phase encoding operator, a group selection signal corresponding to each encoder, and a sign control input signal to obtain a partial product term, the group selection signal and the sign control input signal being generated based on the portion of the bits in the first value, and the P groups of encoders encoding to obtain P partial product terms; and the W layers of inverse compressors are used to compress the P partial product terms using an inverse compression operator to obtain two accumulated values, the sum of the two accumulated values being the product of the first value and the second value.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a multiplier and an operator circuit. Background Art

[0002] With the continuous development and maturity of artificial intelligence (AI) technology, AI technology has gradually become popular in communication equipment such as servers and terminals. AI technology places high demands on the computing power of processors in communication equipment, such as central processing units (CPUs), neural-network processing units (NPUs), graphics processing units (GPUs), or digital signal processors (DSPs). As the core computing unit of the processor, the multiplier plays an increasingly important role.

[0003] The existing multiplier architecture is designed based on a standard encoder and a standard adder, such as Figure 1 As shown in the figure, the specific design implementation can be summarized into three steps: (1) using the Radix-4 Booth algorithm in the Radix-4 Booth encoder to encode the first value and the second value to obtain the partial product; (2) compressing the partial product through the Wallace compression tree; (3) summing the two compressed partial products to obtain the multiplication result. Figure 1 In this example, the first and second values are both 16-bit binary numbers, and the multiplication result is a 32-bit binary number. a[15:0] represents the first value, b[15:0] represents the second value, and y[31:0] represents the multiplication result. However, the multiplier implemented based on the Radix-4 Booth algorithm and Wallace compression tree uses a large number of standard encoders and standard adders. These encoders and adders contain a large number of metal-oxide-semiconductor (MOS) transistors, which are large in area, resulting in a large multiplier area. This means that the design and implementation of existing multipliers are relatively complex. Therefore, designing a more implementable multiplier becomes a challenge. Summary of the Invention

[0004] This application provides a multiplier and an operator circuit for reducing the difficulty of implementing the multiplier. To achieve the above-mentioned purpose, this application adopts the following technical solutions:

[0005] In a first aspect, a multiplier is provided for multiplying a first value of M bits by a second value of N bits, where M and N are integers greater than 1. The multiplier comprises: P groups of encoders and W layers of inverse compressors, each of the P groups of encoders comprising N encoders, where W is a positive integer and P is an integer greater than 1; each group of encoders is configured to encode a portion of the bits of the second value, a group selection signal corresponding to each group of encoders, and a sign control input signal using a positive phase encoding operator or an inverse phase encoding operator to obtain a partial product term, the group selection signal and the sign control input signal being generated based on the portion of the bits of the first value, the P groups of encoders encoding to obtain P partial product terms; and the W layers of inverse compressors are configured to compress the P partial product terms using an inverse compression operator to obtain two accumulated values, the sum of the two accumulated values being the product of the first value and the second value. In the above technical solution, the P groups of encoders using the positive phase encoding operator or the inverse phase encoding operator for encoding and the W layers of inverse compressors using the inverse compression operator for compression are relatively simple to implement. For example, this solution has the advantages of small area and low power consumption, so the multiplier has a small area and low power consumption.

[0006] In a possible implementation of the first aspect, each of the N encoders corresponds to a first bit and a second bit in a second value, and the group selection signal includes the first signal and the second signal; each encoder is specifically configured to: use a positive phase encoding operator or a negative phase encoding operator to encode the first bit, the second bit, the group selection signal, and the sign control input signal to obtain an output bit of a partial product term; wherein the first bit and the second bit can be two adjacent bits in the second value, or the same bit in the second value. In the above possible implementation, an encoding method for an encoder is provided, and its implementation scheme is relatively simple, for example, it can reduce the area of the encoder.

[0007] In one possible implementation of the first aspect, when an encoder uses a positive phase encoding operator, the encoder is a positive phase encoder and is specifically configured to perform the following encoding operation: if the first signal and the first bit are both 1, or the second signal and the second bit are both 1, then the output bit obtained by the encoder is the inverse of the sign-controlled input signal; if at least one of the first signal and the first bit is 0, and at least one of the second signal and the second bit is 0, then the output bit obtained by the encoder is the sign-controlled input signal. In the above possible implementation, a positive phase encoder is provided. The implementation scheme of the positive phase encoder is relatively simple, for example, with a small area and low power consumption.

[0008] In one possible implementation of the first aspect, when an encoder uses an inverting encoding operator, the encoder is an inverting encoder and is specifically configured to perform the following encoding operation: if the first signal and the first bit are both 1, or the second signal and the second bit are both 1, the output bit obtained by the encoder is the sign-controlled input signal; if at least one of the first signal and the first bit is 0, and at least one of the second signal and the second bit is 0, the output bit obtained by the encoder is the inverse of the sign-controlled input signal. In the above possible implementation, an inverting encoder is provided. The implementation scheme of the inverting encoder is relatively simple, for example, with a small area and low power consumption.

[0009] In one possible implementation of the first aspect, W is 1, and the W-layer inverse compressor includes: a first-layer inverse compressor; the first-layer inverse compressor is configured to compress each digit in the array of P partial product terms sequentially from low digit to high digit using an inverse compression operator until the remaining bits corresponding to each digit are less than three, thereby obtaining a first compressed array, the first compressed array including two rows, each row corresponding to an accumulated value; compression of each digit is performed on every three bits of the digit; each row in the array of P partial product terms includes one partial product term, and each column includes multiple bits corresponding to the same digit in the P partial product terms. In the above possible implementation, the provided inverse compressor has high compression efficiency.

[0010] In a possible implementation of the first aspect, W is an integer greater than 1, and the W-layer inverse compressor includes: a first layer of inverse compressors to a W-th layer of inverse compressors; the first layer of inverse compressors is configured to compress each digit in the permutation array of P partial product terms sequentially from low digit to high digit using an inverse compression operator until the remaining bits corresponding to each digit are less than three, thereby obtaining a first compressed array; the i-th layer of inverse compressors is configured to compress each digit in the i-1-th compressed array sequentially from low digit to high digit using an inverse compression operator until the remaining bits corresponding to each digit are less than three, thereby obtaining an i-th compressed array, where the value of i ranges from 2 to W; the W-th compressed array includes two rows, each row corresponding to an accumulated value; wherein each layer of inverse compressors compresses each digit for three bits of the digit; each row in the permutation array of P partial product terms includes one partial product term, and each column includes multiple bits corresponding to the same digit in the P partial product terms. In the above possible implementations, the provided W-layer inverse compressor has high compression efficiency.

[0011] In a possible implementation of the first aspect, for every three bits of each digit, each inverting compressor is specifically configured to perform the following compression: if the three bits are all 0, the carry output bit is 1 and the current sum output bit is 1; if the three bits are all 1, the carry output bit is 0 and the current sum output bit is 0; if one of the three bits is 1 and the other two are 0, the carry output bit is 1 and the current sum output bit is 0; if two of the three bits are 1 and the other is 0, the carry output bit is 0 and the current sum output bit is 1. The above possible implementation provides a simple and effective compression method for an inverting compressor.

[0012] In one possible implementation of the first aspect, the phase of the encoding operator used by the encoder corresponding to the same digit is related to the phase of the current sum output bit or carry output bit output by the inverting compressor; wherein the encoder corresponding to the same digit is the encoder that encodes the output bit corresponding to the same digit, and the inverting compressor corresponding to the same digit is the inverting compressor that compresses the three bits of the same digit. This possible implementation provides a method for quickly and efficiently determining the phase of the encoding operator used by the encoder.

[0013] In a possible implementation of the first aspect, the multiplier further includes one or more inverters configured to invert the phase of a current summation output bit and a carry output bit output by one or more inverting compressors in the W-layer inverting compressors, or invert the phase of at least one of three bits input to the one or more inverting compressors. In this possible implementation, the compression efficiency of the W-layer inverting compressor can be improved while ensuring an accurate compression result.

[0014] In a possible implementation manner of the first aspect, the multiplier further includes: a precoder, configured to receive the first value and generate a group selection signal and a sign control input signal according to some bits in the first value.

[0015] In a possible implementation manner of the first aspect, the multiplier further includes: an adder, configured to receive two accumulated values and sum the two accumulated values to obtain a product.

[0016] In a second aspect, an operator circuit is provided, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; wherein the first transistor and the second transistor are coupled in parallel between a power supply terminal and a first node; the third transistor and the fourth transistor are coupled in parallel between the first node and the second node; the fifth transistor and the seventh transistor are coupled in series between the second node and a ground terminal; the sixth transistor and the eighth transistor are coupled in series between the second node and a ground terminal; the control terminals of the third transistor and the fifth transistor are used to receive a first input; the control terminals of the first transistor and the sixth transistor are used to receive a second input; and the control terminals of the fourth transistor and the seventh transistor are used to receive a third input The control terminals of the second and eighth transistors are used to receive the fourth input; the ninth transistor is coupled between the inverted phase of the fifth input and the output terminal, and the control terminal of the ninth transistor is coupled to the second node; the tenth transistor is coupled between the second node and the output terminal, and the control terminal of the tenth transistor is coupled to the inverted phase of the fifth input; the eleventh and thirteenth transistors are coupled in series between the output terminal and the ground terminal; the control terminal of the eleventh transistor is coupled to the second node; the control terminal of the thirteenth transistor is used to receive the inverted phase of the fifth input; the twelfth transistor is coupled between the output terminal and the second node, and the control terminal of the twelfth transistor is used to receive the fifth input; the fourteenth and fifteenth transistors are coupled in series between the power supply terminal and the ground terminal, and the series coupling node of the fourteenth and fifteenth transistors is coupled to the inverted phase of the fifth input; the control terminals of the fourteenth and fifteenth transistors are used to receive the fifth input. In the above technical solution, a positive phase encoding operator circuit is provided, which has a small number of transistors, occupies a small area, and is simple to implement, so that when the operator circuit is applied to a multiplier, the area of the multiplier can be reduced.

[0017] In a possible implementation of the second aspect, the first transistor, the second transistor, the third transistor, the fourth transistor, the ninth transistor, the tenth transistor, and the fourteenth transistor are P-type MOS (PMOS) transistors; and the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fifteenth transistor are N-type MOS (NMOS) transistors. In this possible implementation, the provided operator circuit has a low transistor flip rate when encoding data, thereby reducing the power consumption of the multiplier when the operator circuit is applied to the multiplier.

[0018] According to a third aspect, an operator circuit is provided, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; wherein the first transistor and the second transistor are coupled in parallel between a power supply terminal and a first node; the third transistor and the fourth transistor are coupled in parallel between the first node and the second node; the fifth transistor and the seventh transistor are coupled in series between the second node and a ground terminal; the sixth transistor and the eighth transistor are coupled in series between the second node and a ground terminal; the control terminals of the third transistor and the fifth transistor are used to receive a first input; the control terminals of the first transistor and the sixth transistor are used to receive a second input; and the control terminals of the fourth transistor and the seventh transistor are used to receive a third input. The control terminals of the second and eighth transistors are used to receive the fourth input; the ninth and tenth transistors are coupled in series between the power supply terminal and the output terminal, the control terminal of the ninth transistor is coupled to the inverse of the fifth input, and the control terminal of the tenth transistor is coupled to the second node; the eleventh transistor is coupled between the second node and the output terminal, the control terminal of the eleventh transistor is coupled to the fifth input; the twelfth transistor is coupled between the output terminal and the inverse of the fifth input, the control terminal of the twelfth transistor is coupled to the second node; the thirteenth transistor is coupled between the output terminal and the second node, the control terminal of the thirteenth transistor is coupled to the inverse of the fifth input; the fourteenth and fifteenth transistors are coupled in series between the power supply terminal and the ground terminal, the series coupling node of the fourteenth and fifteenth transistors is coupled to the inverse of the fifth input; the control terminals of the fourteenth and fifteenth transistors are used to receive the fifth input. In the above technical solution, an inversion encoding operator circuit is provided. The inversion encoding operator circuit has a small number of transistors, occupies a small area, and is simple to implement, so that when the operator circuit is applied to a multiplier, the area of the multiplier can be reduced.

[0019] In a possible implementation of the third aspect, the first transistor, the second transistor, the third transistor, the fourth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the fourteenth transistor are PMOS transistors; and the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the twelfth transistor, the thirteenth transistor, and the fifteenth transistor are NMOS transistors. In this possible implementation, the provided operator circuit has a low transistor flip rate when encoding data, thereby reducing power consumption of the multiplier when the operator circuit is applied to the multiplier.

[0020] In a fourth aspect, an operator circuit is provided, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a twenty-second transistor; wherein the first transistor and the second transistor are coupled in parallel between the power supply terminal and the first node; the third transistor is coupled between the first node and the first output terminal; the fourth transistor is coupled between the first output terminal and the second node; the fifth transistor and the sixth transistor are coupled in parallel between the second node and the ground terminal; the seventh transistor is coupled between the power supply terminal and the third node; the eighth transistor is coupled between the third node and the first output terminal; the ninth transistor is coupled between the first output terminal and the fourth node; the tenth transistor is coupled between the fourth node and the ground terminal; the eleventh transistor and the twelfth transistor are coupled in series; The first transistor is coupled to the first output terminal and the second output terminal; the second transistor is coupled to the first output terminal and the second output terminal; the thirteenth transistor and the fourteenth transistor are coupled in series between the second output terminal and the fourth node; the fifteenth transistor, the sixteenth transistor and the seventeenth transistor are coupled in parallel between the power supply terminal and the fifth node; the eighteenth transistor is coupled between the fifth node and the second output terminal; the nineteenth transistor is coupled between the second output terminal and the sixth node; the twentieth transistor, the twenty-first transistor and the twenty-second transistor are coupled in parallel between the sixth node and the ground terminal; the control terminals of the third transistor, the fourth transistor, the twelfth transistor, the thirteenth transistor, the fifteenth transistor and the twenty-second transistor are used to receive the first input; the control terminals of the first transistor, the fifth transistor, the seventh transistor, the tenth transistor, the sixteenth transistor and the twenty-first transistor are used to receive the second input; the control terminals of the second transistor, the sixth transistor, the eighth transistor, the ninth transistor, the eleventh transistor, the fourteenth transistor, the seventeenth transistor and the twenty-second transistor are used to receive the third input; the control terminals of the eighteenth transistor and the nineteenth transistor are coupled to the first output terminal. In the above technical solution, an inverting compression operator circuit is provided. The inverting compression operator circuit has a small number of transistors, occupies a small area, and is simple to implement. Therefore, when the operator circuit is applied to a multiplier, the area of the multiplier can be reduced.

[0021] In a possible implementation of the fourth aspect, the first transistor, the second transistor, the third transistor, the seventh transistor, the eighth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor are PMOS transistors; and the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the thirteenth transistor, the fourteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, and the twenty-second transistor are NMOS transistors. In the above possible implementation, the provided operator circuit has a low transistor flip rate when compressing data, thereby reducing the power consumption of the multiplier when the operator circuit is applied to the multiplier.

[0022] In a fifth aspect, a processor is provided, comprising a multiplier or an operator circuit; wherein the multiplier is the multiplier provided by the first aspect or any possible implementation of the first aspect, and the operator circuit is the operator circuit provided by any possible implementation of the second to fourth aspects or any possible implementation of the second to fourth aspects. Optionally, the processor includes a neural network processing unit.

[0023] In a sixth aspect, a chip is provided, comprising a multiplier or an operator circuit; wherein the multiplier is a multiplier provided by the above-mentioned first aspect or any possible implementation of the first aspect, and the operator circuit is an operator circuit provided by the above-mentioned second to fourth aspects, or any possible implementation of the second to fourth aspects.

[0024] It can be understood that any of the processors or chips provided above include the multiplier or operator circuit provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the multiplier or operator circuit provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 An architectural diagram of a multiplier provided in the prior art;

[0026] Figure 2 A schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of the structure of a multiplier provided in an embodiment of the present application;

[0028] Figure 4 A logic block diagram of a positive phase encoder provided in an embodiment of the present application;

[0029] Figure 5 A logic block diagram of an inverting encoder provided in an embodiment of the present application;

[0030] Figure 6This is a compression example diagram of a W-layer inverse compressor provided in an embodiment of the present application;

[0031] Figure 7 A logic block diagram of an inverting compressor provided in an embodiment of the present application;

[0032] Figure 8 An example diagram of a precoder and an encoder provided in an embodiment of the present application;

[0033] Figure 9 This is a compression example diagram of another W-layer inverse compressor provided in an embodiment of the present application;

[0034] Figure 10 A circuit diagram of a positive phase encoder provided in an embodiment of the present application;

[0035] Figure 11 A circuit diagram of an inverting encoder provided in an embodiment of the present application;

[0036] Figure 12 A circuit diagram of an inverting compressor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple. In addition, the embodiments of this application use words such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order. The word "coupled" is used to indicate electrical connection, including direct connection through wires or connection terminals or indirect connection through other devices. Therefore, "coupling" should be regarded as an electronic communication connection in a broad sense.

[0038] Figure 2 This is a schematic diagram of the structure of a communication device provided in an embodiment of the present application. The communication device may be a terminal or a server. Figure 2The communication device may include a memory 201, a processor 202, a communication interface 203, and a bus 204. The memory 201, processor 202, and communication interface 203 are interconnected via the bus 204. The memory 201 may be used to store data, software programs, and modules, and primarily includes a program storage area and a data storage area. The program storage area may store an operating system, applications required for at least one function, and the data storage area may store data created when the device is in use. The processor 202 is used to control and manage the operation of the communication device, such as executing or running software programs and / or modules stored in the memory 201 and calling data stored in the memory 201 to execute various functions of the device and process data. The communication interface 203 is used to support communication with the device.

[0039] The processor 202 includes, but is not limited to, a central processing unit (CPU), a network processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP), or a general-purpose processor. The processor 202 includes one or more multipliers, such as a multiplier array, which is a device that implements multiplication operations in the processor 202.

[0040] The bus 204 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 2 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0041] To further describe the technical solution, Figure 3 This is a schematic diagram of the structure of a multiplier provided in an embodiment of the present application, which is used to implement the multiplication of an M-bit first value and an N-bit second value, where M and N are integers greater than 1. Figure 3 The multiplier includes: P precoders 301, P groups of encoders 302, W layers of inverse compressors 303, and an adder 304. Each group of encoders 3021 in the P groups of encoders 302 includes N encoders, where W is a positive integer and P is an integer greater than 1. This multiplier is simpler to implement than traditional designs and will be described in detail below.

[0042] Each precoder 3011 in the P precoders 301 is configured to generate a group selection signal and a symbol control input signal based on a portion of the bits in the first value, thereby generating P group selection signals and P symbol control input signals. The P group selection signals and P symbol control input signals correspond one-to-one to the P groups of encoders, i.e., one group selection signal and one symbol control input signal correspond to one group of encoders. The group selection signal can be generated based on two or three adjacent bits in the first value, and the symbol control input signal can be generated based on one bit in the first value, or based on two or three adjacent bits in the first value.

[0043] For example, if the first value is a 4-bit binary number and is represented by a[3:0], and P is equal to 2, then the two precoders can generate two group selection signals and two symbol control input signals based on a[3:0]. Of these two group selection signals, the first group selection signal can be generated based on a[0] and a[1], and the second group selection signal can be generated based on a[1] to a[3]. Of these two symbol control input signals, the first symbol control input signal can be a[1], and the second symbol control input signal can be a[3]. The above a[i] represents the i-th bit from right to left in a[3:0], and i ranges from 0 to 3.

[0044] Each group of encoders 3021 is used to encode the second value, the group selection signal corresponding to the group of encoders and the sign control input signal using a positive phase encoding operator or a negative phase encoding operator to obtain a partial product term. P groups of encoders encode to obtain P partial product terms.

[0045] Each group of encoders 3021 includes N encoders, each of which corresponds to the first and second bits of the second value, and the group selection signal includes the first and second signals. Each encoder can be specifically configured to use a positive phase encoding operator or a negative phase encoding operator to encode the first and second bits of the encoder, the group selection signal, and the sign control input signal to obtain an output bit of a partial product term. The N encoders in each group of encoders 3021 respectively encode to obtain N output bits of a partial product term, i.e., to obtain the partial product term. The first and second bits can be two adjacent bits in the second value, or the same bit in the second value, as will be described in more detail in subsequent embodiments.

[0046] For example, if the second value is a 3-bit binary number and is represented by b[2:0], and N is 3, then each group of encoders 3021 includes 3 encoders. Among these 3 encoders, the first encoder corresponds to two adjacent bits in b[2:0], namely b[0] and b[1]; the second encoder corresponds to two adjacent bits in b[2:0], namely b[1] and b[2]; and the third encoder corresponds to both the first and second bits, namely b[2] in b[2:0]. That is, the last encoder only inputs one bit, b[2], as both the first and second bits. The above b[i] represents the i-th bit from right to left in b[2:0].

[0047] Taking the example where the first value is a[3:0] and the second value is b[2:0] as an example: if the first encoder in the first group of codes corresponds to two adjacent bits in the second value b[2:0] as b[0] and b[1], the corresponding group selection signal is the first group of selection signals (expressed as A and B) generated based on a[0] and a[1], and the corresponding sign control input signal is a[1], then the first encoder can be specifically used to: use a positive phase encoding operator or a negative phase encoding operator to encode b[0], b[1], A, B and a[1] to obtain 1 output bit in the first partial product term.

[0048] Specifically, when an encoder uses a positive phase encoding operator, the encoder can be called a positive phase encoder; when an encoder uses a negative phase encoding operator, the encoder can be called a negative phase encoder. The following describes positive phase encoders and negative phase encoders in detail.

[0049] The positive phase encoder is specifically used to perform the following encoding operation: if the first signal and the first bit are both 1, or the second signal and the second bit are both 1, then the output bit obtained by the positive phase encoder is the inverse of the sign control input signal; if at least one of the first signal and the first bit is 0, and at least one of the second signal and the second bit is 0, then the output bit obtained by the positive phase encoder is the sign control input signal.

[0050] Figure 4 This is a logic block diagram of a positive phase encoder provided in an embodiment of the present application, which includes a coding selection unit, an inversion unit, and a switch control unit. The function of the coding selection unit is: if A and Sel_A are both 1, or B and Sel_B are both 1, then output 1, otherwise output 0; the function of the inversion unit is: invert the output of the coding selection unit; the function of the switch control unit is: if the output of the inversion unit is 1, then output S, if the output of the inversion unit is 0, then output / S. Figure 4In the figure, A represents the first signal, B represents the second signal, Sel_A represents the first bit, Sel_B represents the second bit, S represents the sign control input signal, / S represents the inversion of the sign control input signal, and OUT represents the output bit.

[0051] That is, the positive phase encoder can be specifically encoded according to the logic table shown in Table 1 below, where x in Table 1 represents either "0" or "1", and A, B, Sel_A, Sel_B, S and OUT are Figure 4 A, B, Sel_A, Sel_B, S and OUT are consistent.

[0052] Table 1

[0053] A Sel_A B Sel_B S OUT 1 1 x x 0 1 1 1 x x 1 0 x x 1 1 0 1 x x 1 1 1 0 0 x 0 x 0 0 0 x 0 x 1 1 x 0 x 0 0 0 x 0 x 0 1 1

[0054] The inverting encoder is specifically used to perform the following encoding operation: if the first signal and the first bit are both 1, or the second signal and the second bit are both 1, then the output bit obtained by the inverting encoder is the sign control input signal; if at least one of the first signal and the first bit is 0, and at least one of the second signal and the second bit is 0, then the output bit obtained by the inverting encoder is the inverse of the sign control input signal.

[0055] Figure 5 This is a logic block diagram of an inverting encoder provided in an embodiment of the present application, which includes a coding selection unit, an inversion unit, and a switch control unit. The function of the coding selection unit is: if A and Sel_A are both 1, or B and Sel_B are both 1, then output 1, otherwise output 0; the function of the inversion unit is: invert the output of the coding selection unit; the function of the switch control unit is: if the output of the inversion unit is 0, then output S, and if the output of the inversion unit is 1, then output / S. Figure 5 In the figure, A represents the first signal, B represents the second signal, Sel_A represents the first bit, Sel_B represents the second bit, S represents the sign control input signal, / S represents the inversion of the sign control input signal, and OUT represents the output bit.

[0056] That is, the inverting encoder can be specifically encoded according to the logic table shown in Table 2 below, where x in Table 2 represents either "0" or "1", and A, B, Sel_A, Sel_B, S and OUT are Figure 5 A, B, Sel_A, Sel_B, S and OUT are consistent.

[0057] Table 2

[0058] A Sel_A B Sel_B S OUT 1 1 x x 0 0 1 1 x x 1 1 x x 1 1 0 0 x x 1 1 1 1 0 x 0 x 0 1 0 x 0 x 1 0 x 0 x 0 0 1 x 0 x 0 1 0

[0059] The W-layer inverse compressor 303 is used to compress P partial product terms using an inverse compression operator to obtain two accumulated values.

[0060] Specifically, when W is 1, the W-layer inverse compressor 303 includes: a first-layer inverse compressor, used to compress each digit in the array of P partial product terms in order from low digit to high digit using an inverse compression operator until the remaining bits corresponding to each digit are less than three, thereby obtaining a first compressed array including two rows, each row corresponding to an accumulated value. When W is an integer greater than 1, the W-layer inverse compressor 303 includes: a first-layer inverse compressor to a W-th-layer inverse compressor; the first-layer inverse compressor is used to compress each digit in the arrangement array of P partial product terms using an inverse compression operator in order from low digit to high digit until the remaining bits corresponding to each digit are less than three, thereby obtaining a first compressed array; the i-th-layer inverse compressor is used to compress each digit in the i-1-th compressed array using an inverse compression operator in order from low digit to high digit until the remaining bits corresponding to each digit are less than three, thereby obtaining an i-th compressed array, where the value range of i is from 2 to W, and the W-th compressed array includes two rows, each row corresponding to an accumulated value.

[0061] Each layer of inverted compressors compresses each digit for the three bits associated with that digit, and does not compress the carry output bit and the current summation bit obtained by compression by the inverted compressors in that layer. Each row of the array of P partial product terms includes one partial product term, and each column includes multiple bits of the P partial product terms corresponding to the same digit. Each digit is compressed for the three bits associated with that digit; each row of the array of P partial product terms includes one partial product term, and each column includes multiple bits of the P partial product terms corresponding to the same digit.

[0062] For example, assuming that the P group of encoders encodes 8 partial product terms, each of which includes 16 bits, the array of these 8 partial product terms can be as follows: Figure 6 As shown in (a), PP[1] to PP[8] represent 8 partial product terms, 20, 2 1 , 2 1 ,…,2 32 Represents different digits. A digit refers to the output of the W-layer inverting compressor. Similar to the units, tens, or hundreds digits in decimal, this digit represents a single bit in the binary value of the output. For example, if the output of the W-layer inverting compressor is a 32-bit binary number, the output consists of 32 digits. In contrast, a bit corresponds to either 0 or 1, representing a single binary piece of information. A digit can be considered a single bit in the output of the W-layer inverting compressor.

[0063] For ease of understanding, Figure 6 (a) in the conversion to Figure 6 As shown in (b), the compression process of each layer of the W-layer inverse compressor 303 is illustrated. Specifically, the output result has 32 digits. The first layer of inverse compressor is specifically used to 4 to 2 29 The bits corresponding to each digit in the digit are compressed every three bits, and bits less than three bits are retained, divided by 2 4 to 2 29 The bits corresponding to other digits except 1 are less than three bits and are also retained. Figure 6 Each solid rectangular box in (b) can be used to represent an inverse compressor in the first layer of inverse compressors. The first compressed array obtained by the first layer of inverse compressors is as follows: Figure 6 As shown in (c), the represents the current sum output bit of the first layer inverting compressor output, ○ represents the carry output bit of the first layer inverting compressor output; the second layer inverting compressor is specifically used to compress the 2 in the first compression array 6 to 2 23 , and 2 26 The bits corresponding to each digit in the digit are compressed every three bits, and bits less than three bits are retained, divided by 2 6 to 2 23 , and 2 26 The bits corresponding to other digits except 1 are less than three bits and are also retained. Figure 6 Each rectangular box in (c) can be used to represent an inverse compressor in the second layer of inverse compressors. The second compressed array obtained by the second layer of inverse compressors is as follows: Figure 6 As shown in (d) in the figure, represents the current summed output bit of the second-layer inverted compressor, and ◎ represents the carry output bit of the second-layer inverted compressor. The specific compression process of the subsequent third-layer inverted compressor to the W-th-layer inverted compressor is similar to the specific compression process of the first-layer inverted compressor and the second-layer inverted compressor described above, and will not be repeated here in this embodiment of the present application.

[0064] For every three bits of each digit, each inverting compressor is specifically used to perform the following compression: if the three bits are all 0, the carry output bit is 1 and the current sum output bit is 1; if the three bits are all 1, the carry output bit is 0 and the current sum output bit is 0; if one of the three bits is 1 and the other two bits are 0, the carry output bit is 1 and the current sum output bit is 0; if two of the three bits are 1 and the other bit is 0, the carry output bit is 0 and the current sum output bit is 1.

[0065] Among them, the carry output bit is the output bit pointing to the next digit of the current compressed digit, and the current sum output bit is the output bit after the current compressed digit is compressed. For example, if the current compressed digit is 2 5 、The next digit of the current compressed digit is 2 6 , for 2 5 If all three bits are 0, then the compressed 5 Corresponding to 1 1, 2 6 A corresponding 1 is generated.

[0066] Figure 7 A logic block diagram of an inverting compressor provided in an embodiment of the present application, the logic block diagram includes an inverting carry output unit and an inverting summing output unit. The function of the inverting carry output unit is: if at least 2 of Ai, Bi and Ci are valid (valid can be 1 or 0), then the output is invalid (if valid is 1, then invalid is 0, if valid is 0, then invalid is 1), otherwise the output is valid. The function of the inverting summing output unit is: if there are 2 valid or all invalid among Ai, Bi and Ci, then the output is valid, otherwise the output is invalid, and the nCip1 input to the inverting summing output unit can be used to distinguish whether Ai, Bi and Ci are 2 valid or all invalid when valid. The above Figure 7 In the equation, Ai, Bi, and Ci represent the three input bits, nCip1 represents the carry output bit, and nSi represents the current summation output bit. That is, each layer of the inverting compressor can perform compression according to the logic table shown in Table 3 below. In Table 3, Ai, Bi, and Ci represent the three input bits, nCip1 represents the carry output bit, and nSi represents the current summation output bit.

[0067] Table 3

[0068]

[0069]

[0070] Furthermore, the multiplier may also include: one or more inverters, used to invert the phase of the current sum output bit and carry output bit output by one or more inverting compressors in the W-layer inverting compressor 303, or to invert the phase of at least one of the three bits input to the one or more inverting compressors.

[0071] Among them, the W-layer inverting compressor 303 can include multiple layers of inverting compressors, each layer of the multiple layers of inverting compressors can include at least one inverting compressor, the output phase of each inverting compressor can be set according to requirements, and the output phase of each inverting compressor is opposite to the input phase, so that the input phase of each inverting compressor is also set.

[0072] It should be noted that the output phase of an inverting compressor may refer to the phase of the current sum output bit and carry output bit output by the inverting compressor, and the phases of the current sum output bit and carry output bit are the same, that is, both are positive or negative. The input phase of an inverting compressor may refer to the phase of the three bits input to the inverting compressor, and the phases of the three bits are the same, that is, both are positive or negative.

[0073] When the output phase of one or more inverting compressors in the W-layer inverting compressors 303 differs from the set output phase, the one or more inverters may be used to invert the phase of the current summation output bit and carry output bit output by the one or more inverting compressors to make them consistent with the set output phase. Similarly, when the phase of at least one of the three bits input to the one or more inverting compressors differs from the set input phase, the one or more inverters may be used to invert the phase of at least one of the three bits input to the one or more inverting compressors to make them consistent with the set input phase.

[0074] In one possible implementation, the output phase of at least one inverted compressor included in each layer of inverted compressors can be set as follows: the output phase of the inverted compressor in the last layer is set to positive phase, the output phase of the inverted compressor in the second-to-last layer is set to negative phase, the output phase of the inverted compressor in the third-to-last layer is set to positive phase, and so on, until the output phase of the inverted compressor in the first layer is set. The first layer of inverted compressors herein may refer to the inverted compressor in the topmost layer when compressing multiple bits corresponding to each digit from top to bottom. The second layer of inverted compressors may refer to the inverted compressor in the next-to-top layer, and so on. For example, if the W-layer inverted compressor 303 includes four layers of inverted compressors, the output phase of the inverted compressor in the fourth layer may be set to positive phase, the output phase of the inverted compressor in the third layer is set to negative phase, the output phase of the inverted compressor in the second layer is set to positive phase, and the output phase of the inverted compressor in the first layer is set to negative phase.

[0075] Optionally, when the output phase or input phase of a certain inverting compressor itself is inconsistent with the set output phase or input phase, and at least three inverters are required to invert the phase to meet the requirements, the output phase setting of the inverting compressor can be locally adjusted to reduce the number of inverters required. For example, when the output phase of a certain inverting compressor is set to positive phase (the input phase of the inverting compressor is set to negative phase), if the output phase of the inverting compressor itself is positive phase and the phases of the three bits input to the inverting compressor are also positive phase, the inverting compressor needs three inverters to invert the phases of the three bits respectively to meet the set output phase and input phase requirements; at this time, by resetting the output phase of the inverting compressor to negative phase (the input phase of the inverting compressor is set to positive phase), the inverting compressor only needs two inverters to invert the output phases of two output bits (i.e., the current sum output bit and the carry output bit) to meet the set output phase and input phase requirements.

[0076] Furthermore, the phase of the encoding operator used by at least one encoder in the P group of encoders 302 is related to the phase of the current summed output bit or carry output bit output by at least one layer of inverse compressors in the W layers of inverse compressors 303. Optionally, the phase of the encoding operator used by each encoder in the at least one encoder is set to be the same as the input phase of the inverse compressor to which it is connected. The phase of the encoding operator used by each encoder can be positive or negative. When the phase of the encoding operator used by an encoder is positive (i.e., a positive encoding operator is used), the encoder is the above-mentioned positive encoder; when the phase of the encoding operator used by an encoder is negative (i.e., an negative encoding operator is used), the encoder is the above-mentioned negative encoder.

[0077] Adder 304 is configured to receive the two accumulated values and sum them to obtain the product. After W-layer inverse compressor 303 compresses the P partial product terms to obtain the two accumulated values, W-layer inverse compressor 303 may send the two accumulated values to adder 304. Upon receiving the two accumulated values, adder 304 sums them to obtain the product of the first value and the second value.

[0078] For ease of understanding, the following uses the first value a[10:0] and the second value b[12:0] as an example to illustrate the multiplier described in this application. Figure 8 As shown, the multiplier may include 6 precoders, 6 groups of encoders and 3 layers of inverse compressors.

[0079] Specifically, the first precoder is used to generate group selection signals S0 and S1, and symbol control input signal a[1] according to a[0] and a[1]; the second precoder is used to generate group selection signals S2 and S3, and symbol control input signal a[3] according to a[1], a[2] and a[3]; the third precoder is used to generate group selection signals S4 and S5, and symbol control input signal a[5] according to a[3], a[4] and a[5]; the fourth precoder is used to generate group selection signals S6 and S7, and symbol control input signal a[7] according to a[5], a[6] and a[7]; the fifth precoder is used to generate group selection signals S8 and S9, and symbol control input signal a[9] according to a[7], a[8] and a[9]; the sixth precoder is used to generate group selection signal S10, and symbol control input signal S_11 according to a[9] and a

[10] . Correspondingly, the first group of encoders is used to encode b[12:0], S0, S1 and a[1] to obtain the first partial product term PP[1]; the second group of encoders is used to encode b[12:0], S2, S3 and a[3] to obtain the second partial product term PP[2]; the third group of encoders is used to encode b[12:0], S4, S5 and a[5] to obtain the third partial product term PP[3]; the fourth group of encoders is used to encode b[12:0], S6, S7 and a[7] to obtain the fourth partial product term PP[4]; the fifth group of encoders is used to encode b[12:0], S8, S9 and a[9] to obtain the fifth partial product term PP[5]; the sixth group of encoders is used to encode b[12:0], S10 and S_11 to obtain the sixth partial product term PP[6]. Each encoder in each group of encoders is used to encode one or two bits in b[12:0], as well as the corresponding group selection signal and symbol control input signal. For details, see Figure 8 Finally, the permutation array corresponding to these 6 partial product terms PP[1] to PP[6] can be shown as Figure 9 As shown, according to the relevant description of the W-layer inverse compressor 303 in the above multiplier, the 3-layer inverse compressor can be used to Figure 9 The array shown is compressed. The detailed compression process is the same as above. Figure 6 The relevant descriptions in are similar, and the embodiments of the present application will not be repeated here.

[0080] In the multiplier provided in the embodiment of the present application, the P precoders may include precoders with different structures, such as Figure 8The first precoder in the embodiment includes a NOT gate and an AND gate, the second to fifth precoders include an XOR gate, an XNOR gate, and a NOR gate, and the sixth precoder includes an XOR gate and an AND gate. In addition, in the embodiment of the present application, the structure of the first encoder of the same group of encoders can be different from that of other encoders, and the structures of encoders in different groups can also be different. For example, Figure 8 The first encoder of the first to fifth groups of encoders includes an AND gate and an XOR gate, the second to thirteenth encoders are positive phase encoders or negative phase encoders, and each encoder of the sixth group of encoders includes an AND gate and an XOR gate.

[0081] It should be noted that Figure 8 PP[1]_i (where i ranges from 1 to 14) represents the i-th bit of the first partial product term PP[1], A represents the first signal, B represents the second signal, Sel_A represents the first bit, Sel_B represents the second bit, S represents the sign control input signal, and OUT represents the output bit.

[0082] Figure 10 This is a schematic diagram of the structure of a positive phase encoding operator circuit provided in an embodiment of the present application. The positive phase encoding operator circuit may also be referred to as a positive phase encoder. The positive phase encoder includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15.

[0083] The first transistor M1 and the second transistor M2 are coupled in parallel between the power supply terminal and the first node ①; the third transistor M3 and the fourth transistor M4 are coupled in parallel between the first node ① and the second node ②; the fifth transistor M5 and the seventh transistor M7 are coupled in series between the second node ② and the ground terminal; and the sixth transistor M6 and the eighth transistor M8 are coupled in series between the second node ② and the ground terminal. The control terminals of the third transistor M3 and the fifth transistor M5 are used to receive the first input A; the control terminals of the first transistor M1 and the sixth transistor M6 are used to receive the second input Sel_A; the control terminals of the fourth transistor M4 and the seventh transistor M7 are used to receive the third input B; and the control terminals of the second transistor M2 and the eighth transistor M8 are used to receive the fourth input Sel_B.

[0084] The ninth transistor M9 is coupled between the inverted phase / S of the fifth input S and the output terminal OUT. The control terminal of the ninth transistor M9 is coupled to the second node ②, where the signal at the second node ② is / Y. The tenth transistor M10 is coupled between the second node ② and the output terminal OUT. The control terminal of the tenth transistor M10 is coupled to the inverted phase / S of the fifth input S. The eleventh transistor M11 and the thirteenth transistor M13 are coupled in series between the output terminal OUT and the ground terminal. The control terminal of the eleventh transistor M11 is coupled to the second node ②. The control terminal of the thirteenth transistor M13 is configured to receive the inverted phase / S of the fifth input S. The twelfth transistor M12 is coupled between the output terminal OUT and the second node ②. The control terminal of the twelfth transistor M12 is configured to receive the fifth input S. The fourteenth transistor M14 and the fifteenth transistor M15 are coupled in series between the power supply terminal and the ground terminal. The series coupling node of the fourteenth transistor M14 and the fifteenth transistor M15 is coupled to the inverted phase / S of the fifth input S. The control terminals of the fourteenth transistor M14 and the fifteenth transistor M15 are configured to receive the fifth input S.

[0085] In an embodiment of the present application, the above-mentioned first input A to fifth input S can respectively be the first signal, first bit, second signal, second bit and sign control input signal in the relevant description of the positive phase encoder in the above-mentioned multiplier embodiment.

[0086] Optionally, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the ninth transistor M9, the tenth transistor M10, and the fourteenth transistor M14 are PMOS transistors; the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fifteenth transistor M15 are NMOS transistors. Accordingly, the control terminal may specifically refer to the gate of the corresponding PMOS transistor or NMOS transistor.

[0087] It should be noted that the first transistor M1 to the fifteenth transistor M15 in the above examples may be MOS transistors or bipolar transistors. Figure 10 The types of transistors shown in the figure are merely exemplary and do not limit the embodiments of the present application.

[0088] Figure 11This is a schematic diagram of the structure of an inverting encoding operator circuit provided in an embodiment of the present application. The inverting encoding operator circuit may also be referred to as an inverting encoder. The inverting encoder includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15.

[0089] Among them, the first transistor M1 and the second transistor M2 are coupled in parallel between the power supply terminal and the first node ①; the third transistor M3 and the fourth transistor M4 are coupled in parallel between the first node ① and the second node ②; the fifth transistor M5 and the seventh transistor M7 are coupled in series between the second node ② and the ground terminal; the sixth transistor M6 and the eighth transistor M8 are coupled in series between the second node ② and the ground terminal; the control terminals of the third transistor M3 and the fifth transistor M5 are used to receive the first input A; the control terminals of the first transistor M1 and the sixth transistor M6 are used to receive the second input Sel_A; the control terminals of the fourth transistor M4 and the seventh transistor M7 are used to receive the third input B; and the control terminals of the second transistor M2 and the eighth transistor M8 are used to receive the fourth input Sel_B.

[0090] The ninth transistor M9 and the tenth transistor M10 are coupled in series between the power supply terminal and the output terminal OUT. The control terminal of the ninth transistor M9 is coupled to the inverted phase / S of the fifth input S. The control terminal of the tenth transistor M10 is coupled to the second node ②, where the signal at the second node ② is / Y. The eleventh transistor M11 is coupled between the second node ② and the output terminal OUT. The control terminal of the eleventh transistor M11 is coupled to the fifth input S. The twelfth transistor M12 is coupled between the output terminal OUT and the inverted phase / S of the fifth input S. The control terminal of the twelfth transistor M12 is coupled to the second node ②. The thirteenth transistor M13 is coupled between the output terminal OUT and the second node ②. The control terminal of the thirteenth transistor M13 is coupled to the inverted phase / S of the fifth input S. The fourteenth transistor M14 and the fifteenth transistor M15 are coupled in series between the power supply terminal and the ground terminal. The series coupling node of the fourteenth transistor M14 and the fifteenth transistor M15 is coupled to the inverted phase / S of the fifth input S. The control terminals of the fourteenth transistor M14 and the fifteenth transistor M15 are used to receive the fifth input S.

[0091] In an embodiment of the present application, the first input A to the fifth input S may respectively be the first signal, the first bit, the second signal, the second bit and the sign control input signal in the relevant description of the inverting encoder in the above multiplier embodiment.

[0092] Optionally, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the fourteenth transistor M14 are PMOS transistors; and the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the twelfth transistor M12, the thirteenth transistor M13, and the fifteenth transistor M15 are NMOS transistors. Accordingly, the control terminal may specifically refer to the gate of the corresponding PMOS transistor or NMOS transistor.

[0093] It should be noted that the first transistor M1 to the fifteenth transistor M15 in the above examples may be MOS transistors or bipolar transistors. Figure 11 The types of transistors shown in the figure are merely exemplary and do not limit the embodiments of the present application.

[0094] Figure 12 This is a schematic diagram of the structure of an inverting compression operator circuit provided in an embodiment of the present application, which may also be referred to as an inverting compressor. The inverting compressor includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, and a twenty-second transistor M22.

[0095] Among them, the first transistor M1 and the second transistor M2 are coupled in parallel between the power supply terminal and the first node ①; the third transistor M3 is coupled between the first node ① and the first output terminal nCip1; the fourth transistor M4 is coupled between the first output terminal nCip1 and the second node ②; the fifth transistor M5 and the sixth transistor M6 are coupled in parallel between the second node ② and the ground terminal; the seventh transistor M7 is coupled between the power supply terminal and the third node ③; the eighth transistor M8 is coupled between the third node ③ and the first output terminal nCip1; the ninth transistor M9 is coupled between the first output terminal nCip1 and the fourth node ④; the tenth transistor M10 is coupled between the fourth node ④ and the ground terminal; the eleventh transistor M11 is coupled between the fourth node ④ and the ground terminal; The transistor M11 and the twelfth transistor M12 are coupled in series between the third node ③ and the second output terminal nSi; the thirteenth transistor M13 and the fourteenth transistor M14 are coupled in series between the second output terminal nSi and the fourth node ④; the fifteenth transistor M15, the sixteenth transistor M16 and the seventeenth transistor M17 are coupled in parallel between the power supply terminal and the fifth node ⑤; the eighteenth transistor M18 is coupled between the fifth node ⑤ and the second output terminal nSi; the nineteenth transistor M19 is coupled between the second output terminal nSi and the sixth node ⑥; the twentieth transistor M20, the twenty-first transistor M21 and the twenty-second transistor M22 are coupled in parallel between the sixth node ⑥ and the ground terminal.

[0096] Control terminals of the third transistor M3, the fourth transistor M4, the twelfth transistor M12, the thirteenth transistor M13, the fifteenth transistor M15 and the twentieth transistor M20 are used to receive the first input Ai; control terminals of the first transistor M1, the fifth transistor M5, the seventh transistor M7, the tenth transistor M10, the sixteenth transistor M16 and the twenty-first transistor M21 are used to receive the second input Bi; control terminals of the second transistor M2, the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, the eleventh transistor M11, the fourteenth transistor M14, the seventeenth transistor M17 and the twenty-second transistor M22 are used to receive the third input Ci; control terminals of the eighteenth transistor M18 and the nineteenth transistor M19 are coupled to the first output terminal nCip1.

[0097] In an embodiment of the present application, the above-mentioned first input Ai, second input Bi and third input Ci can be the three bits in the relevant description of the inverting compressor in the above-mentioned multiplier embodiment, the first output terminal nCip1 can be used to output the carry output bit of the inverting compressor, and the second output terminal nSi can be used to output the current sum output bit of the inverting compressor.

[0098] Optionally, the first transistor M1, the second transistor M2, the third transistor M3, the seventh transistor M7, the eighth transistor M8, the eleventh transistor M11, the twelfth transistor M12, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18 are PMOS transistors; the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, the thirteenth transistor M13, the fourteenth transistor M14, the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21, and the twenty-second transistor M22 are NMOS transistors. Accordingly, the control terminal may specifically refer to the gate of the corresponding PMOS transistor or NMOS transistor.

[0099] It should be noted that the first transistor M1 to the twenty-second transistor M22 in the above examples may be MOS transistors, or may be replaced by bipolar transistors. Figure 12 The types of transistors shown in the figure are merely exemplary and do not limit the embodiments of the present application.

[0100] The embodiment of the present application compares the multiplier using the positive phase encoder, negative phase encoder and negative phase compressor provided above with the existing multiplier based on the standard encoder and standard adder, as shown in Tables 4 and 5 below. As an embodiment of the present application, it is not limited to the following specific parameter values.

[0101] Table 4

[0102]

[0103] As can be seen from Table 4, the number of transistors used by each standard encoder is 22, the occupied area is 0.2736, and the area benefit is 1.18; the number of transistors used by each positive phase encoder or negative phase encoder is 15, the occupied area is 0.23256, and the area benefit is 1; the number of transistors used by each standard adder is 28, the occupied area is 0.2736, and the area benefit is 1.10; the number of transistors used by each negative phase compressor is 24, the occupied area is 0.24816, and the area benefit is 1. Therefore, the multiplier provided in the embodiment of the present application has a small area.

[0104] Table 5

[0105]

[0106]

[0107] As can be seen from Table 5, the standard encoder flips 4 times per bit of data encoded, has a static power consumption of 0.44522, a static power consumption benefit of 1.18, and a dynamic power consumption benefit of 1.09. The positive phase encoder or the inverted phase encoder flips 3 times per bit of data encoded, has a static power consumption of 0.4084, and the static power consumption and dynamic power consumption benefits are both 1. The standard adder flips 4 times per bit of data compressed, has a static power consumption of 0.57685, a static power consumption benefit of 1.10, and a dynamic power consumption benefit of 1.80. The inverted phase compressor flips 2 times per bit of data compressed, has a static power consumption of 0.32122, and the static power consumption and dynamic power consumption benefits are both 1. Therefore, the multiplier provided in the embodiment of the present application has low power consumption.

[0108] The encoder in the multiplier provided in the embodiments of the present application uses a positive-phase encoding operator or a negative-phase encoding operator for encoding, i.e., the multiplier uses a positive-phase encoder or a negative-phase encoder for encoding, and the compressor uses a negative-phase compressor for compression. This implementation is relatively simple, for example, and can reduce the number of MOS transistors in the multiplier, thereby reducing the area of the multiplier. Furthermore, the encoder or compressor performs relatively few flips per bit of data encoded or compressed by the multiplier, thereby reducing the power consumption of the multiplier.

[0109] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A processor, characterized in that: The method comprises one or more multipliers, wherein each multiplier is configured to multiply an M-bit first value by an N-bit second value, where M and N are integers greater than 1, and the multiplier comprises: P groups of encoders and W layers of inverse compressors, wherein each group of the P groups of encoders comprises N encoders, W is a positive integer, and P is an integer greater than 1; Each group of encoders is configured to encode a portion of the bits in the second value, a group selection signal corresponding to each group of encoders, and a sign control input signal using a positive phase encoding operator or a negative phase encoding operator to obtain a partial product term, wherein the group selection signal and the sign control input signal are generated based on the portion of the bits in the first value, and the P groups of encoders encode to obtain P partial product terms; The W-layer inverse compressor is used to compress the P partial product terms using an inverse compression operator to obtain two accumulated values, and the sum of the two accumulated values is the product of the first value and the second value.

2. The processor according to claim 1, wherein: Each encoder among the N encoders corresponds to the first bit and the second bit in the second value, and the group selection signal includes the first signal and the second signal; each encoder is specifically used to: use a positive phase encoding operator or a negative phase encoding operator to encode the first bit, the second bit, the group selection signal and the sign control input signal to obtain an output bit of a partial product term.

3. The processor according to claim 2, wherein: When an encoder uses a positive phase encoding operator, the encoder is a positive phase encoder and is specifically used to perform the following encoding operations: If the first signal and the first bit are both 1, or the second signal and the second bit are both 1, the output bit obtained by the encoder is the inverse of the sign control input signal; If at least one of the first signal and the first bit is 0, and at least one of the second signal and the second bit is 0, the output bit obtained by the encoder is the sign control input signal.

4. The processor according to claim 2, wherein: When an encoder uses an inverting encoding operator, the encoder is an inverting encoder and is specifically used to perform the following encoding operations: If the first signal and the first bit are both 1, or the second signal and the second bit are both 1, the output bit obtained by the encoder is the sign control input signal; If at least one of the first signal and the first bit is 0, and at least one of the second signal and the second bit is 0, the output bit obtained by the encoder is the inverse of the sign control input signal. The processor according to claim 1 , wherein: W is 1, and the W-layer inverting compressor includes: a first-layer inverting compressor; The first-layer inverse compressor is configured to compress each digit in the array of the P partial product terms sequentially from a low digit to a high digit using the inverse compression operator until the number of remaining bits corresponding to each digit is less than three, thereby obtaining a first compressed array comprising two rows, each row corresponding to an accumulated value; Compression of each digit is performed on every three bits of the digit; each row in the array of the P partial product terms includes a partial product term, and each column includes multiple bits corresponding to the same digit in the P partial product terms. The processor according to claim 1 , wherein: W is an integer greater than 1, and the W-layer inverse compressor includes: a first-layer inverse compressor to a W-th-layer inverse compressor; The first-layer inverse compressor is configured to compress each digit in the array of the P partial product terms sequentially from low digit to high digit using the inverse compression operator until the number of remaining bits corresponding to each digit is less than three, thereby obtaining a first compressed array; The i-th layer of inverse compressor is used to compress each digit in the i-1-th compression array using the inverse compression operator in order from low digit to high digit until the remaining bits corresponding to each digit are less than three, thereby obtaining the i-th compression array, where the value of i ranges from 2 to W; The Wth compressed array includes two rows, each row corresponding to an accumulated value; In which, the compression of each digit by the inverting compressor at each layer is performed on the three bits of the digit; each row in the array of the P partial product terms includes a partial product term, and each column includes multiple bits corresponding to the same digit in the P partial product terms.

7. The processor according to claim 5 or 6, characterized in that For each of the three bits of the digit, each inverse compressor is specifically configured to perform the following compression: If all three bits are 0, the carry output bit is 1 and the current sum output bit is 1; If all three bits are 1, the carry output bit is 0 and the current sum output bit is 0; If one of the three bits is 1 and the other two bits are 0, the carry output bit is 1 and the current sum output bit is 0; If two of the three bits are 1 and the other bit is 0, the carry output bit is 0 and the current sum output bit is 1.

8. The processor according to claim 7, wherein: The phase of the encoding operator used by the encoder corresponding to the same digit is related to the phase of the current sum output bit or carry output bit output by the inverting compressor; The encoder corresponding to the same digit refers to an encoder that encodes and obtains the output bits corresponding to the same digit, and the inverse compressor corresponding to the same digit refers to an inverse compressor that compresses three bits of the same digit.

9. The processor according to claim 8, wherein: The multiplier further comprises: One or more inverters, used to invert the phase of the current sum output bit and carry output bit output by one or more inverting compressors in the W layer, or to invert the phase of at least one of the three bits input to the one or more inverting compressors.

10. The processor according to any one of claims 1 to 9, characterized in that: The multiplier further comprises: The precoder is configured to receive the first value and generate the group selection signal and the symbol control input signal according to the portion of bits in the first value.

11. The processor according to any one of claims 1 to 9, characterized in that: The multiplier further comprises: An adder is configured to receive the two accumulated values and sum the two accumulated values to obtain the product.

12. An operator circuit in a processor, characterized in that: include: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; wherein, The first transistor and the second transistor are coupled in parallel between a power supply terminal and a first node; The third transistor and the fourth transistor are coupled in parallel between the first node and the second node; The fifth transistor and the seventh transistor are coupled in series between the second node and a ground terminal; The sixth transistor and the eighth transistor are coupled in series between the second node and the ground terminal; The control terminals of the third transistor and the fifth transistor are used to receive a first input; The control terminals of the first transistor and the sixth transistor are configured to receive a second input; The control terminals of the fourth transistor and the seventh transistor are used to receive a third input; The control terminals of the second transistor and the eighth transistor are used to receive a fourth input; The ninth transistor is coupled between the inverting terminal and the output terminal of the fifth input, and the control terminal of the ninth transistor is coupled to the second node; The tenth transistor is coupled between the second node and the output terminal, and the control terminal of the tenth transistor is coupled to the inverse phase of the fifth input; The eleventh transistor and the thirteenth transistor are coupled in series between the output terminal and the ground terminal; The control terminal of the eleventh transistor is coupled to the second node; The control terminal of the thirteenth transistor is used to receive the inverse of the fifth input; The twelfth transistor is coupled between the output terminal and the second node, and the control terminal of the twelfth transistor is used to receive the fifth input; The fourteenth transistor and the fifteenth transistor are coupled in series between the power supply terminal and the ground terminal, and a series coupling node between the fourteenth transistor and the fifteenth transistor is coupled to the inverting phase of the fifth input; The control terminals of the fourteenth transistor and the fifteenth transistor are configured to receive the fifth input.

13. The operator circuit according to claim 12, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the ninth transistor, the tenth transistor and the fourteenth transistor are PMOS transistors; The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fifteenth transistor are NMOS transistors.

14. An operator circuit in a processor, characterized in that: include: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; wherein, The first transistor and the second transistor are coupled in parallel between a power supply terminal and a first node; The third transistor and the fourth transistor are coupled in parallel between the first node and the second node; The fifth transistor and the seventh transistor are coupled in series between the second node and a ground terminal; The sixth transistor and the eighth transistor are coupled in series between the second node and the ground terminal; The control terminals of the third transistor and the fifth transistor are used to receive a first input; The control terminals of the first transistor and the sixth transistor are configured to receive a second input; The control terminals of the fourth transistor and the seventh transistor are used to receive a third input; The control terminals of the second transistor and the eighth transistor are configured to receive a fourth input; The ninth transistor and the tenth transistor are coupled in series between the power supply terminal and the output terminal, the control terminal of the ninth transistor is coupled to the inverse phase of the fifth input, and the control terminal of the tenth transistor is coupled to the second node; The eleventh transistor is coupled between the second node and the output terminal, and the control terminal of the eleventh transistor is coupled to the fifth input; The twelfth transistor is coupled between the output terminal and the inverse phase of the fifth input, and the control terminal of the twelfth transistor is coupled to the second node; The thirteenth transistor is coupled between the output terminal and the second node, and the control terminal of the thirteenth transistor is coupled to the inverse phase of the fifth input; The fourteenth transistor and the fifteenth transistor are coupled in series between the power supply terminal and the ground terminal, and a series coupling node between the fourteenth transistor and the fifteenth transistor is coupled to the inverting phase of the fifth input; The control terminals of the fourteenth transistor and the fifteenth transistor are configured to receive the fifth input.

15. The operator circuit according to claim 14, characterized in that The first transistor, the second transistor, the third transistor, the fourth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the fourteenth transistor are PMOS transistors; The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the twelfth transistor, the thirteenth transistor, and the fifteenth transistor are NMOS transistors.

16. An operator circuit in a processor, characterized in that: include: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a twenty-second transistor; wherein, The first transistor and the second transistor are coupled in parallel between a power supply terminal and a first node; The third transistor is coupled between the first node and the first output terminal; The fourth transistor is coupled between the first output terminal and a second node; The fifth transistor and the sixth transistor are coupled in parallel between the second node and a ground terminal; The seventh transistor is coupled between the power supply terminal and the third node; The eighth transistor is coupled between the third node and the first output terminal; The ninth transistor is coupled between the first output terminal and the fourth node; The tenth transistor is coupled between the fourth node and the ground terminal; The eleventh transistor and the twelfth transistor are coupled in series between the third node and the second output terminal; The thirteenth transistor and the fourteenth transistor are coupled in series between the second output terminal and the fourth node; The fifteenth transistor, the sixteenth transistor, and the seventeenth transistor are coupled in parallel between the power supply terminal and a fifth node; The eighteenth transistor is coupled between the fifth node and the second output terminal; The nineteenth transistor is coupled between the second output terminal and the sixth node; The twentieth transistor, the twenty-first transistor, and the twenty-second transistor are coupled in parallel between the sixth node and the ground terminal; The control terminals of the third transistor, the fourth transistor, the twelfth transistor, the thirteenth transistor, the fifteenth transistor and the twentieth transistor are configured to receive a first input; The control terminals of the first transistor, the fifth transistor, the seventh transistor, the tenth transistor, the sixteenth transistor and the twenty-first transistor are configured to receive a second input; control terminals of the second transistor, the sixth transistor, the eighth transistor, the ninth transistor, the eleventh transistor, the fourteenth transistor, the seventeenth transistor, and the twenty-second transistor are configured to receive a third input; Control terminals of the eighteenth transistor and the nineteenth transistor are coupled to the first output terminal.

17. The operator circuit according to claim 16, characterized in that the first transistor, the second transistor, the third transistor, the seventh transistor, the eighth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor are PMOS transistors; The fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the thirteenth transistor, the fourteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, and the twenty-second transistor are NMOS transistors.

18. A W-layer inverse compressor in a processor, characterized in that: W is an integer greater than 1, and the W-layer inverse compressor includes: a first-layer inverse compressor to a W-th-layer inverse compressor; The first-layer inverse compressor is configured to compress each digit in the array of the P partial product terms in order from low digit to high digit using an inverse compression operator until the number of remaining bits corresponding to each digit is less than three, thereby obtaining a first compressed array; The i-th layer of inverse compressor is used to compress each digit in the i-1-th compression array using the inverse compression operator in order from low digit to high digit until the remaining bits corresponding to each digit are less than three, thereby obtaining the i-th compression array, where the value of i ranges from 2 to W; The Wth compressed array includes two rows, each row corresponding to an accumulated value; In which, the compression of each digit by the inverting compressor at each layer is performed on the three bits of the digit; each row in the array of the P partial product terms includes a partial product term, and each column includes multiple bits corresponding to the same digit in the P partial product terms.

19. The W-layer inverse compressor according to claim 18, characterized in that For each of the three bits of the digit, each inverse compressor is specifically configured to perform the following compression: If all three bits are 0, the carry output bit is 1 and the current sum output bit is 1; If all three bits are 1, the carry output bit is 0 and the current sum output bit is 0; If one of the three bits is 1 and the other two bits are 0, the carry output bit is 1 and the current sum output bit is 0; If two of the three bits are 1 and the other bit is 0, the carry output bit is 0 and the current sum output bit is 1.

20. The W-layer inverse compressor according to claim 18 or 19, characterized in that: The W-layer inverse compressor further includes: One or more inverters, used to invert the phase of the current sum output bit and carry output bit output by one or more inverting compressors in the W layer, or to invert the phase of at least one of the three bits input to the one or more inverting compressors.

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