A Trigger Chain Length Limiting Structure and Method Based on the RISC-V Debug Protocol

Abstract

The present invention discloses a Trigger chain length limit structure and method based on the RISC-V debugging protocol. Define the number of Triggers in the Trigger sequence as n, where n≥1. Number the Triggers in sequence as 1, 2, …, n. The upper limit of the Trigger chain length is m, where 1≤m≤n. Define the D flip-flop Trigger_i_chain as the chain configuration signal register of the Trigger numbered i, and the output is the chain configuration signal chain_i, indicating whether the Trigger is linked to the subsequent Trigger. A high level indicates that the link between this Trigger and the subsequent Trigger is valid, and a low level indicates that the link between the Trigger and the subsequent Trigger is invalid. The implementation method of the present invention is clear, the logic is simple, and the signal delay is low.

Description

Technical Field

[0001] The present invention belongs to the technical field of hardware circuit design, and particularly relates to a Trigger chain length limit structure and method based on the RISC-V debugging protocol. Background Art

[0002] Based on the requirements of the RISC-V debugging protocol, the Trigger function not only supports the matching trigger of a single Trigger, but also supports the matching trigger of a Trigger chain composed of multiple Triggers. Considering performance, the Trigger function should meet the single-cycle response requirement, that is, be able to send a feedback signal before the next instruction after the Trigger is triggered is executed.

[0003] To meet this requirement, it is necessary to ensure that the Trigger function has a low response latency. However, after configuring the Trigger chain, multiple Triggers in the Trigger chain will work serially, increasing the response latency. Therefore, it is necessary to limit the length of the Trigger chain. If the debugging software or the user records and judges whether the length of the Trigger chain exceeds the upper limit by themselves, it will increase the complexity of the debugging software and cannot ensure that the Trigger chain is configured correctly.

[0004] Based on the above considerations for the Trigger chain length limit structure, no relevant patents and literatures have been retrieved currently. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a Trigger chain length limit structure and method based on the RISC-V debugging protocol for the deficiencies in the above-mentioned prior art, which can hardware detect whether adding the current Trigger to the Trigger chain makes the Trigger chain exceed the length upper limit, control the enable signal for adding the current Trigger to the Trigger chain, achieve the purpose of limiting the length of the Trigger chain, support the configuration of the Trigger chain in any order, and ensure the fast response of the Trigger function.

[0006] The present invention adopts the following technical solutions:

[0007] A Trigger chain length limit structure based on the RISC-V debug protocol, including a Trigger sequence and a chain configuration signal register; the number of Triggers in the Trigger sequence is n, n≥1, and the Triggers in the sequence are numbered 1, 2, …, n in order, and the upper limit of the chain length of the Trigger sequence is m, 1≤m≤n; the chain configuration signal register of Trigger is the D flip-flop Trigger_i_chain, 1≤i≤n; the chain configuration signal chain_i generates m judgment signals through m AND gates, and the m judgment signals generate the Trigger chain configuration enable signal chain_i_enable through a NOR gate, and the Trigger chain configuration enable signal chain_i_enable and the Trigger_i_set signal are AND-operated and then output to the D terminal of the D flip-flop Trigger_i_chain; the Q terminal of the D flip-flop Trigger_i_chain generates the chain configuration signal chain_i of the Trigger.

[0008] A working method of a Trigger chain length limit structure based on the RISC-V debug protocol includes the following steps:

[0009] The Trigger numbered i receives the chain configuration signals of m-1 predecessor Triggers numbered i-m+1 to i-1 and m-1 successor Triggers numbered i+1 to i+m-1.

[0010] Set the chain configuration signals with numbers exceeding the Trigger number range to a constant low level, and form a new sequence with the 2m-2 chain configuration signals in the order of Trigger numbers; perform an AND operation on every m-1 adjacent consecutive signals in the new sequence to generate m judgment signals, and perform a NOR operation on the m judgment signals to generate the Trigger chain configuration enable signal chain_i_enable;

[0011] Perform an AND operation on the generated Trigger chain configuration enable signal chain_i_enable and the Trigger_i_set signal and connect the output to the D terminal of the D flip-flop Trigger_i_chain; the Q terminal of the D flip-flop Trigger_i_chain generates the chain configuration signal chain_i of the Trigger numbered i.

[0012] Specifically, when the chain configuration signal chain_i is at a high level, the corresponding Trigger is effectively linked to the successor Trigger, and when the chain configuration signal chain_i is at a low level, the corresponding Trigger is not effectively linked to the successor Trigger.

[0013] Furthermore, when the length of the Trigger chain generated corresponding to the valid Trigger chain configuration signal chain_i does not exceed the upper limit m, the chain configuration enable signal chain_i_enable is automatically set to the valid high level.

[0014] Furthermore, when the length of the Trigger chain generated corresponding to the valid Trigger chain configuration signal chain_i exceeds the upper limit m, the chain configuration enable signal chain_i_enable is automatically set to the invalid low level.

[0015] Specifically, generating m judgment signals is specifically as follows: First, perform a NAND operation on every m - 1 adjacent consecutive signals in the new sequence to generate m judgment signals, and then perform an AND operation on the m judgment signals to generate the Trigger chain configuration enable chain_i_enable signal.

[0016] Specifically, when the Trigger_i_set signal is high, the Trigger chain configuration signal chain_i is configured.

[0017] Specifically, when the Trigger_i_set signal is low, the Trigger chain configuration signal chain_i is cleared to the low level.

[0018] Specifically, when the Trigger chain configuration enable signal Trigger_i_enable is high, chain_i is consistent with chain_i_set.

[0019] Specifically, when the Trigger chain configuration enable signal is low, chain_i is constantly at the low level.

[0020] Compared with the prior art, the present invention has at least the following beneficial effects:

[0021] A Trigger chain length limitation structure based on the RISC-V debug protocol of the present invention. The limitation structure of the present invention can limit the length of the trigger chain, thereby limiting the serial signal delay, and ensuring that the response speed meets the single-cycle response of the processor debug hardware. Automatically judge whether the current trigger makes the trigger chain length exceed the trigger chain length upper limit after adding the trigger to the trigger chain and automatically control the trigger chain configuration of the current trigger, thereby limiting the trigger chain length, limiting the signal delay of the entire trigger chain, ensuring the response speed, and eliminating the need for the user to record the configured trigger chain length by themselves, making the use of the trigger chain simpler.

[0022] A working method of a Trigger chain length limitation structure based on the RISC-V debugging protocol enables the trigger numbered i to automatically determine whether a Trigger chain with a length exceeding the upper limit will be generated after the trigger numbered i is configured into the Trigger chain according to the Trigger chain configuration of other triggers when the trigger chain configuration command is received. If the Trigger chain will exceed the length upper limit, the trigger chain configuration command is ignored. If the Trigger chain will not exceed the upper limit, whether the trigger numbered i is configured into the Trigger chain is determined by the trigger chain configuration command; in this way, the length of the Trigger chain can be limited, thereby ensuring that the signal delay of the entire Trigger chain is low enough.

[0023] Further, a low Chain_i signal indicates that the trigger numbered i is not configured into the Trigger chain, and a high chain_i signal indicates that the trigger numbered i has been configured into the Trigger chain. After the trigger user issues a trigger chain configuration command to the trigger numbered i through trigger_i_set, it can be known whether the configuration is successful by reading the chain_i signal.

[0024] Further, setting chain_i_enable to an active high level indicates that the trigger numbered i can be configured into the Trigger chain. The Chain_i_enable and trigger_i_set signals are output to the D terminal of the register trigger_i_chain through an AND gate. Setting chain_i_enable to a high level signal can ensure that the input of the D terminal of the register trigger_i_chain is equal to chain_i_set.

[0025] Further, setting chain_i_enable to an inactive low level indicates that the trigger numbered i cannot be configured into the Trigger chain; the Chain_i_enable and trigger_i_set signals are output to the D terminal of the register trigger_i_chain through an AND gate. Setting chain_i_enable to a low level signal can ensure that the input of the D terminal of the register trigger_i_chain is low.

[0026] Furthermore, since triggers outside the trigger number range do not exist, they will not be configured into the trigger chain either, and the corresponding chain configuration signal is constantly at a low level. A trigger chain enable signal chain_i_enable is generated to control the D-terminal input of register trigger_i_chain through a simple AND operation with the trigger configuration signal chain_i_set.

[0027] Furthermore, a high Trigger_i_set signal indicates that the trigger chain command is to add the trigger with number i to the trigger chain, and the signal chain_i indicates whether the trigger with number i is finally configured into the trigger chain.

[0028] Furthermore, a low Trigger_i_set signal indicates that the trigger chain command is not to add the trigger with number i to the trigger chain, and the signal chain_i indicates that the trigger with number i is not in the trigger chain.

[0029] Furthermore, according to the definition of logical AND, for a two-input AND gate, when one of the inputs is high, the AND gate output is the same as the other input. A high Trigger_i_enable indicates that the trigger with number i can be configured into the trigger chain, and at this time, chain_i is determined by the trigger chain configuration command chain_i_set.

[0030] Furthermore, a low trigger chain configuration enable signal indicates that the trigger with number i cannot be configured into the trigger chain at this time, ignoring the trigger chain configuration command chain_i_set, chain_i is constantly low, and the trigger with number i is not in the trigger chain.

[0031] In summary, the structure of the present invention is easy to expand and can adapt to trigger sequences and trigger chain length limits including any number of triggers; the circuit implementation method is clear, the logic is simple, and the signal delay is low.

[0032] Next, through the accompanying drawings and embodiments, the technical solution of the present invention will be further described in detail. Description of the Drawings

[0033] Figure 1 It is a schematic diagram of the trigger chain length limit structure of the present invention;

[0034] Figure 2Another equivalent structure of the Trigger chain length limit structure with a maximum length of 4;

[0035] Figure 3 Is the Trigger chain length limit structure with a maximum length of 5. Detailed implementation manners

[0036] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0037] It should be understood that the terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms.

[0038] It should also be further understood that the term "and / or" used in the specification of the present invention and the appended claims refers to any combination and all possible combinations of one or more of the related listed items, and includes these combinations.

[0039] Various structural schematic diagrams according to the disclosed embodiments of the present invention are shown in the drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures and their relative sizes and positional relationships are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes and relative positions according to actual needs.

[0040] The present invention provides a Trigger chain length limit structure based on the RISC-V debugging protocol. Define the number of Triggers in the Trigger sequence as n, where n ≥ 1. The Triggers are sequentially numbered as 1, 2, …, n. The upper limit of the Trigger chain length is m, where 1 ≤ m ≤ n. Define the D flip-flop Trigger_i_chain (1 ≤ i ≤ n) as the chain configuration signal register of the Trigger numbered i. Its output is the chain configuration signal chain_i (1 ≤ i ≤ n). This signal indicates whether this Trigger is linked to the subsequent Trigger. A high level indicates that the link between this Trigger and the subsequent Trigger is valid, and a low level indicates that the link between this Trigger and the subsequent Trigger is invalid; the chain configuration signal register of the Trigger is the D flip-flop Trigger_i_chain, 1 ≤ i ≤ n; the chain configuration signal chain_i generates m judgment signals through m AND gates. The m judgment signals generate the Trigger chain configuration enable signal chain_i_enable through a NOR gate. The Trigger chain configuration enable signal chain_i_enable and the Trigger_i_set signal are AND-operated and then output to the D terminal of the D flip-flop Trigger_i_chain; the Q terminal of the D flip-flop Trigger_i_chain generates the chain configuration signal chain_i of the Trigger.

[0041] The present invention provides a working method for a Trigger chain length limit structure based on the RISC-V debugging protocol, including the following steps:

[0042] For the Trigger numbered i, receive the chain configuration signals of the m - 1 predecessor Triggers numbered from i - m + 1 to i - 1 and the m - 1 subsequent Triggers numbered from i + 1 to i + m - 1.

[0043] For the chain configuration signals whose Trigger numbers exceed the Trigger number range, set them to a constant low level. The 2m - 2 chain configuration signals form a new sequence according to their Trigger number order; perform an AND operation on every m - 1 adjacent consecutive signals in the new sequence to generate m judgment signals, and perform a NOR operation on the m judgment signals to generate the Trigger chain configuration enable signal chain_i_enable.

[0044] That is, if the Trigger chain configuration signal chain_i is valid, a Trigger chain with a length exceeding the upper limit m is generated. At this time, the hardware automatically sets the chain configuration enable signal chain_i_enable to an invalid low level;

[0045] When the Trigger chain configuration signal chain_i is valid, a Trigger chain with a length exceeding the upper limit m is not generated. At this time, the hardware automatically sets the chain configuration enable signal chain_i_enable to the active high level.

[0046] Again, for the generation of the m judgment signals and the Trigger chain configuration enable signal chain_i_enable in the second structure, it is equivalent to first performing a NAND operation on every m - 1 adjacent consecutive signals in the new sequence to generate m judgment signals, and then performing an AND operation on the m judgment signals to generate the Trigger chain configuration enable chain_i_enable signal.

[0047] Finally, define the Trigger_i_set signal as the chain configuration command for the Trigger numbered i. When this signal is high, it indicates that the Trigger chain configuration signal chain_i is configured. When this signal is low, it indicates that the Trigger chain configuration signal chain_i is cleared to the low level.

[0048] Perform an AND operation on the generated Trigger chain configuration enable signal chain_i_enable and the Trigger_i_set signal, and connect the output to the D terminal of the D flip - flop Trigger_i_chain; the Q terminal of the D flip - flop Trigger_i_chain generates the chain configuration signal chain_i for the Trigger numbered i.

[0049] That is, when the Trigger chain configuration enable signal Trigger_i_enable is high, chain_i is consistent with chain_i_set. When the Trigger chain configuration enable signal is low, chain_i is always at the low level.

[0050] The structure of the present invention enables a trigger to determine whether it can be configured into a trigger chain according to the trigger chain configuration of other triggers when receiving a trigger chain configuration command, limits the length of the trigger chain, and thus ensures that the signal delay of the entire trigger chain is low enough.

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components described and shown in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0052] Please refer to Figure 1 , taking the maximum length of 4 as an example, with 16 Triggers in the Trigger sequence numbered from 0 to 16 and the Trigger chain length limit of 4 as an example, Figure 1 The structure inside is the length limit structure within the Trigger numbered 5. The signal chain_2 is the Trigger chain configuration signal of the Trigger numbered 2, the signal chain_3 is the Trigger chain configuration signal of the Trigger numbered 3, the signal chain_4 is the Trigger chain configuration signal of the Trigger numbered 4, the signal chain_6 is the Trigger chain configuration signal of the Trigger numbered 6, the signal chain_7 is the Trigger chain configuration signal of the Trigger numbered 7, and the signal chain_8 is the Trigger chain configuration signal of the Trigger numbered 8. The Trigger chain configuration signal being high indicates that this Trigger is linked to its subsequent Trigger to form a Trigger chain. The Trigger chain configuration signal being low indicates that this Trigger is not linked to its subsequent Trigger and is not on the same Trigger chain.

[0053] AND1 is a three-input AND gate that receives the signals from chain_2, chain_3, and chain_4 as inputs. If the output of AND1 is high, it means that chain_2, chain_3, and chain_4 are all high, and the Trigger numbered 2 to the Trigger numbered 5 are linked into a Trigger chain with a length of 4. If chain_5 is set to high, then the Trigger numbered 2 to the Trigger numbered 6 will be linked into a Trigger chain with a length of 5, exceeding the length limit.

[0054] AND2 is a three-input AND gate that receives signals from chain_3, chain_4, and chain_6 as inputs. If the output of AND2 is high, it means that chain_3, chain_4, and chain_6 are all high. The link from Trigger numbered 3 to Trigger numbered 5 forms a Trigger chain with a length of 3, and the link from Trigger numbered 6 to Trigger numbered 7 forms a Trigger chain with a length of 2. If chain_5 is set to high, then the link from Trigger numbered 3 to Trigger numbered 7 will form a Trigger chain with a length of 5, exceeding the length limit.

[0055] AND3 is a three-input AND gate that receives signals from chain_4, chain_6, and chain_7 as inputs. If the output of AND3 is high, it means that chain_4, chain_6, and chain_7 are all high. The link from Trigger numbered 4 to Trigger numbered 5 forms a Trigger chain with a length of 2, and the link from Trigger numbered 6 to Trigger numbered 8 forms a Trigger chain with a length of 3. If chain_5 is set to high, then the link from Trigger numbered 4 to Trigger numbered 8 will form a Trigger chain with a length of 5, exceeding the length limit.

[0056] AND4 is a three-input AND gate that receives signals from chain_6, chain_7, and chain_8 as inputs. If the output of AND4 is high, it means that chain_6, chain_7, and chain_8 are all high. The link from Trigger numbered 6 to Trigger numbered 9 forms a Trigger chain with a length of 4. If chain_5 is set to high, then the link from Trigger numbered 5 to Trigger numbered 9 will form a Trigger chain with a length of 5, exceeding the length limit.

[0057] NOR is a four-input NOR gate that receives the output signals from AND1, AND2, AND3, and AND4 as inputs, and its output signal is chain_5_enable, which serves as the chain configuration enable signal. When the output of one of the AND1 to AND4 gates is high, NOR outputs a low-level signal, and the chain configuration enable bit is invalid. When there are no three consecutive high-level signals in the signal sequence composed of chain_2 to chain_4 and chain_6 to chain_8, AND1 to AND4 all output low-level signals, and NOR outputs a high-level signal, and the chain configuration enable bit is valid.

[0058] The chain_5_set signal is a trigger chain configuration command sent by the Trigger function user to Trigger numbered 5. A high level indicates setting the trigger chain configuration signal of this Trigger, and a low level indicates clearing the trigger chain configuration signal of this Trigger. The clk signal is the trigger signal of the D flip-flop Trigger_5_chain. The D flip-flop Trigger_5_chain is used to record the trigger chain configuration information of this Trigger. The chain_5_set signal and the chain_5_enable signal are connected to the input terminals of a two-input AND gate, and the output terminal of this AND gate is connected to the D terminal of Trigger_5_chain. When the chain_5_enable signal is high, the D terminal of Trigger_5_chain is consistent with chain_5_set and can be set or cleared by the trigger chain configuration command. When the chain_5_enable signal is low, the D terminal of Trigger_5_chain is constantly at a low level, and the trigger chain configuration signal is constantly at a low level. chain_5 is the trigger chain configuration signal of Trigger numbered 5. When this signal is high, Trigger numbered 5 and Trigger numbered 6 are linked into a trigger chain. The chain_5 signal is simultaneously output to the trigger chain length limit structures in Triggers numbered 2, 3, 4, 6, 7, and 8.

[0059] Please refer to Figure 2 , for another equivalent structure of the trigger chain length limit structure of Trigger numbered 5 with a trigger chain length limit of 4 in a trigger sequence containing 16 Triggers numbered 0 to 16. This structure can achieve the same function as the structure in Figure 1 .

[0060] Please refer to Figure 3 , for a trigger chain length limit structure with a maximum length of 5. Taking a trigger sequence containing 16 Triggers numbered 0 to 16 with a trigger chain length limit of 5 as an example, Figure 3In the middle is the length limit structure inside the Trigger numbered 5. The signal chain_1 is the Trigger chain configuration signal of the Trigger numbered 1, the signal chain_2 is the Trigger chain configuration signal of the Trigger numbered 2, the signal chain_3 is the Trigger chain configuration signal of the Trigger numbered 3, the signal chain_4 is the Trigger chain configuration signal of the Trigger numbered 4, the signal chain_6 is the Trigger chain configuration signal of the Trigger numbered 6, the signal chain_7 is the Trigger chain configuration signal of the Trigger numbered 7, the signal chain_8 is the Trigger chain configuration signal of the Trigger numbered 8, and the signal chain_9 is the Trigger chain configuration signal of the Trigger numbered 9.

[0061] AND1 is a four-input AND gate that receives the signals from chain_1, chain_2, chain_3, and chain_4 as inputs. If the output of AND1 is high, it means that chain_1, chain_2, chain_3, and chain_4 are all high. The Trigger numbered 1 to the Trigger numbered 5 are linked into a Trigger chain with a length of 5. If chain_5 is set to high, it will cause the Trigger numbered 1 to the Trigger numbered 6 to be linked into a Trigger chain with a length of 6, exceeding the length limit.

[0062] AND2 is a four-input AND gate that receives the signals from chain_2, chain_3, chain_4, and chain_6 as inputs. If the output of AND2 is high, it means that chain_2, chain_3, chain_4, and chain_6 are all high. The Trigger numbered 2 to the Trigger numbered 5 are linked into a Trigger chain with a length of 4, and the Trigger numbered 6 to the Trigger numbered 7 are linked into a Trigger chain with a length of 2. If chain_5 is set to high, it will cause the Trigger numbered 2 to the Trigger numbered 7 to be linked into a Trigger chain with a length of 6, exceeding the length limit.

[0063] AND3 is a four-input AND gate that receives signals from chain_3, chain_4, chain_6, and chain_7 as inputs. If the output of AND3 is high, it means that chain_3, chain_4, chain_6, and chain_7 are all high. The link from Trigger numbered 3 to Trigger numbered 5 forms a Trigger chain with a length of 3, and the link from Trigger numbered 6 to Trigger numbered 8 forms a Trigger chain with a length of 3. If chain_5 is set to high, the link from Trigger numbered 3 to Trigger numbered 8 will form a Trigger chain with a length of 6, exceeding the length limit.

[0064] AND4 is a four-input AND gate that receives signals from chain_4, chain_6, chain_7, and chain_8 as inputs. If the output of AND4 is high, it means that chain_4, chain_6, chain_7, and chain_8 are all high. The link from Trigger numbered 4 to Trigger numbered 5 forms a Trigger chain with a length of 2, and the link from Trigger numbered 6 to Trigger numbered 9 forms a Trigger chain with a length of 4. If chain_5 is set to high, the link from Trigger numbered 4 to Trigger numbered 9 will form a Trigger chain with a length of 6, exceeding the length limit.

[0065] AND5 is a four-input AND gate that receives signals from chain_6, chain_7, chain_8, and chain_9 as inputs. If the output of AND4 is high, it means that chain_6, chain_7, chain_8, and chain_9 are all high. The link from Trigger numbered 6 to Trigger numbered 10 forms a Trigger chain with a length of 5. If chain_5 is set to high, the link from Trigger numbered 5 to Trigger numbered 10 will form a Trigger chain with a length of 6, exceeding the length limit.

[0066] The NOR is a five-input NOR gate that receives the output signals from AND1, AND2, AND3, AND4, and AND5 as inputs, and its output signal is chain_5_enable, which serves as the chain configuration enable signal. When the output of one of the AND gates from AND1 to AND5 is high, the NOR outputs a low-level signal, and the chain configuration enable bit is invalid. When there are no four consecutive high-level signals in the signal sequences formed by chain_1 to chain_4 and chain_6 to chain_9, AND1 to AND5 all output low-level signals, the NOR outputs a high-level signal, and the chain configuration enable bit is valid.

[0067] The chain_5_set signal is the Trigger chain configuration command sent by the Trigger function user to the Trigger numbered 5. A high level indicates that the Trigger chain configuration signal of this Trigger is set, and a low level indicates that the Trigger chain configuration signal of this Trigger is cleared. The clk signal is the trigger signal of the D flip-flop Trigger_5_chain. The D flip-flop Trigger_5_chain is used to record the Trigger chain configuration information of this Trigger. The chain_5_set signal and the chain_5_enable signal are connected to the input terminals of a two-input AND gate, and the output terminal of this AND gate is connected to the D terminal of Trigger_5_chain. When the chain_5_enable signal is high, the D terminal of Trigger_5_chain is the same as chain_5_set and can be set or cleared by the Trigger chain configuration command. When the chain_5_enable signal is low, the D terminal of Trigger_5_chain is always low level, and the Trigger chain configuration signal is always low. chain_5 is the Trigger chain configuration signal of the Trigger numbered 5. When this signal is high, the Triggers numbered 5 and 6 are linked as a Trigger chain. The chain_5 signal is also output to the Trigger chain length limit structures in the Triggers numbered 1, 2, 3, 4, 6, 7, 8, and 9.

[0068] The present invention has been applied to a RISC-V processor core and completed FPGA verification. The implementation method of this architecture is clear, the control logic is simple, and it has strong generality and scalability. It can be used as a general module in the design of RISC-V processor cores.

[0069] In summary, a Trigger chain length limit structure based on the RISC-V debug protocol in the present invention can detect in hardware whether configuring the current Trigger into the Trigger chain will cause the length of the Trigger chain to exceed the upper limit; the structure is easy to expand and can adapt to Trigger sequences with any number of Triggers and the upper limit of the Trigger chain length; the circuit implementation method is clear, the logic is simple, and the signal delay is low.

[0070] The above content is only to illustrate the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution according to the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A working method of a Trigger chain length limit structure based on the RISC-V debug protocol, characterized in that, it includes a Trigger sequence and a chain configuration signal register; the number of Triggers in the Trigger sequence is n, n≥1, the Triggers in the sequence are numbered 1, 2, …, n in order, and the upper limit of the chain length of the Trigger sequence is m, 1≤m≤n; the chain configuration signal register of the Trigger is a D flip-flop Trigger_i_chain, 1≤i≤n; the chain configuration signal chain_i of the Trigger generates m judgment signals through m AND gates, and the m judgment signals generate a Trigger chain configuration enable signal chain_i_enable through a NOR gate, and the Trigger chain configuration enable signal chain_i_enable and the Trigger_i_set signal are AND-operated and then output to the D terminal of the D flip-flop Trigger_i_chain; the Trigger numbered i receives the chain configuration signals of m-1 predecessor Triggers numbered i-m+1 to i-1 and m-1 successor Triggers numbered i+1 to i+m-1, and sets the chain configuration signals with numbers outside the Trigger number range to a constant low level; The 2m-2 chain configuration signals are arranged in a new sequence according to the Trigger number order; each m-1 adjacent consecutive signals in the new sequence are AND-operated to generate m judgment signals, and the m judgment signals are NOR-operated to generate a Trigger chain configuration enable signal chain_i_enable; The generated Trigger chain configuration enable signal chain_i_enable and the Trigger_i_set signal are AND-operated and the output is connected to the D terminal of the D flip-flop Trigger_i_chain; the Q terminal of the D flip-flop Trigger_i_chain generates the chain configuration signal chain_i of the Trigger numbered i. When the chain configuration signal chain_i is at a high level, the corresponding Trigger is effectively linked to the successor Trigger. When the chain configuration signal chain_i is at a low level, the corresponding Trigger is not effectively linked to the successor Trigger.

2. The method according to claim 1, characterized in that, when the Trigger chain length generated corresponding to the effective Trigger chain configuration signal chain_i does not exceed the upper limit m, the chain configuration enable signal chain_i_enable is automatically set to an effective high level.

3. The method according to claim 1, characterized in that, when the Trigger chain length generated corresponding to the effective Trigger chain configuration signal chain_i exceeds the upper limit m, the chain configuration enable signal chain_i_enable is automatically set to an ineffective low level.

4. The method according to claim 1, characterized in that, Generating m judgment signals specifically includes: First, perform a NAND operation on every m - 1 adjacent consecutive signals in the new sequence to generate m judgment signals, and then perform an AND operation on the m judgment signals to generate the Trigger chain configuration enable chain_i_enable signal.

5. The method according to claim 1, characterized in that, when the Trigger_i_set signal is high, configure the Trigger chain configuration signal chain_i.

6. The method according to claim 1, characterized in that, when the Trigger_i_set signal is low, clear the Trigger chain configuration signal chain_i to a low level.

7. The method according to claim 1, characterized in that, when the Trigger chain configuration enable signal Trigger_i_enable is high, chain_i is consistent with chain_i_set.

8. The method according to claim 1, characterized in that, when the Trigger chain configuration enable signal is low, chain_i is constantly at a low level.

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