Memory device and operating method thereof

Abstract

A memory device and an operating method thereof are provided. The memory device includes: a latch configured to sense a voltage or current of a bit line coupled to a memory cell and store read data; a transmission circuit configured to output the read data stored in the latch via a page bus in response to a transmission signal; a cache latch configured to receive the read data via the page bus and temporarily store the read data; and a pump voltage output circuit coupled to the transmission circuit via a transmission line and configured to apply a second voltage greater than the first voltage after applying a first voltage to the transmission line for a set time.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to a memory device and a method of operating the same, and more particularly, to a memory device including a page buffer and a method of operating the same. Background Art

[0002] A memory device may include a memory block in which data is stored; a peripheral circuit which is a group of circuits / components for performing a program operation, a read operation, or an erase operation on the memory block; and a logic circuit which controls the peripheral circuit.

[0003] The peripheral circuit may generate a program voltage, a read voltage, and an erase voltage to be applied to a word line connected to a memory block. The peripheral circuit may store data input from an external device in the memory block, read the stored data from the memory block, output the read data to the external device, and erase the stored data from the memory block.

[0004] The logic circuit may include software and hardware that controls the peripheral circuit in response to commands input from an external device. For example, the software included in the logic circuit may control the hardware in response to commands, and the hardware may control the peripheral circuit by outputting various voltages and signals in response to the control of the software. Summary of the Invention

[0005] Various embodiments of the present disclosure relate to a memory device capable of suppressing a voltage drop of a signal controlling a page buffer included in the memory device and a method of operating the memory device.

[0006] According to an embodiment, a memory device may include: a latch configured to sense a voltage or a current of a bit line coupled to a memory cell and store read data; a transfer circuit configured to output the read data stored in the latch through a page bus in response to a transfer signal; a cache latch configured to receive the read data through the page bus and temporarily store the read data; and a pump voltage output circuit coupled to the transfer circuit through a transfer line and configured to apply a second voltage greater than the first voltage after applying the first voltage to the transmission line for a set time.

[0007] According to an embodiment, a memory device may include: a switch that transmits data on a first line to a second line in response to a transmission signal; and a pump voltage output circuit that is connected to a gate of the switch and outputs a transmission signal to the gate, wherein the pump voltage output circuit is configured to: increase the potential of the gate to a first voltage before the data is transmitted to the second line; and when the data is transmitted to the second line, output a transmission signal having a second voltage greater than the first voltage to the gate.

[0008] According to an embodiment, a method of operating a memory device may include: storing read data in a latch of a page buffer by reading a memory cell; precharging a gate of a transfer switch coupled between the latch and a cache latch by applying a first voltage to the gate; and turning on the transfer switch by applying a second voltage greater than the first voltage to the gate when the gate is precharged.

[0009] According to an embodiment, a memory device may include: page buffers configured to provide data in response to a common signal of a target voltage level; cache latches configured to latch the data provided from the respective page buffers; and a control circuit configured to provide a common signal through a common line by increasing the common signal to precharge the common line to an intermediate voltage level and then increasing the common signal to the target voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0011] Figure 2 is a diagram illustrating an example memory cell array;

[0012] Figure 3 is a diagram illustrating a memory block;

[0013] Figure 4 is a diagram illustrating a page buffer group and a cache latch group;

[0014] Figure 5 is a diagram illustrating page buffers included in a page buffer group;

[0015] Figure 6 is a diagram illustrating the voltage drop occurring on a transmission line;

[0016] Figure 7 is a diagram illustrating the voltage of a transmission signal when a voltage drop occurs on a transmission line;

[0017] Figure 8 is a diagram illustrating a pump voltage output circuit according to an embodiment of the present disclosure;

[0018] Figure 9 is a diagram illustrating a method of operating a pump voltage output circuit.

[0019] Figure 10 is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure; and

[0020] Figure 11 is a diagram illustrating a memory system including a memory device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Throughout the specification, references to "one embodiment," "another embodiment," etc. do not necessarily refer to only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. When used herein, the term "embodiment" does not necessarily refer to all embodiments.

[0022] Figure 1 is a diagram illustrating a memory device 1100 according to an embodiment of the present disclosure.

[0023] Reference Figure 1 , the memory device 1100 may include a memory cell array 110 , a row decoder 120 , a voltage generator 130 , a page buffer group 140 , a cache latch group 150 , a column decoder 160 , an input / output circuit 170 , and a logic circuit 180 .

[0024] The memory cell array 110 may include a plurality of memory blocks for storing data. Each memory block may include a plurality of memory cells. Each memory cell may have a two-dimensional structure in which the memory cells are arranged parallel to the substrate or a three-dimensional structure in which the memory cells are stacked in a vertical direction relative to the substrate.

[0025] The row decoder 120 may select one memory block among the memory blocks in the memory cell array 110 in response to the row address RADD and transfer the input operation voltage Vop to the selected memory block.

[0026] The voltage generator 130 may generate and output an operation voltage Vop for performing various operations in response to the operation code OPCD. For example, the voltage generator 130 may generate and output an operation voltage Vop including a program voltage, a verification voltage, a read voltage, an erase voltage, and a pass voltage.

[0027] The page buffer group 140 can be coupled to the memory cell array 110 via bit lines. For example, the page buffer group 140 can include page buffers that are respectively coupled to the bit lines. The page buffers can operate simultaneously in response to a page buffer control signal PBSIGS and temporarily store data during a programming operation or a read operation. The verification operation performed in the programming operation and the erase verification operation performed in the erase operation can be performed in the same manner as the read operation. During the verification operation, the page buffers can precharge the bit lines to sense the threshold voltage of the memory cells, and can sense data from the memory cells based on the voltage or current of the bit lines.

[0028] The cache latch group 150 can temporarily store data input from an external device through the data line DL# and transmit the data to the page buffer group 140 in response to the control of the column decoder 160. In addition, the cache latch group 150 can receive and temporarily store data read from the page buffer group 140 and output the data through the data line DL# in response to the control of the column decoder 160.

[0029] The column decoder 160 may control the cache latch group 150 in response to the column address CADD to transfer data. For example, when data is temporarily stored in the cache latch group 150, the column decoder 160 may control the cache latch group 150 in response to the column address CADD so that the data temporarily stored in the cache latch group 150 is transferred to the page buffer group 140. Alternatively, the column decoder 160 may control the cache latch group 150 in response to the column address CADD so that the data stored in the page buffer group 140 is transferred to the cache latch group 150.

[0030] The input / output circuit 170 can communicate with an external device via an input / output line 10. The external device may be a controller that controls the memory device 1100. The input / output circuit 170 can receive a command CMD, an address ADD, and data from the external device via the input / output line 10, or output data received from the cache latch group 150 to the external device. The input / output circuit 170 can transmit the command CMD and address ADD received via the input / output line 10 to the logic circuit 180, and can transmit data to the cache latch group 150.

[0031] The logic circuit 180 can output an operation code OPCD, a row address RADD, a page buffer control signal PBSIGS, and a column address CADD in response to a command CMD and an address ADD. The logic circuit 180 may include software that executes algorithms for various operations in response to the command CMD, and hardware configured to output various signals in response to the software's control. For example, the logic circuit 180 can output a row address RADD and a column address CADD by decoding the address ADD, and output an operation code OPCD and a page buffer control signal PBSIGS in response to the command CMD. The logic circuit 180 may include a signal output circuit (SIG_OUT) 190 that outputs the page buffer control signal PBSIGS. The signal output circuit 190 can output the page buffer control signal PBSIGS at various voltage levels, and includes a pump voltage output circuit (VPMP_OUT) 200 for outputting a signal having a second voltage level among the page buffer control signals PBSIGS.

[0032] Figure 2 is a diagram illustrating the memory cell array 110 .

[0033] Reference Figure 2 , the memory cell array 110 may be formed to have a single-plane structure or a multi-plane structure. The single-plane structure may refer to a structure in which the memory cell array 110 has a single plane, and the multi-plane structure may refer to a structure in which the memory cell array 110 has multiple planes. Figure 2 A memory cell array 110 having a multi-plane structure is illustrated.

[0034] The memory cell array 110 may include a first plane P1, a second plane P2, a third plane P3, and a fourth plane P4. The first plane P1, the second plane P2, the third plane P3, and the fourth plane P4 may be connected to different row decoders and different page buffers, respectively. Each of the first plane P1, the second plane P2, the third plane P3, and the fourth plane P4 may include a plurality of memory blocks BLK1 to BLKi, where i is a positive integer of 2 or greater. Different physical addresses may be assigned to the first plane P1, the second plane P2, the third plane P3, and the fourth plane P4, respectively. Furthermore, different physical addresses may be assigned to the plurality of memory blocks BLK1 to BLKi, respectively.

[0035] The first plane P1, the second plane P2, the third plane P3, and the fourth plane P4 can be simultaneously selected during a program operation, a read operation, or an erase operation, and the selected memory blocks of the first plane P1, the second plane P2, the third plane P3, and the fourth plane P4 can be the same or different depending on the row address. For example, the first memory block BLK1 of the first plane P1, the third memory block BLK3 of the second plane P2, the second memory block BLK2 of the third plane P3, and the first memory block BLK1 of the fourth plane P4 can be selected according to the row address.

[0036] For example, during a program operation, when data is input to page buffers connected to the first plane P1, the second plane P2, the third plane P3, and the fourth plane P4, respectively, a program operation can be performed simultaneously on the selected memory blocks of the first plane P1, the second plane P2, the third plane P3, and the fourth plane P4. During a read operation, a read operation can be performed simultaneously on the selected memory blocks of the first plane P1, the second plane P2, the third plane P3, and the fourth plane P4. During an erase operation, an erase operation can be performed simultaneously on the selected memory blocks of the first plane P1, the second plane P2, the third plane P3, and the fourth plane P4.

[0037] Figure 3 is a diagram illustrating a representative storage block.

[0038] Reference Figure 3 , as an example of an embodiment Figure 2 One memory block BLKi among the plurality of memory blocks BLK1 to BLKi shown in FIG.

[0039] The memory block BLKi may include a plurality of strings ST coupled between first to m-th bit lines BL1 to BLm and a source line SL, where m is a positive integer of 2 or greater. Each string ST may include a source select transistor SST coupled in series between the source line SL and the first to m-th bit lines BL1 to BLm, first to n-th memory cells C1 to Cn, and a drain select transistor DST.

[0040] supply Figure 3 The memory block BLKi shown is used to illustrate the configuration of the memory block. Therefore, the number of source selection transistors SST, memory cells and drain selection transistors DST is not limited to Figure 3 Quantity shown.

[0041] The gates of the source selection transistors SST connected to different strings ST can be connected to the source selection line SSL, the gates of the first to nth memory cells C1 to Cn can be connected to the first to nth word lines WL1 to WLn, respectively, and the gates of the drain selection transistors DST can be connected to the drain selection line DSL.

[0042] A group of memory cells connected to the same word line and included in different strings ST may form a page PG. A program operation or a read operation may be performed in units of page PG. For example, a sub-program operation or a verify operation may be performed in units of page PG. During a program operation, after performing a program operation on a selected page, a verify operation on the selected page may be performed. During a read operation, when performing a read operation on a selected page, the read data may be stored in a page buffer.

[0043] Figure 4 is a diagram illustrating the page buffer group 140 and the cache latch group 150 .

[0044] Reference Figure 4 The page buffer group 140 may include first to m-th page buffers PB1 to PBm, where m is a positive integer of 2 or greater. The first to m-th page buffers PB1 to PBm may be coupled to the first to m-th bit lines BL1 to BLm, respectively. The first to m-th page buffers PB1 to PBm may sense a voltage or current of the first to m-th bit lines BL1 to BLm and may store the sensed data. The first to m-th page buffers PB1 to PBm may receive a page buffer control signal PBSIGS in common and operate simultaneously.

[0045] The cache latch group 150 may include first to m-th cache latches CL1 to CLm. Each of the first to m-th cache latches CL1 to CLm may be configured to store data. For example, the first to m-th cache latches CL1 to CLm may temporarily store data DATA input through the first to m-th data lines DL1 to DLm, and may transmit the data DATA to the first to m-th page buffers PB1 to PBm, respectively, through the first to m-th page buses PBUS1 to PBUSm in response to control of the column decoder 160.

[0046] Figure 5 is a diagram illustrating a page buffer included in the page buffer group 140. As an example, Figure 5 The first page buffer PB1 is illustrated in . Each of the other page buffers may be configured the same as or substantially the same as PB1 .

[0047] Reference Figure 5 , the first page buffer PB1 may include a precharge circuit PRE, a first transfer circuit TRAN1 , a sensing circuit SEN, a discharge circuit DIS, first to k-th latches LAT1 to LATk, and a second transfer circuit TRAN2 . Figure 5 is a diagram illustrating an embodiment of a representative first page buffer PB1. Therefore, each of PB1 and other page buffers may be configured differently. Figure 5 For example, each page buffer may include Figure 5 One or more additional circuits not shown.

[0048] The precharge circuit PRE may be configured to precharge the first bit line BL1. For example, the precharge circuit PRE may transmit a first voltage V1 to the first bit line BL1 in response to a precharge signal BL_PRE to precharge the first bit line BL1. The first voltage V1 may be an internal voltage provided to the memory device 1100. Figure 1 V1 is shown in FIG as the source voltage.

[0049] The first transfer circuit TRAN1 may couple the first bit line BL1 to the sensing node SO or block (ie, disconnect) the connection between the first bit line BL1 and the sensing node SO in response to a first transfer signal PBSENSE.

[0050] The sensing circuit SEN can sense the voltage or current of the first bit line BL1 in response to the sensing signal SESG and the latch data QS during a verification operation or a read operation. Therefore, when the sensing circuit SEN operates, the first bit line BL1 and the sense node SO can be coupled together through the first transfer circuit TRAN1. The latch data QS can be input from an external device during a programming operation.

[0051] The first through k-th latches LAT1 through LATk can temporarily store data during a program or read operation. During a program operation, one or more of the first through k-th latches LAT1 through LATk can temporarily store data input from an external device, and during a verify operation, one or more different latches from the first through k-th latches LAT1 through LATk can temporarily store read data read from a memory cell. For example, the first latch LAT1 can temporarily store data input from an external device, and the second latch LAT2 can temporarily store read data read by the sense circuit SEN. The read data stored in the second latch LAT2 can be transmitted to the sense node SO during an evaluation operation used to determine whether the verify operation has passed or failed. The k-th latch LATk can receive data input from an external device via the first data line DL1. For example, during a program operation, the k-th latch LATk can receive data loaded to (i.e., loaded onto) the first data line DL1 in response to the first column select signal CS1. During a read operation, the kth latch LATk may output read data read in response to the first column select signal CS1 to the first data line DL1 .

[0052] The first to k-th latches LAT1 to LATk may operate by receiving a first voltage V1 as a voltage source. The first voltage V1 may be an internal voltage that may also be used as a voltage source for the precharge circuit PRE and the sensing circuit SEN.

[0053] The second transmission circuit TRAN2 can transmit data loaded onto the sense node SO to the first cache latch CL1 via the first page bus PBUS1 in response to a second transmission signal TRANPB provided via the transmission line TRL. For example, the second transmission circuit TRAN2 can include a transmission switch SWt that can be turned on or off in response to the second transmission signal TRANPB. The transmission switch SWt can be implemented as an NMOS transistor. When the second transmission signal TRANPB is enabled at a voltage greater than a threshold voltage, the transmission switch SWt can be turned on. Therefore, data loaded onto the sense node SO can be transmitted to the first cache latch CL1 via the first page bus PBUS1. The transmission switch SWt can be turned on at a sufficient voltage level to transmit the data from the sense node SO to the first page bus PBUS1. This is because only when the transmission switch SWt is turned on at a sufficient voltage level can the read data loaded onto the sense node SO be quickly transmitted to the first cache latch CL1.

[0054] Figure 6 is a diagram illustrating a voltage drop occurring in the transmission line TRL. Figure 7 is a diagram illustrating the voltage of a transmission signal when a voltage drop occurs in the transmission line TRL.

[0055] Reference Figure 6 , the first to mth page buffers PB1 to PBm may respond to Figure 1 The page buffer control signal PBSIGS shown in FIG. 1 may include a plurality of signals for controlling the first to m-th page buffers PB1 to PBm. The second transfer signal TRANPB may be one of the plurality of signals included in the page buffer control signal PBSIGS. The second transfer signal TRANPB may be a plurality of signals included in the page buffer control signal PBSIGS. Figure 1 The logic circuit 180 shown is output via a transmission line TRL. Because the transmission line TRL is commonly coupled to the first to mth page buffers PB1 to PBm, the second transmission signal TRANPB output from the logic circuit 180 can be simultaneously transmitted to the first to mth page buffers PB1 to PBm. Therefore, when the second transmission signal TRANPB is applied to the transmission line TRL, the amount of current can be temporarily increased to fill the capacitance CP defined between the transmission line TRL and each of the first to mth page buffers PB1 to PBm. As a result, the voltage of the second transmission signal TRANPB may drop, and thus the voltage level of the second transmission signal TRANPB can slowly increase during the setup time. The voltage level of the second transmission signal TRANPB applied to the transmission line TRL is described in more detail below.

[0056] Reference Figure 7, the second voltage V2 can be used to enable the second transmission signal TRANPB. The second voltage V2 can be greater than the first voltage V1 and can be output from a pump (not shown). For example, the pump (not shown) can output a second voltage V2 that is greater than the first voltage V1 by pumping up the first voltage V1. Even when the second voltage V2 is greater than the first voltage V1, when the second voltage V2 is applied to the transmission line TRL having a potential of 0V, the voltage level of the second transmission signal TRANPB can increase to the first pre-voltage Vpr1 as the amount of current of the transmission line TRL increases. The first pre-voltage Vpr1 may be less than the second voltage V2 that is the target voltage of TRANPB. When the voltage level of the second transmission signal TRANPB increases to the first pre-voltage Vpr1 and then the amount of current of the transmission line TRL decreases, the voltage level of the second transmission signal TRANPB can increase from the first pre-voltage Vpr1 to the second voltage V2. Because the amount of current can slowly decrease through the capacitance CP of the transmission line TRL, the voltage level of the second transmission signal TRANPB can slowly increase to the second voltage V2. As Figure 7 As shown, when the second transmission signal TRANPB is instantaneously applied to the transmission line TRL in a state where the potential of the transmission line TRL is 0V, the voltage level of the second transmission signal TRANPB may take a first time T1 to increase to the second voltage V2.

[0057] Thus, according to an embodiment, a circuit that outputs the second transmission signal TRANPB to reduce the first time T1 may be provided.

[0058] Figure 8 is a diagram illustrating a pump voltage output circuit 200 according to an embodiment of the present disclosure.

[0059] Reference Figure 8 The pump voltage output circuit 200 may include a first voltage output circuit 210 and a second voltage output circuit 220 .

[0060] The first voltage output circuit 210 may be configured to output a first voltage V1 to the transmission line TRL in response to a first enable signal EN1 . The second voltage output circuit 220 may be configured to output a second voltage V2 to the transmission line TRL in response to a second enable signal EN2 .

[0061] The first voltage output circuit 210 may include a first switch SW1 coupled between a terminal provided with the first voltage V1 and the transmission line TRL. The first switch SW1 may be implemented as a PMOS transistor that transmits the first voltage V1 to the transmission line TRL in response to a first enable signal EN1.

[0062] The second voltage output circuit 220 may include a pump PMP configured to generate a second voltage V2 by pumping up the first voltage V1 , and a second switch SW2 configured to output the second voltage V2 to the transmission line TRL in response to a second enable signal EN2 .

[0063] The voltage level of the second transmission signal TRANPB output through the transmission line TRL may vary according to the voltages output from the first voltage output circuit 210 and the second voltage output circuit 220. For example, the first voltage output circuit 210 may output the first voltage V1 through the transmission line TRL before the second voltage output circuit 220 outputs the second voltage V2. In other words, the transmission line TRL may be precharged with the first voltage V1 before the second voltage V2 is output.

[0064] When the second voltage output circuit 220 outputs the second voltage V2 through the transmission line TRL in a state where the transmission line TRL is precharged with the first voltage V1 , the potential of the transmission line TRL may quickly increase to a target level as the second voltage V2 .

[0065] In other words, when the first voltage V1 has been applied to the transmission line TRL before the second voltage V2 is transmitted to the transmission line TRL, the voltage V1 may be filled. Figure 6 The transmission line TRL shown in FIG. 1 and each of the first to mth page buffers PB1 to PBm are connected to each of the first to mth page buffers PB1 to PBm. Figure 6 When the second voltage V2 is applied to the transmission line TRL in a state where the capacitor CP is filled, the phenomenon that the current amount of the transmission line TRL increases rapidly can be slowed down, so the potential of the transmission line TRL can quickly increase to the second voltage V2.

[0066] The operation of the pump voltage output circuit 200 is described in more detail below.

[0067] Figure 9 is a diagram illustrating a method of operating the pump voltage output circuit 200 .

[0068] Reference Figure 8 and Figure 9, the pump voltage output circuit 200 may activate the first enable signal EN1 to a low level L before outputting the second voltage V2. For example, the pump voltage output circuit 200 may output the second transmission signal TRANPB having the level of the first voltage V1 by activating the first enable signal EN1 to a low level L before a time Ta. In one type of system that has been proposed, the time Ta may be the time when the second voltage V2 is started to be output to the transmission line TRL. However, according to an embodiment of the present disclosure, the first voltage V1 may be applied to the transmission line TRL before the time Ta. In other words, according to an embodiment, the transmission line TRL may be precharged with the first voltage V1 before the second voltage V2 is applied to the transmission line TRL.

[0069] When the transmission line TRL is precharged with the first voltage V1, the pump voltage output circuit 200 can output the second voltage V2 by activating the second enable signal EN2 to a low level L before time Tb. The second voltage V2 may be greater than the first voltage V1, and the first voltage V1 may be greater than 0V.

[0070] Therefore, when Figure 6 When the first to m-th page buffers PB1 to PBm included in the page buffer group 140 output the second transmission signal TRANPB, the first voltage V1 is applied to the transmission line TRL in advance, and thus, the transmission line TRL is Figure 6 The capacitor CP shown in can be charged in advance. Therefore, when the second voltage V2 is applied to the transmission line TRL at time Tb, the second voltage V2 can be applied to the transmission line TRL without a voltage drop (91).

[0071] Alternatively, when the second voltage V2 is applied to the transmission line TRL at time Tb, the current of the transmission line TRL may temporarily increase, and the voltage level of the second transmission signal TRANPB may temporarily decrease (92). However, even when the voltage level of the second transmission signal TRANPB temporarily decreases to the second pre-voltage Vpr2 (92), since the transmission line TRL is pre-charged with the first voltage V1, the second pre-voltage Vpr2 may be greater than Figure 7 Therefore, the time for the voltage level of the second transmission signal TRANPB to temporarily decrease to the level of the second pre-voltage Vpr2 and then recover to the level of the second voltage V2 can be short.

[0072] Therefore, the second time T2 taken for the voltage level of the transmission line TRL to increase to the second voltage V2 from the time Ta may be longer than the second time T2. Figure 7 The first time T1 shown is short.

[0073] As described above, since the time it takes for the second voltage V2 having the target level to be applied to the transmission line TRL is shortened, the time it takes to transfer data between the page buffer and the cache latch can be shortened. Therefore, the time it takes to perform a program operation or a read operation of the memory device can be shortened.

[0074] Figure 10 is a diagram illustrating a memory system 1000 including a memory device 1100 according to an embodiment of the present disclosure.

[0075] Reference Figure 10 , the memory system 1000 may include a memory device 1100 and a controller 1200 that communicates between the memory device 1100 and a host 2000 .

[0076] In addition, the memory device 1100 may be configured as Figure 1 Memory device 1100 is shown.

[0077] The memory system 1000 may include multiple memory devices 1100, and the memory devices 1100 may be coupled to the controller 1200 via at least one channel. For example, the multiple memory devices 1100 may be coupled to a single channel. If multiple channels are coupled to the controller 1200, the multiple memory devices 1100 may be coupled to the channels, respectively.

[0078] The controller 1200 can communicate between the host 2000 and the memory device 1100. The controller 1200 can control the memory device 1100 in response to a request from the host 2000, or can perform background operations without a request from the host 2000 to improve the performance of the memory system 1000. The host 2000 can generate requests for various operations and can output the generated requests to the memory system 1000. For example, the request may include a program request for controlling a program operation, a read request for controlling a read operation, or an erase request for controlling an erase operation.

[0079] The host 2000 can communicate with the memory system 1000 through any of a variety of interfaces such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0080] Figure 11 is a diagram illustrating a memory system including a memory device 1100 according to another embodiment of the present disclosure.

[0081] Reference Figure 11 The memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100 , a controller 1200 , and a card interface 7100 .

[0082] In addition, the memory device 1100 may be configured as Figure 1 Memory device 1100 is shown.

[0083] The controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. According to an embodiment, the card interface 7100 may be, but is not limited to, a secure digital (SD) card interface or a multimedia card (MMC) interface.

[0084] The card interface 7100 may interface data exchange between the host 60000 and the controller 1200 according to the protocol of the host 60000. Depending on the embodiment, the card interface 7100 may support the Universal Serial Bus (USB) protocol and the Inter-Chip (IC)-USB protocol. The card interface 7100 may refer to hardware supporting the protocol used by the host 60000, software installed on the hardware, or a signal transmission method.

[0085] When the memory system 70000 is connected to the host interface 6200 of a host 60000 such as a PC, a tablet PC, a digital camera, a digital audio player, a cellular phone, console video game hardware, or a digital set-top box, the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 in response to the control of the microprocessor (μP) 6100.

[0086] According to an embodiment of the present disclosure, an operation time of a memory device may be shortened and reliability of the memory device may be improved by suppressing a voltage drop of a signal controlling a page buffer included in the memory device.

[0087] While embodiments of the present invention have been illustrated and described, those skilled in the art will recognize, based on this disclosure, that various modifications may be made within the spirit and scope of the invention. The invention encompasses all such modifications that fall within the scope of the appended claims.

[0088] CROSS-REFERENCE TO RELATED APPLICATIONS

[0089] This application claims priority from Korean Patent Application No. 10-2020-0088433, filed on Jul. 16, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A memory device, comprising: a latch configured to sense a voltage or a current of a bit line coupled to a memory cell and store read data; a transfer circuit configured to output the read data stored in the latch through a page bus in response to a transfer signal; a cache latch configured to receive the read data through the page bus and temporarily store the read data; as well as A pump voltage output circuit is coupled to the transmission circuit through a transmission line and is configured to apply a second voltage greater than the first voltage after applying a first voltage to the transmission line for a set time.

2. The memory device according to claim 1, wherein The cache latch is configured to transfer data input from an external device to the latch through the page bus during a program operation.

3. The memory device according to claim 1, wherein The transmission circuit includes a switch that electrically couples or disconnects the latch and the transmission line in response to the transmission signal.

4. The memory device according to claim 3, wherein The switch is configured to be turned on in response to the transmission signal.

5. The memory device according to claim 1, wherein The pump voltage output circuit comprises: a first voltage output circuit configured to output the first voltage in response to a first enable signal; and A second voltage output circuit is configured to output the second voltage in response to a second enable signal. The memory device according to claim 5 , wherein: The first voltage output circuit includes a first switch coupled between a terminal to which the first voltage is applied and the transmission line and transmitting the first voltage to the transmission line in response to the first enable signal.

7. The memory device according to claim 5, wherein The second voltage output circuit includes a pump and a second switch coupled in series between a terminal to which the first voltage is applied and the transmission line.

8. The memory device according to claim 7, wherein The pump generates the second voltage by pumping up the first voltage, and The second switch transmits the second voltage to the transmission line in response to the second enable signal.

9. The memory device according to claim 8, wherein After transmitting the first voltage to the transmission line using the first voltage output circuit, the pump voltage output circuit transmits the second voltage to the transmission line using the second voltage output circuit.

10. A memory device, comprising: a latch configured to sense a voltage or a current of a bit line coupled to a memory cell and store read data; a switch configured to output the read data stored in the latch through a page bus in response to a transmission signal; a cache latch configured to receive the read data through the page bus and temporarily store the read data; and a pump voltage output circuit, the pump voltage output circuit being coupled to a gate of the switch and outputting the transmission signal to the gate, Wherein, the pump voltage output circuit is configured as follows: Before transmitting the read data to the page bus, increasing the potential of the gate to a first voltage; and When the read data is transmitted to the page bus, the transmission signal of a second voltage is output to the gate, the second voltage being greater than the first voltage. The memory device according to claim 10 , wherein: The pump voltage output circuit comprises: a first voltage output circuit configured to output the first voltage to the gate in response to a first enable signal; and A second voltage output circuit is configured to output the second voltage to the gate in response to a second enable signal.

12. The memory device according to claim 11, wherein After outputting the first voltage to the gate using the first voltage output circuit, the pump voltage output circuit outputs the second voltage to the gate using the second voltage output circuit.

13. The memory device according to claim 11, wherein The first voltage output circuit includes a transistor that transmits the first voltage to the gate in response to the first enable signal.

14. The memory device according to claim 11, wherein The second voltage output circuit includes: a pump that generates the second voltage by pumping up the first voltage; and A transistor that transmits the second voltage to the gate in response to the second enable signal.

15. The memory device according to claim 10, wherein The switch is implemented as a transistor having a conduction level adjusted according to the level of the transmission signal.

16. A method of operating a memory device, the method comprising the steps of: storing read data in a latch of the page buffer by reading a memory cell; precharging a gate of a transmission switch coupled between the latch and a cache latch by applying a first voltage to the gate; as well as turning on the transmission switch by applying a second voltage greater than the first voltage to the gate when the gate is precharged, Wherein, the first voltage is a positive voltage.

17. The method according to claim 16, wherein The first voltage is provided as a voltage source of a circuit included in the page buffer.

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