Method for manufacturing a semiconductor device

Abstract

An embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor structure, the semiconductor structure comprising a plurality of first target regions and at least one second target region, the plurality of first target regions being divided by the at least one second target region, the upper surface of the first target region being higher than the upper surface of the second target region; forming a filling material layer on the semiconductor structure; performing a planarization process on the filling material layer; forming a patterned photoresist layer on the semiconductor structure, and etching the first target region through the patterned photoresist layer. In the above method, the filling material layer is planarized, and on the basis of filling the second target region with the filling material, the upper surface of the first target region is made flush with the upper surface of the second target region, thereby reducing the adverse effects of the height difference between the first target region and the second target region on subsequent processes, thereby improving the stability of the semiconductor manufacturing process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] With the rapid development of the electronics industry, there is an increasing demand for high-performance, low-cost semiconductor devices. Three-dimensional (3D) memory, a typical vertical channel memory, has gained widespread application due to its ability to significantly increase memory integration. A 3D memory typically includes a substrate and a stacked structure located on the substrate. However, as the number of stacked layers (tiers) increases, the manufacturing process becomes increasingly complex. Summary of the Invention

[0003] In view of this, the present application provides a method for manufacturing a semiconductor device in order to solve at least one technical problem existing in the prior art.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] An embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0006] Providing a semiconductor structure, the semiconductor structure comprising a plurality of first target regions and at least one second target region, the plurality of first target regions being divided by the at least one second target region, and an upper surface of the first target region being higher than an upper surface of the second target region;

[0007] forming a filling material layer on the semiconductor structure;

[0008] performing a planarization process on the filling material layer;

[0009] A patterned photoresist layer is formed on the semiconductor structure, and the first target area is etched through the patterned photoresist layer.

[0010] According to one embodiment of the present application, the planarizing process of the filling material layer includes:

[0011] The filling material layer is planarized so that an upper surface of the filling material layer is flush with an upper surface of the first target area and the upper surface of the first target area is exposed.

[0012] According to one embodiment of the present application, the planarizing process of the filling material layer includes:

[0013] The filling material layer is planarized, and the planarized filling material layer covers the first target area and the second target area.

[0014] According to an embodiment of the present application, the material of the filling material layer is the same as the material of the patterned photoresist layer.

[0015] According to one embodiment of the present application, the first target area is a chip area, and the second target area is a cutting groove.

[0016] According to one embodiment of the present application, the semiconductor structure further includes a photolithography alignment mark located in the second target area; and forming a patterned photoresist layer on the semiconductor structure includes:

[0017] forming a photoresist layer on the semiconductor structure;

[0018] Illuminating the photolithography alignment mark with a detection light source to obtain a mark signal corresponding to the photolithography alignment mark, converting the mark signal into an electrical signal, and obtaining position information of the photolithography alignment mark through the electrical signal;

[0019] The photoresist layer is exposed and developed to form the patterned photoresist layer.

[0020] According to one embodiment of the present application, the semiconductor structure further includes a photolithography alignment mark located in the second target area; after etching the first target area through the patterned photoresist layer, the method further includes:

[0021] The patterned photoresist layer and the filling material layer are removed to expose the photolithography alignment mark.

[0022] According to one embodiment of the present application, the method further includes: simultaneously removing the patterned photoresist layer and the filling material layer.

[0023] The present application provides a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor structure, the semiconductor structure comprising a plurality of first target regions and at least one second target region, the plurality of first target regions being divided by the at least one second target region, the upper surface of the first target region being higher than the upper surface of the second target region; forming a filling material layer on the semiconductor structure; performing a planarization process on the filling material layer; forming a patterned photoresist layer on the semiconductor structure, and etching the first target region through the patterned photoresist layer. The method for manufacturing a semiconductor device provided in an embodiment of the present application performs a planarization process on the filling material layer, and on the basis of filling the second target region with the filling material, makes the upper surface of the first target region flush with the upper surface of the second target region, thereby reducing the adverse effects of the height difference between the first target region and the second target region on subsequent processes, thereby reducing the error of the semiconductor device manufacturing process, and thus improving the stability of the semiconductor device manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 、 Figure 2 、 Figure 3A and Figure 3B ,as well as Figure 4A and Figure 4B A schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0025] Figure 5 、 Figure 6 、 Figure 7A and Figure 7B 、 Figure 8A and Figure 8B 、 Figure 9 、 Figure 10 as well as Figure 11 A schematic cross-sectional view of a method for manufacturing a semiconductor device according to another embodiment of the present application;

[0026] Figure 12 A process flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0027] The figure includes: 100-first target area; 100a-upper surface of the first target area; 200-second target area; 200a-upper surface of the second target area; 300-substrate; 400-filling material layer; 400a-upper surface of the filling material layer; 500-photoresist layer; 600-patterned photoresist layer; 101-chip area; 101a-upper surface of the chip area; 201-cutting groove; 201a-upper surface of the cutting groove; 301-wafer; 700-photolithography alignment mark; 800-opening. DETAILED DESCRIPTION

[0028] The following will be combined with the embodiments of this application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0030] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0031] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0032] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0035] With the rapid development of the electronics industry, three-dimensional (3D) memory has attracted increasing attention due to its three-dimensional development characteristics. It can achieve higher storage density by forming a stacked structure with more tiers.

[0036] A three-dimensional memory device may include a peripheral circuit area and a memory array area. The peripheral circuit area not only provides power to the memory array area but also performs logic operations and electrostatic protection. The memory array area may include a core area and a staircase area. The staircase area may be located on at least one side of the core area and is used to extract electrical signals from the gate layer in the memory array area. The gate layer serves as the word line for the memory array area, performing operations such as read, program, and erase.

[0037] Figure 12 The process flow of the method for manufacturing a semiconductor device provided by an embodiment of the present application is shown. Figure 12 As shown, in step S1201, a semiconductor structure is provided, which includes multiple first target areas and at least one second target area, the multiple first target areas are divided by the at least one second target area, and the upper surface of the first target area is higher than the upper surface of the second target area.

[0038] like Figure 1 As shown, the semiconductor structure includes a plurality of first target areas 100 and at least one second target area 200, and the plurality of first target areas 100 are divided by at least one second target area 200, that is, the semiconductor structure includes a plurality of first target areas 100 and second target areas 200 distributed at intervals on a substrate 300, wherein the upper surface 100a of the first target area is higher than the upper surface 200a of the second target area. Figure 1 Only two first target areas and one second target area are shown, and the second target area is located between the two first target areas. Figure 1 It can be understood that since the upper surfaces of the first target areas on both sides of the second target area are higher, the second target area appears as a recessed area between the two first target areas, that is, the upper surfaces of the first target area and the second target area appear concave in the cross-sectional view.

[0039] In fact, the number of the first target areas and the second target areas is not limited thereto, and the positional relationship between the first target areas and the second target areas is not limited thereto.

[0040] In some embodiments of the present application, the number of first target areas and second target areas can be set according to actual needs. For example, the number of first target areas can be 10, 20, or 30, and the number of second target areas can be 5, 15, or 25, etc. These first target areas and second target areas are arranged at intervals. Of course, the number of first target areas and second target areas is not limited to the above examples and can be any number.

[0041] In other embodiments of the present application, the number of the first target area and the second target area may also be determined according to the actual circuit layout.

[0042] In some embodiments of the present application, the positional relationship between the first target area and the second target area is not limited to Figure 1 For example, the first target area may be located between two second target areas, and since the upper surface of the first target area is higher than the upper surface of the second target area, the upper surfaces of the first target area and the second target area appear convex in the cross-sectional view.

[0043] In other embodiments of the present application, the first target area and the second target area may be located at the edge of the circuit layout. For example, the first target area is close to one side of the edge of the circuit layout and is adjacent to the second target area. Because the upper surface of the first target area is higher than the upper surface of the second target area, the upper surfaces of the first target area and the second target area appear stepped in a cross-sectional view.

[0044] In some embodiments of the present application, the semiconductor device may include a three-dimensional memory, and in particular, a 3D NAND memory.

[0045] like Figure 12 As shown, in step S1202 , a filling material layer is formed on the semiconductor structure.

[0046] like Figure 2 As shown, a filling material layer 400 is formed on the semiconductor structure, that is, a filling material layer 400 covering the first target area 100 and the second target area is formed. In some embodiments of the present application, a spin coating process can be used to form the filling material layer on the upper surface of the first target area and the second target area. Figure 2 Due to the height difference between the upper surfaces of the first and second target areas, the upper surface of the filling material layer covering the upper surfaces of the first and second target areas is uneven. Specifically, the portion of the filling material layer located in the second target area is recessed. Furthermore, the recessed area of ​​the upper surface of the filling material layer corresponds to the second target area. It is understood that the greater the height difference between the upper surfaces of the first and second target areas, the greater the arc of the recessed portion of the upper surface of the filling material layer located in the second target area.

[0047] It should be noted that the coating thickness of the filling material layer is at least greater than the height difference between the upper surface of the first target area and the upper surface of the second target area.

[0048] like Figure 12 As shown, in step S1203, the filling material layer is planarized; in step S1204, a patterned photoresist layer is formed on the semiconductor structure, and the first target area is etched through the patterned photoresist layer.

[0049] In some embodiments of the present application, the filling material layer can be planarized so that the upper surface of the filling material layer is parallel to the upper surface of the first target area. Here, the planarization process can use a chemical mechanical polishing (CMP) process. After the filling material layer is subjected to chemical mechanical polishing, the recessed area of ​​the filling material layer is eliminated, and the upper surface of the filling material layer presents a flat or smooth plane. In this way, in the subsequent manufacturing process, other layer structures can be further deposited on the planarized filling material layer, which can reduce the error of the semiconductor manufacturing process and improve the stability of the semiconductor device manufacturing process.

[0050] In some embodiments of the present application, Figure 3A As shown, the filling material layer 400 is subjected to chemical mechanical polishing to make the upper surface 400 a of the filling material layer flush with the upper surface 100 a of the first target area and expose the upper surface 100 a of the first target area.

[0051] refer to Figure 4A A photoresist layer 500 is formed on the filling material layer 400 and the first target region 100. After chemical mechanical polishing, the upper surface of the filling material layer is flattened and forms a plane parallel to the substrate together with the upper surface of the first target region.

[0052] In some embodiments of the present application, the semiconductor structure can be fixed on the wafer stage of the coating equipment. After photoresist is dripped on the surface of the semiconductor structure, the wafer stage is rotated and the centrifugal force generated by the rotation is used to evenly distribute the photoresist on the surface of the semiconductor structure.

[0053] According to the needs of the actual manufacturing process, a photoresist layer can be further formed on the filling material layer and the first target area. In some embodiments of the present application, a spin coating process can be adopted to form a photoresist layer on the filling material layer and the first target area. As previously mentioned, the upper surface of the filling material layer and the upper surface of the first target area together constitute a plane parallel to the substrate. Taking into account the characteristics of the spin coating process, the upper surface of the photoresist layer formed is also a flattened plane, which is parallel to the upper surface of the filling material layer and also parallel to the upper surface of the first target area. In general, the upper surface of the filling material layer formed is conducive to forming a flattened upper surface of the photoresist, which ultimately helps to reduce the error of the subsequent manufacturing process.

[0054] In other embodiments of the present application, Figure 3BAs shown, the filling material layer 400 is subjected to chemical mechanical polishing to make the upper surface 400a of the filling material layer higher than the upper surface 100a of the first target area. At this time, the upper surface 400a of the filling material layer is parallel to the plane of the substrate 300. At this time, the planarized filling material layer covers the first target area and the second target area.

[0055] refer to Figure 4B A photoresist layer 500 is formed on the filling material layer 400. After the chemical mechanical polishing process, the filling material layer now completely covers the upper surfaces of the first target area and the second target area, and the upper surface of the filling material layer presents a flat surface.

[0056] According to the needs of the actual manufacturing process, a photoresist layer can be further formed on the filling material layer. In some embodiments of the present application, a spin coating process can be adopted to form a photoresist layer on the filling material layer. As previously mentioned, the upper surface of the filling material layer is parallel to the upper surface of the first target area. Taking into account the characteristics of the spin coating process, the upper surface of the photoresist layer formed is also a flattened plane, which is parallel to the upper surface of the filling material layer, that is, also parallel to the upper surface of the first target area. In general, the upper surface of the filling material layer formed is flattened, which helps to form a flattened upper surface of the photoresist, and ultimately helps to reduce the error of the subsequent manufacturing process.

[0057] The manufacturing method of the semiconductor device provided in the embodiment of the present application flattens the filling material layer, and on the basis of filling the second target area with the filling material, makes the upper surface of the first target area flush with the upper surface of the second target area, thereby reducing the adverse effects of the height difference between the first target area and the second target area on subsequent processes, thereby reducing the error of the semiconductor device manufacturing process and improving the stability of the semiconductor device manufacturing process.

[0058] The following description will be made with the first target area being the chip area and the second target area being the cutting groove. Figures 5 to 11 This is a schematic diagram of a cross-sectional structure of a method for manufacturing a semiconductor device provided in another embodiment of the present application. Figure 5 As shown, the semiconductor structure may include a plurality of spaced-apart chip regions 101 and cut grooves 201 on a wafer 301 , wherein the upper surface 101 a of the chip region is higher than the upper surface 201 a of the cut groove. Furthermore, the semiconductor structure may include a photolithography alignment mark 700 located within the cut groove 201 . Figure 5 Only two chip areas and one cutting groove are shown, and the cutting groove is located between the two chip areas. Figure 5 It can be understood that since the upper surfaces of the chip areas on both sides of the cutting groove are higher, the cutting groove appears as a recessed area between the two chip areas, that is, the upper surfaces of the chip areas and the cutting groove appear concave in the cross-sectional view.

[0059] In practice, a wafer is typically divided into several spaced-apart chip areas, with dicing grooves separating adjacent chip areas. The wafer is typically processed as a whole, and only during the subsequent chip packaging process are dicing performed within the dicing grooves, resulting in individual chips that are then packaged.

[0060] like Figure 6 As shown, a filling material layer 400 is formed on the semiconductor structure, that is, a filling material layer 400 covering the chip region 101 and the cutting groove is formed. In some embodiments of the present application, a spin coating process can be used to form a filling material layer on the upper surface of the chip region and the cutting groove. Figure 6 Due to the height difference between the chip area and the upper surface of the cutting groove, the upper surface of the filling material layer covering the chip area and the upper surface of the cutting groove is uneven. Specifically, the portion of the filling material layer located in the cutting groove is recessed. Furthermore, the recessed area of ​​the upper surface of the filling material layer corresponds to the cutting groove. It is understood that the greater the height difference between the upper surface of the chip area and the upper surface of the cutting groove, the greater the curvature of the recessed portion of the upper surface of the filling material layer located in the cutting groove.

[0061] It should be noted that the coating thickness of the filling material layer is at least greater than the height difference between the upper surface of the chip region and the upper surface of the cutting groove.

[0062] Typically, in order to facilitate the removal of the filling material layer and the photoresist layer in subsequent processes, photoresist can also be used as the filling material layer. It is understandable that with the rapid development of the electronics industry, three-dimensional memory achieves higher storage density by forming a stacked structure with more layers. The three-dimensional memory may include a peripheral circuit area and a memory array area, wherein the memory array area may include a core area and a step area. Among them, the step area may be located on at least one side of the core area to lead out the electrical signal of the gate layer in the memory array area. In other words, the step height (step high) of the memory array area is getting higher and higher. Then, in order to etch the above-mentioned step area, the thickness of the photoresist layer (PR) required is also getting larger and larger. As the height of the memory array area becomes larger and larger, the thickness of the required photoresist layer is also getting larger and larger. For example, the thickness of the photoresist layer gradually increases from 5μm to 8μm, 10μm, 12μm, and so on.

[0063] It is worth noting that the increase in the step height causes the upper surface of the filling material layer formed on the photolithography alignment mark in the cutting groove to become more uneven. In other words, the greater the height difference between the upper surface of the chip area and the upper surface of the cutting groove, the greater the arc of the downward depression of the portion of the filling material layer located in the cutting groove. It can be understood that the role of the photolithography alignment mark is to use a detection light source to illuminate the photolithography alignment mark, obtain a mark signal corresponding to the photolithography alignment mark, convert the mark signal into an electrical signal, and obtain the position information of the photolithography alignment mark through the electrical signal. Then, in the case that the filling material layer on the photolithography alignment mark is uneven, it will affect the signal strength and integrity of the photolithography alignment mark, thereby causing a large measurement error and resulting in a deterioration in the overlay accuracy (OVL), and even wafer rejection.

[0064] "Registration accuracy" here refers to the accuracy of the alignment between the current layer and the previous layer. If the overlay accuracy exceeds the error tolerance, the interlayer design circuit may be disconnected or shorted due to displacement, thus affecting product yield. "Wafer rejection" here refers to the excessive deviation between coarse and fine alignment on the silicon wafer workbench, resulting in the wafer being rejected by the photolithography machine for exposure, resulting in wafer exposure failure and requiring rework (rework) to strip the photoresist.

[0065] In some embodiments of the present application, the unevenness of the filler material layer can be improved by slowing down the spin coating rate of the filler material coating. On the one hand, the probability of wafer rejection is reduced when the surface of the filler material layer is smoother, but residual overlay performance (ROPI) still exists. On the other hand, the reduced spin coating rate may lead to a decrease in wafer output per hour (WPH), that is, a decrease in production output.

[0066] Based on the measurement results of the lithography alignment marks on the reference layer on the wafer, the lithography machine calculates a grid of exposure positions for the current layer according to the model and then performs exposure according to this grid. Due to the incompleteness of the model, although the exposure grid is calculated based on the measurement data, it still deviates from the actual measured grid. This deviation is called the "corrected residual." The size of the corrected residual value indicates the effectiveness of the correction; a smaller ROPI indicates a better correction effect.

[0067] Therefore, there is a need for a method for manufacturing a semiconductor device that can reduce errors in the manufacturing process, especially in the photolithography process, so as to improve the stability of the manufacturing process.

[0068] In some embodiments of the present application, Figure 7A As shown, the filling material layer 400 is subjected to chemical mechanical polishing treatment so that the upper surface 400 a of the filling material layer is flush with the upper surface 101 a of the chip region and the upper surface 101 a of the chip region is exposed.

[0069] refer to Figure 8A A photoresist layer 500 is formed on the filling material layer 400 and the chip region 101. After chemical mechanical polishing, the upper surface of the filling material layer is flattened, and together with the upper surface of the chip region, forms a plane parallel to the wafer.

[0070] Continue to form a photoresist layer on the filling material layer and the chip area. In some embodiments of the present application, a spin coating process can be adopted to form a photoresist layer on the filling material layer and the chip area. As previously mentioned, the upper surface of the filling material layer and the upper surface of the chip area constitute a plane parallel to wafer together. Considering the characteristics of the spin coating process, the upper surface of the photoresist layer formed is also a planarized plane, which is parallel to the upper surface of the filling material layer and also parallel to the upper surface of the chip area. Generally speaking, the upper surface of the filling material layer formed is planarized, which helps to form the upper surface of the planarized photoresist. That is to say, the filling material layer above the photolithography alignment mark and the topography (topography) of the photoresist layer are flat, to ensure the signal strength and integrity of the photolithography alignment mark.

[0071] In some embodiments of the present application, a wafer can be fixed on a wafer stage of a coating device. After photoresist is dripped onto the surface of the wafer, the wafer stage is rotated and the centrifugal force generated by the rotation is used to evenly distribute the photoresist on the surface of the wafer.

[0072] In other embodiments of the present application, Figure 7B As shown, the filling material layer 400 is subjected to chemical mechanical polishing to make the upper surface 400a of the filling material layer higher than the upper surface 101a of the chip region. The upper surface 400a of the filling material layer is parallel to the surface of the wafer 301. At this point, the planarized filling material layer covers the upper surface of the chip region and the cutting groove.

[0073] refer to Figure 8B , a photoresist layer 500 is formed on the filling material layer 400. After the chemical mechanical polishing process, the filling material layer now completely covers the upper surface of the chip region, and the upper surface of the filling material layer presents a flat surface.

[0074] Continue to form a photoresist layer on the filling material layer. In some embodiments of the present application, a spin coating process can be adopted to form a photoresist layer on the filling material layer. As previously mentioned, the upper surface of the filling material layer is parallel to the upper surface of the chip area. Taking into account the characteristics of the spin coating process, the upper surface of the photoresist layer formed is also a planarized plane, which is parallel to the upper surface of the filling material layer, that is, also parallel to the upper surface of the chip area. In general, the upper surface of the filling material layer formed is flat, which helps to form the upper surface of the planarized photoresist. In other words, the topography of the filling material layer and the photoresist layer above the photolithography alignment mark is flat, to ensure the signal strength and integrity of the photolithography alignment mark.

[0075] In some embodiments of the present application, a photoresist layer can be formed on the semiconductor structure; a detection light source is used to illuminate a photolithography alignment mark to obtain a mark signal corresponding to the photolithography alignment mark, and the mark signal is converted into an electrical signal, and the position information of the photolithography alignment mark is obtained through the electrical signal; the photoresist layer is exposed and developed to form the patterned photoresist layer.

[0076] like Figure 9 、 Figure 10 and Figure 11 As shown, taking the case where the upper surface 400a of the filling material layer is flush with the upper surface 101a of the chip region as an example, the photoresist layer is exposed and developed to form a patterned photoresist layer 600. After the chip region 101 is etched through the patterned photoresist layer 600, an opening 800 is formed. The patterned photoresist layer 600 and the filling material layer 400 are removed to expose the photolithography alignment mark 700. Planarizing the filling material layer helps form a flat photoresist layer, thereby ensuring the signal strength and integrity of the photolithography alignment mark. After the subsequent litho / etch process, the patterned photoresist layer and the filling material layer can be removed in sequence.

[0077] In a preferred embodiment of the present application, the material of the filling material layer is the same as the material of the patterned photoresist layer. In this way, after performing the photolithography / etching process, the patterned photoresist layer and the filling material layer can be removed simultaneously to expose the photolithography alignment marks. It is understandable that the filling material layer here only serves as a filling material for the cutting groove and has no functional role. Therefore, the material forming the filling material layer can be photoresist or other materials. When the material of the filling material layer is the same as the material of the patterned photoresist layer, the patterned photoresist layer and the filling material layer can be removed simultaneously and using the same process without adding additional process steps.

[0078] In some embodiments of the present application, when the material of the filling material layer and the material of the photoresist layer are the same, that is, when both are photoresists, the method for removing the photoresist may include ashing the filling material layer and / or the patterned photoresist layer on the semiconductor structure (e.g., a wafer), and wet stripping the ashed photoresist. Specifically, the semiconductor structure is placed on an ashing device, and the photoresist on the semiconductor structure is ashed at a relatively high temperature (e.g., above 250° C.) to prevent the metal on the semiconductor structure from recrystallizing; then, wet stripping is used to remove residues (e.g., burnt residues of the photoresist) after the ashing process.

[0079] In some embodiments of the present application, the ashing process may utilize a gas to react with the photoresist. For example, oxygen (O2) may be used to burn the photoresist, converting it into carbon dioxide (CO2) for discharge. However, after the ashing process, burnt residues of the photoresist may remain attached to the semiconductor structure. Therefore, it is difficult to completely remove the photoresist through ashing.

[0080] In some embodiments of the present application, after the ashing process, wet stripping may be used to remove residues from the ashing process, for example, by using diluted sulfuric acid (H 2 SO 4 ) and hydrofluoric acid (HF).

[0081] In some embodiments of the present application, after removing the photoresist, the following may also be included: detecting the surface morphology of the semiconductor structure (for example, a wafer and a device structure formed on the wafer) through an optical microscope to determine whether the surface morphology of the semiconductor structure meets the standard.

[0082] The present application provides a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor structure, the semiconductor structure comprising a plurality of first target regions and at least one second target region, the plurality of first target regions being divided by the at least one second target region, the upper surface of the first target region being higher than the upper surface of the second target region; forming a filling material layer on the semiconductor structure; flattening the filling material layer; forming a patterned photoresist layer on the semiconductor structure, and etching the first target region through the patterned photoresist layer. After covering the upper surfaces of the first target region and the second target region with the filling material layer, the filling material layer is flattened, and on the basis of filling the second target region with the filling material, the upper surface of the first target region is flush with the upper surface of the second target region, thereby reducing the adverse effects of the height difference between the first target region and the second target region on subsequent processes, thereby reducing errors in the semiconductor device manufacturing process and improving the stability of the semiconductor device manufacturing process.

[0083] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0084] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application description and drawings under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Providing a semiconductor structure, the semiconductor structure comprising a plurality of first target regions and at least one second target region, the plurality of first target regions being divided by the at least one second target region, and an upper surface of the first target region being higher than an upper surface of the second target region; forming a filling material layer on the semiconductor structure; performing a planarization process on the filling material layer; A patterned photoresist layer is formed on the semiconductor structure, and the first target area is etched through the patterned photoresist layer; wherein the second target area includes a photolithography alignment mark, and the photolithography alignment mark is used to provide a corresponding mark signal during the process of forming the patterned photoresist layer.

2. The manufacturing method according to claim 1, wherein The planarizing process of the filling material layer includes: The filling material layer is planarized so that an upper surface of the filling material layer is flush with an upper surface of the first target area and the upper surface of the first target area is exposed.

3. The manufacturing method according to claim 1, wherein The planarizing process of the filling material layer includes: The filling material layer is planarized, and the planarized filling material layer covers the first target area and the second target area.

4. The manufacturing method according to claim 1, wherein The material of the filling material layer is the same as that of the patterned photoresist layer.

5. The manufacturing method according to claim 1, wherein: The first target area is a chip region, and the second target area is a cutting groove.

6. The manufacturing method according to claim 1, wherein: The step of forming a patterned photoresist layer on the semiconductor structure comprises: forming a photoresist layer on the semiconductor structure; Illuminating the photolithography alignment mark with a detection light source to obtain a mark signal corresponding to the photolithography alignment mark, converting the mark signal into an electrical signal, and obtaining position information of the photolithography alignment mark through the electrical signal; The photoresist layer is exposed and developed to form the patterned photoresist layer.

7. The manufacturing method according to claim 1, wherein: After etching the first target area through the patterned photoresist layer, the method further includes: The patterned photoresist layer and the filling material layer are removed to expose the photolithography alignment mark.

8. The manufacturing method according to claim 4, wherein: The method further includes simultaneously removing the patterned photoresist layer and the filling material layer.

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