High-voltage MOS transistor and method for manufacturing the same

Abstract

The present invention provides a method for manufacturing a high-voltage MOS transistor, comprising: providing a substrate in which a shallow trench isolation structure is formed, and a pad oxide layer is further formed on its surface; forming a mask layer; etching the mask layer, the pad oxide layer, the shallow trench isolation structure and the substrate to obtain a stepped trench in the shallow trench isolation structure and the substrate and form a gate oxide layer in the stepped trench. In this application, by simultaneously etching the substrate and the shallow trench isolation structure in the high-voltage device region to form a stepped trench, the top surface of the gate oxide layer deposited in the stepped trench tends to be flush with the top surfaces of the gate oxide layers in other device (medium-voltage, low-voltage device) regions around it, thereby improving the height uniformity of the pseudo-polysilicon gate formed above the subsequent gate oxide layer, avoiding the situation that the pseudo-polysilicon gate in the high-voltage device region is overly mis-polished during the subsequent ILD0 CMP process, and thus ensuring the integrity of the metal gate.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor devices, and particularly to a high-voltage MOS transistor and a manufacturing method thereof. Background Art

[0002] As the size of transistors continues to shrink, HKMG (high-k insulating layer + metal gate) has gradually replaced the original silicon dioxide insulating layer + polysilicon gate configuration and become an essential part of the manufacturing process below 28 nm.

[0003] In the existing high-voltage MOS transistor, the gate oxide process directly grows a gate oxide layer on the surface of the silicon substrate. However, since the thickness of the gate oxide layer in the high-voltage MOS transistor is much thicker than that of other devices (such as medium-voltage and low-voltage MOS transistors) on the same wafer, in the high-voltage MOS transistor, the high-voltage gate oxide layer grown by the existing process will make the overall height of the high-voltage MOS transistor much higher than the overall height of the medium-voltage and low-voltage MOS transistors after the formation of the gate oxide layer.

[0004] Furthermore, in the high-voltage MOS transistor, the metal gate manufacturing process usually first fabricates a dummy poly gate, and then removes the dummy poly gate through the ILD0 CMP (interlayer dielectric chemical mechanical polishing) process, dry and / or wet etching processes in subsequent processes and leaves a trench, and finally fills the original trench with a metal material to finally form a metal gate. Among them, when performing the ILD0 CMP (interlayer dielectric chemical mechanical polishing) process, since all the devices on the same wafer are polished simultaneously, the dummy poly gate above the gate oxide layer in the high-voltage MOS transistor region is over-etched because it is higher than the dummy poly gate in the medium-voltage and low-voltage MOS transistor regions, which will affect the formation of the metal gate in the high-voltage MOS transistor. Even in extreme cases, after the ILD0 CMP process, the dummy poly gate in the high-voltage device region will be completely ground off, thus affecting the filling of the metal material, that is, affecting the formation of the metal gate in the high-voltage MOS transistor, and thus easily leading to the performance failure of the device. Summary of the Invention

[0005] This application provides a high-voltage MOS transistor and a manufacturing method thereof, which can solve the problems in the related art.

[0006] On the one hand, an embodiment of this application provides a manufacturing method of a high-voltage MOS transistor, including:

[0007] Providing a substrate, a shallow trench isolation structure is formed in the substrate, and a pad oxide layer is formed on the surface of the substrate around the shallow trench isolation structure;

[0008] Forming a mask layer, the mask layer covering the shallow trench isolation structure and the pad oxide layer;

[0009] Etch the mask layer and the pad oxide layer to expose part of the substrate and part of the shallow trench isolation structure;

[0010] Etch the shallow trench isolation structure and the substrate to form a stepped trench in the shallow trench isolation structure and the substrate; and,

[0011] Form a gate oxide layer, and the gate oxide layer fills the stepped trench.

[0012] Optionally, in the manufacturing method of the high-voltage MOS transistor, etch the mask layer and the pad oxide layer to expose the edge position of the shallow trench isolation structure and part of the substrate adjacent to the shallow trench isolation structure.

[0013] Optionally, in the manufacturing method of the high-voltage MOS transistor, the size of the exposed edge position of the shallow trench isolation structure in width is at least 800 angstroms.

[0014] Optionally, in the manufacturing method of the high-voltage MOS transistor, the etching thickness of the shallow trench isolation structure is less than the etching thickness of the substrate to obtain the stepped trench.

[0015] Optionally, in the manufacturing method of the high-voltage MOS transistor, after forming the gate oxide layer, the manufacturing method of the high-voltage MOS transistor further includes:

[0016] Wet-etch the mask layer.

[0017] Optionally, in the manufacturing method of the high-voltage MOS transistor, the thickness of the mask layer is 500 angstroms to 600 angstroms.

[0018] Optionally, in the manufacturing method of the high-voltage MOS transistor, use a high-temperature furnace tube oxidation process to grow the gate oxide layer in the stepped trench, and the process temperature is 800 °C to 1000 °C.

[0019] Optionally, in the manufacturing method of the high-voltage MOS transistor, the thickness of the gate oxide layer is 1100 angstroms to 1300 angstroms.

[0020] On the other hand, an embodiment of the present application further provides a high-voltage MOS transistor, including:

[0021] A substrate, in which a shallow trench isolation structure is formed, and a stepped trench is formed in the shallow trench isolation structure and the substrate;

[0022] A pad oxide layer, which covers the shallow trench isolation structure and the surface of the substrate around the stepped trench; and,

[0023] A gate oxide layer, which fills the stepped trench.

[0024] The technical solution of the present application has at least the following advantages:

[0025] The present application expands the exposure area to the edge position of the shallow trench isolation structure, and simultaneously etches the substrate in the high-voltage device region and the shallow trench isolation structure to form a stepped trench, so as to form a sunken gate oxide layer in the stepped trench, making the top surface of the sunken gate oxide layer tend to be flush with the top surfaces of the gate oxide layers in other device (medium-voltage, low-voltage device) regions around it. Furthermore, it improves the height uniformity of the dummy polycrystalline silicon gate (dummy poly) formed in the subsequent process, avoids the situation that the dummy polycrystalline silicon gate in the high-voltage device region is over-etched by mistake in the ILD0 CMP process, ensures that the dummy polycrystalline silicon gate has sufficient height, that is, ensures the integrity of the metal gate filled subsequently in the high-voltage device region, thereby improving the electrical performance and reliability of the device. Further, the present application does not need to introduce complex process steps to form the sunken gate oxide layer, and its process is simple. Description of the Drawings

[0026] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0027] Figure 1 is a flowchart of a method for manufacturing a high-voltage MOS transistor according to an embodiment of the present invention;

[0028] Figures 2 - 7 is a schematic diagram of a semiconductor structure in each process step of manufacturing a high-voltage MOS transistor according to an embodiment of the present invention;

[0029] Among them, the reference numerals are explained as follows:

[0030] 10 - Substrate, 20 - Shallow trench isolation structure, 30 - Pad oxide layer, 40 - Mask layer, 41 - Opening, 50 - Gate oxide layer, 100 - Stepped trench. Specific Embodiments

[0031] The following will clearly and completely describe the technical solutions in the present application in conjunction with the drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present application belong to the scope of protection of the present application.

[0032] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0033] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0034] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0035] The embodiment of the present application provides a manufacturing method of a high-voltage MOS transistor. Refer to Figure 1 , Figure 1 which is a flowchart of the manufacturing method of the high-voltage MOS transistor according to the embodiment of the present invention. The manufacturing method of the high-voltage MOS transistor includes:

[0036] S01: Provide a substrate, in which a shallow trench isolation structure (STI) is formed, and a pad oxide layer is formed on the surface of the substrate around the shallow trench isolation structure;

[0037] S02: Form a mask layer, and the mask layer covers the shallow trench isolation structure and the pad oxide layer;

[0038] S03: Etch the mask layer and the pad oxide layer to expose part of the substrate and part of the shallow trench isolation structure;

[0039] S04: Etch the shallow trench isolation structure and the substrate to form a stepped trench in the shallow trench isolation structure and the substrate; and,

[0040] S05: Form a gate oxide layer, and the gate oxide layer fills the stepped trench.

[0041] Specifically, please refer to Figures 2 - 7 , Figures 2 - 7It is a schematic diagram of a semiconductor structure in each process step of manufacturing a high-voltage MOS transistor according to an embodiment of the present invention.

[0042] First, please refer to Figure 2 , a substrate 10 is provided, a shallow trench isolation structure 20 is formed in the substrate 10, and a pad oxide layer 30 is formed on the substrate 10 around the shallow trench isolation structure 20. Specifically, the substrate 10 can be one of single-crystalline silicon, polycrystalline silicon, and amorphous silicon, the substrate 10 can also be gallium arsenide, silicon-gallium compound, etc., and the substrate 10 can also have a silicon-on-insulator or epitaxial layer structure on silicon; the substrate 10 can also be other semiconductor materials, which will not be listed one by one here. The substrate 10 can have an N-well or a P-well, etc. The pad oxide layer 30 is deposited on the surface of the substrate 10 by PVD process or CVD process first, and then the pad oxide layer 30 and the substrate 10 are opened by photolithography and etching processes to obtain a trench, and then an insulating material (oxide) is filled in the trench to form the shallow trench isolation structure 20. Among them, the thickness of the pad oxide layer 30 can be Due to the difference in stress (lattice mismatch) between the shallow trench isolation structure 20 and the substrate 10, the top surface of the shallow trench isolation structure 20 will be slightly higher than the top surface of the substrate 10.

[0043] Next, please refer to Figure 3 , a mask layer 40 is formed, and the mask layer 40 covers the shallow trench isolation structure 20 and the pad oxide layer 30. Specifically, in this embodiment, the mask layer 40 can be deposited by a thermal oxidation furnace tube growth process, and the thickness of the mask layer 40 can be The material of the mask layer 40 can be silicon nitride.

[0044] Furthermore, please refer to Figure 4 , the mask layer 40 and the pad oxide layer 30 are etched to expose part of the substrate 10 and part of the shallow trench isolation structure 20. Specifically, first, a high-voltage gate oxide region is defined on the mask layer 40 by photolithography, starting from Figure 4It can be seen that the high-voltage gate oxide region defined in this embodiment includes the surface of the substrate 10 and the edge position of the shallow trench isolation structure 20. Then, the mask layer 40 and the pad oxide layer 30 are etched back by a dry etching process to expose the edge position of the shallow trench isolation structure 20 and a part of the substrate 10 adjacent to the shallow trench isolation structure 20 to obtain an opening 41. The ratio of the etched thickness of the substrate 10 to the thickness of the subsequently formed gate oxide layer 50 can be 0.54:1, so that the top surface of the subsequently formed gate oxide layer 50 can be flush with the top surface of the substrate 10 or the top surface of the pad oxide layer 30. The edge position of the exposed shallow trench isolation structure 20 has a size in width of at least Finally, the photoresist remaining in the photolithography process is ashed and removed. Refer to Figure 7 , the present invention expands the exposure area to the edge position of the shallow trench isolation structure 20 so as to form a sunken gate oxide layer 50, and further, a sunken dummy poly structure is formed above the gate oxide layer 50 subsequently, reducing the overall height of the high-voltage device, reducing the height difference of the dummy poly structures among the high-voltage, medium-voltage, and low-voltage devices on the same wafer, and avoiding the situation that the pseudo polysilicon gate in the high-voltage device region is over-etched by mistake during the ILD0 CMP process. The present invention expands the exposure area to the edge position of the shallow trench isolation structure 20, and the edge position of the exposed shallow trench isolation structure 20 coincides with the edge position of the subsequently deposited dummy poly, which can further ensure the height uniformity of the deposited dummy poly.

[0045] Next, please refer to Figure 5 , the shallow trench isolation structure 20 and the substrate 10 are etched to form a stepped trench 100 in the shallow trench isolation structure 20 and the substrate 10. Specifically, the shallow trench isolation structure 20 and the substrate 10 are etched by a dry etching process. On the one hand, since the top surface of the shallow trench isolation structure 20 is higher than the top surface of the substrate 10, and on the other hand, since the etched thickness of the shallow trench isolation structure 20 is less than the etched thickness of the substrate 10, the stepped trench 100 is obtained in the shallow trench isolation structure 20 and the substrate 10, as shown in Figure 5As shown, in the stepped trench 100, the upper surface of the shallow trench isolation structure 20 is higher than the upper surface of the substrate 10. In the present invention, the stepped trench 100 is formed by simultaneously etching the substrate 10 and the shallow trench isolation structure 20 in the high-voltage device region, so that the top surface of the gate oxide layer 50 deposited in the stepped trench 100 tends to be flush with the top surfaces of the gate oxide layers in other device (medium-voltage and low-voltage device) regions around it. Furthermore, the height uniformity of the dummy poly formed in the subsequent process is improved, and the situation that the pseudo polysilicon gate in the high-voltage device region is over-etched by mistake in the ILD0 CMP process is avoided, ensuring that the pseudo polysilicon gate has sufficient height, that is, ensuring the integrity of the subsequently filled metal gate in the high-voltage device region, thereby improving the electrical performance and reliability of the device.

[0046] Finally, please refer to Figure 6 , to form the gate oxide layer 50, and the gate oxide layer 50 fills the stepped trench 100. Specifically, in this embodiment, the gate oxide layer 50 can be grown in the stepped trench 100 by using a high-temperature furnace tube oxidation process, and the process temperature is 800°C to 1000°C. The thickness of the gate oxide layer 50 is In the present invention, the thickness of the gate oxide layer 50 is not reduced at all compared with that of traditional high-voltage devices, which ensures the high-voltage resistance of the device and avoids the situation that the device is broken down due to insufficient insulation at high voltage. Therefore, in the present invention, under the condition that the insulation of the device is ensured, that is, under the condition that the insulation of the device is ensured, the sunken gate oxide layer 50 is formed, reducing the overall height of the high-voltage device.

[0047] Preferably, please refer to Figure 7 , after forming the gate oxide layer 50, the manufacturing method of the high-voltage MOS transistor may further include: wet-etching the mask layer 40.

[0048] Furthermore, after wet-etching the mask layer 40 in the present application, it further includes process steps such as depositing dummy poly, ILD0 CMP, removing dummy poly, and filling gate metal.

[0049] Based on the same inventive concept, an embodiment of the present application further provides a high-voltage MOS transistor. Please refer to Figure 7, the high-voltage MOS transistor includes: a substrate 10, a pad oxide layer 30, and a gate oxide layer 50. A shallow trench isolation structure 20 is formed in the substrate 10. The top surface of the shallow trench isolation structure 20 is higher than the top surface of the substrate 10. A stepped trench 100 is formed in the shallow trench isolation structure 20 and the substrate 10. The pad oxide layer 30 covers the surface of the substrate 10 except for the surface of the shallow trench isolation structure 20 and the stepped trench 100. The gate oxide layer 50 fills the stepped trench 100.

[0050] Obviously, the above embodiments are merely examples for clear illustration and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A manufacturing method of a high-voltage MOS transistor, characterized in that, comprising: providing a substrate, a shallow trench isolation structure is formed in the substrate, and a pad oxide layer is formed on the surface of the substrate around the shallow trench isolation structure; forming a mask layer, the mask layer covering the shallow trench isolation structure and the pad oxide layer; etching the mask layer and the pad oxide layer to expose a part of the substrate and a part of the shallow trench isolation structure; etching the shallow trench isolation structure and the substrate to form a stepped trench in the shallow trench isolation structure and the substrate; and, forming a gate oxide layer, the gate oxide layer filling the stepped trench to be flush with the top surface of the pad oxide layer.

2. The manufacturing method of a high-voltage MOS transistor according to claim 1, characterized in that, etching the mask layer and the pad oxide layer to expose the edge position of the shallow trench isolation structure and a part of the substrate adjacent to the shallow trench isolation structure.

3. The manufacturing method of a high-voltage MOS transistor according to claim 2, characterized in that, the dimension of the exposed edge position of the shallow trench isolation structure in width is at least 800 angstroms.

4. The manufacturing method of a high-voltage MOS transistor according to claim 1, characterized in that, the etching thickness of the shallow trench isolation structure is less than the etching thickness of the substrate to obtain the stepped trench.

5. The manufacturing method of a high-voltage MOS transistor according to claim 1, characterized in that, after forming the gate oxide layer, the manufacturing method of the high-voltage MOS transistor further comprises: removing the mask layer by wet etching.

6. The manufacturing method of a high-voltage MOS transistor according to claim 1, characterized in that, the thickness of the mask layer is 500 angstroms to 600 angstroms.

7. The manufacturing method of a high-voltage MOS transistor according to claim 1, characterized in that, using a high-temperature furnace tube oxidation process to grow the gate oxide layer in the stepped trench, and the process temperature is 800 °C to 1000 °C.

8. The manufacturing method of a high-voltage MOS transistor according to claim 1, characterized in that, the thickness of the gate oxide layer is 1100 angstroms to 1300 angstroms.

9. A high-voltage MOS transistor, characterized in that, comprising: a substrate, a shallow trench isolation structure is formed in the substrate, and the edge of the top surface of the shallow trench isolation structure is etched to form a stepped trench in the substrate; a pad oxide layer, the pad oxide layer covering the shallow trench isolation structure and the surface of the substrate around the stepped trench; and, a gate oxide layer, the gate oxide layer filling the stepped trench to be flush with the top surface of the pad oxide layer.

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