Isolation Method for Active Region of SOI

Abstract

The present invention discloses a method for isolating an active region of an SOI, comprising: Step 1, providing an SOI substrate structure and forming a hard mask layer on the semiconductor top layer surface of the SOI substrate; Step 2, performing patterned etching on the hard mask layer to form a first opening; Step 3, performing selective epitaxial growth to form a first epitaxial layer on the semiconductor top layer surface exposed by the first opening, and a first notch will be formed at the side of the first opening after the formation of the first epitaxial layer; Step 4, performing an oxidation process to oxidize the entire first epitaxial layer and also oxidize the semiconductor top layer at the bottom of the first notch and finally form a first oxide layer, and the first oxide layer will penetrate through the semiconductor top layer at the bottom of the first notch; Step 5, removing the hard mask layer and the first oxide layer, and forming an isolation groove at the position where the first oxide layer penetrates through the semiconductor top layer to isolate the active region. The present invention can achieve ultra-small gap cutting of the semiconductor top layer and can reduce the critical dimension of the isolation structure.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and particularly to a method for isolating an active area (AA) of a Semiconductor On Insulator (SOI). Background Art

[0002] With the continuous and rapid development of integrated circuits, the critical dimensions of devices in the circuit continue to shrink, and the thickness of the thin films corresponding to the components also continues to decrease. Fully Depleted SOI (FDSOI) has become an option to overcome the short-channel effect. In the FDSOI process, the substrate structure includes a semiconductor body layer, a buried dielectric layer, and a semiconductor top layer. The buried dielectric layer is formed on the surface of the semiconductor body layer, and the semiconductor top layer is formed on the surface of the buried dielectric layer; generally, the materials of the semiconductor body layer and the semiconductor top layer are Si. The semiconductor top layer is usually referred to as the SOI layer. The semiconductor top layer has an ultra-thin structure. By using the ultra-thin semiconductor top layer to form semiconductor devices, ultra-thin transistors can be obtained. The channel region composed of the semiconductor top layer at the bottom of the gate structure of the ultra-thin transistor will be completely depleted during device operation, which can eliminate the floating body effect, thereby well controlling the short-channel effect of the transistor, and then reducing the supply voltage.

[0003] In the FDSOI process, in addition to forming ultra-thin transistors such as CMOS devices in the semiconductor top layer, sometimes it is also necessary to form passive devices and pickup structures that are in contact with the bottom semiconductor body layer. To form these passive devices and pickup structures in contact with the bottom semiconductor body layer, it is necessary to form semiconductor epitaxial silicon in the FDSOI that is directly in contact with the bottom semiconductor body layer and whose top surface is flush with the top surface of the semiconductor top layer. This requires separately defining a Hybrid region to form the semiconductor epitaxial layer in direct contact with the semiconductor body layer.

[0004] As Figures 1A to 1B shown, it is a schematic diagram of the device structure in each step of the existing method for isolating the active area of FDSOI; the existing method for isolating the active area of FDSOI is similar to the formation method of shallow trench isolation, and includes the following steps:

[0005] Step 1: As Figure 1A shown, provide an SOI substrate structure. The SOI substrate includes a semiconductor body layer 101, a buried dielectric layer 102, and a semiconductor top layer 103. The buried dielectric layer 102 is formed on the surface of the semiconductor body layer 101, and the semiconductor top layer 103 is formed on the surface of the buried dielectric layer 102.

[0006] The SOI substrate has completed a Hybrid Loop, and the Hybrid Loop forms an epitaxial layer 106 in the hybrid region corresponding to the brace 104. The epitaxial layer 106 is in direct contact with the semiconductor body layer 101 at the bottom.

[0007] The hybrid region 104 is also the region to the right of the dashed line BB, and the region to the left of the dashed line BB is the SOI region 105.

[0008] The SOI region 105 is used to form semiconductor devices such as NMOS and PMOS. Figure 1A shows an NMOS and a PMOS. The NMOS is located to the left of the dashed line AA, and the PMOS is located between the dashed lines AA and BB. Generally, an isolation structure needs to be formed between the NMOS, the PMOS, and the hybrid region 104.

[0009] Step 2: Form a hard mask layer composed of a stacked oxidation layer 107 and a nitride layer 108, and coat photoresist 109.

[0010] Step 3: As shown in Figure 1B , perform exposure and development to form a pattern of the photoresist 109.

[0011] Step 4: As shown in Figure 1B , sequentially etch the nitride layer 108, the oxidation layer 107, the semiconductor top layer 103, the dielectric buried layer 102, and the semiconductor body layer 101 to form trenches 110. The semiconductor top layer 103 between the trenches 110 is the active region.

[0012] After that, a semiconductor device structure will be formed in the active region.

[0013] As shown in Figure 2 , is a top view of a semiconductor device formed by using the Figure 1B formed isolation structure; Figure 2 shows two adjacent semiconductor devices 112a and 112b. The semiconductor devices 112a and 112b respectively include corresponding gate structures 111 and source and drain regions formed on both sides of the gate structure 111. The isolation structure between the semiconductor devices 112a and 112b is formed in the trenches 110. The width of the isolation structure is the width d101 of the trenches 110. The width d101 is defined by the lithography process and is affected by both the lithography accuracy and the etching process, such that the minimum width d101 of the isolation structure formed by the existing method can only reach about 60 nm. Summary of the Invention

[0014] The technical problem to be solved by the present invention is to provide an isolation method for the active region of an SOI, which can achieve ultra-small gap cutting of the semiconductor top layer, thereby reducing the critical dimension of the isolation structure of the active region, saving the effective utilization area of the SOI, increasing the density of semiconductor devices, and reducing the chip manufacturing cost.

[0015] To solve the above technical problem, the isolation method for the active region of the SOI provided by the present invention includes the following steps:

[0016] Step 1: Provide an SOI substrate structure. The SOI substrate includes a semiconductor body layer, a buried dielectric layer, and a semiconductor top layer. The buried dielectric layer is formed on the surface of the semiconductor body layer, and the semiconductor top layer is formed on the surface of the buried dielectric layer; a hard mask layer is formed on the surface of the semiconductor top layer.

[0017] Step 2: Pattern etch the hard mask layer to form a first opening, and the first opening exposes the surface of the semiconductor top layer.

[0018] Step 3: Perform selective epitaxial growth to form a first epitaxial layer on the surface of the semiconductor top layer exposed by the first opening. The first epitaxial layer grows from the surface of the semiconductor top layer from bottom to top, and the first epitaxial layer does not grow on the side surface of the first opening. After the first epitaxial layer is formed, a first notch will be formed at the side surface of the first opening.

[0019] Step 4: Perform an oxidation process to oxidize the entire first epitaxial layer and also oxidize the semiconductor top layer at the bottom of the first notch, and finally form a first oxide layer. The first oxide layer will penetrate through the semiconductor top layer at the bottom of the first notch.

[0020] Step 5: Remove the hard mask layer and the first oxide layer to expose the top surface of the semiconductor top layer and form an isolation groove at the position where the first oxide layer penetrates through the semiconductor top layer. The semiconductor top layer between the isolation grooves serves as the active region.

[0021] A further improvement is that the SOI substrate is an FDSOI substrate. When the semiconductor device formed in the semiconductor top layer operates, the entire thickness of the semiconductor top layer at the bottom of the gate structure will be completely depleted.

[0022] A further improvement is that the material of the semiconductor body layer includes silicon or germanium.

[0023] A further improvement is that the material of the buried dielectric layer includes silicon oxide and high-k materials.

[0024] A further improvement is that the material of the semiconductor top layer includes silicon or germanium.

[0025] A further improvement is that the thickness of the top semiconductor layer reaches 5 nm to 20 nm.

[0026] A further improvement is that the hard mask layer is formed by stacking a second oxide layer and a third nitride layer.

[0027] A further improvement is that the thickness of the second oxide layer is The thickness of the third nitride layer is

[0028] A further improvement is that in step one, the second oxide layer is formed by using a diffusion (DIFF) process or a chemical vapor deposition (CVD) process.

[0029] The third nitride layer is HCD silicon nitride formed by using a diffusion process.

[0030] A further improvement is that the patterning etching process in step two includes the following sub-steps:

[0031] Step 21: Perform a photolithography process to define the formation region of the first opening;

[0032] Step 22: Etch the hard mask layer according to the photolithography definition to form the first opening.

[0033] A further improvement is that the etching process in step 22 includes:

[0034] Perform a dry etching and stop on the second oxide layer;

[0035] Perform a wet etching to remove the second oxide layer.

[0036] Alternatively, the etching process in step 22 includes: performing a dry etching with the top semiconductor layer as the stop layer to remove both the third nitride layer and the second oxide layer.

[0037] A further improvement is that the material of the first epitaxial layer includes silicon or germanium.

[0038] A further improvement is that the thickness of the first epitaxial layer is

[0039] A further improvement is that the oxidation process in step four uses a rapid thermal oxidation process.

[0040] A further improvement is that the oxidation process in step four includes the following sub-steps:

[0041] Perform a thermal oxidation at a temperature of 1050 °C to 1100 °C and a time of 180 s to 240 s;

[0042] Perform thermal annealing at a temperature of 1050°C to 1100°C and a time of 60 s to 120 s.

[0043] A further improvement is that the critical dimension of the isolation groove formed in step five is less than twice the thickness of the semiconductor top layer.

[0044] A further improvement is that the SOI substrate provided in step one further includes a mixing region, in which the semiconductor top layer and the buried dielectric layer are removed and a second epitaxial layer is formed, and the top surface of the second epitaxial layer is flush with the top surface of the semiconductor top layer in the SOI region outside the mixing region.

[0045] Different from the prior art in which the formation region of the isolation structure for defining the active region needs to be defined by lithography, and then the isolation structure is formed through trench etching and trench filling processes, the present invention utilizes the characteristics that during the selective epitaxial growth of the first epitaxial layer in the first opening, the first epitaxial layer only grows on the surface of the semiconductor top layer exposed at the bottom of the first opening and does not grow on the side surface of the first opening. Finally, the first epitaxial layer has a thick middle and thin ends. The thin ends mean that the thickness of the first epitaxial layer at the side surface of the first opening gradually thins from the middle to the edge, so that a first notch is automatically formed at the side surface of the first opening; then an oxidation process is performed to completely oxidize the first epitaxial layer. Since the thickness of the first epitaxial layer at the bottom of the first notch is thinned, under the condition that the first epitaxial layer in the middle region is completely oxidized, the semiconductor top layer at the bottom of the first epitaxial layer at the first notch will also be oxidized and the first oxide layer will penetrate through the semiconductor top layer. After that, removing the first oxide layer can form an isolation groove passing through the semiconductor top layer, that is, the isolation groove will cut off the semiconductor top layer, so that the active region can be isolated. Since the isolation groove of the present invention is formed through the epitaxial growth process, oxidation process and removal process of the first oxide layer of the first epitaxial layer in the first opening, and these processes do not require lithography definition, the size of the isolation groove is not limited by the lithography process. Finally, ultra-small gap cutting of the semiconductor top layer can be achieved, so that the critical dimension of the isolation structure of the active region can be reduced, the effective utilization area of the SOI can be saved, the density of semiconductor devices can be increased, and the chip manufacturing cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The present invention will be further described in detail below with reference to the drawings and specific embodiments:

[0047] Figures 1A - 1B are schematic diagrams of device structures in each step of the prior art method for isolating the active region of FDSOI;

[0048] Figure 2 is the Figure 1B top view of a semiconductor device formed by the isolation structure formed.

[0049] Figure 3 is a flowchart of the isolation method for the active region of the SOI in the embodiment of the present invention;

[0050] Figures 4A - 4G is a schematic diagram of the device structure in each step of the isolation method for the active region of the FDSOI in the embodiment of the present invention;

[0051] Figure 5 is adopted Figure 4G is a top view of a semiconductor device formed by the formed isolation structure. Detailed implementation manners

[0052] As Figure 3 shown, it is a flowchart of the isolation method for the active region of the SOI in the embodiment of the present invention; as Figures 4A to 4G shown, it is a schematic diagram of the device structure in each step of the isolation method for the active region of the FDSOI in the embodiment of the present invention; the isolation method for the active region of the SOI in the embodiment of the present invention includes the following steps:

[0053] Step 1, as Figure 4A shown, provide an SOI substrate structure, the SOI substrate includes a semiconductor body layer 201, a dielectric buried layer 202 and a semiconductor top layer 203, the dielectric buried layer 202 is formed on the surface of the semiconductor body layer 201, and the semiconductor top layer 203 is formed on the surface of the dielectric buried layer 202.

[0054] In the embodiment of the present invention, the SOI substrate is an FDSOI substrate. When the semiconductor device formed in the semiconductor top layer 203 works, the entire thickness of the semiconductor top layer 203 at the bottom of the gate structure will be completely depleted.

[0055] The material of the semiconductor body layer 201 includes silicon or germanium.

[0056] The material of the dielectric buried layer 202 includes silicon oxide and high-k materials.

[0057] The material of the semiconductor top layer 203 includes silicon or germanium. The thickness of the semiconductor top layer 203 reaches 5 nm to 20 nm.

[0058] The SOI substrate further includes a mixed region, Figure 4A the mixed region is not shown in, only the SOI region located outside the mixed region is shown. In the mixed region, the semiconductor top layer 203 and the dielectric buried layer 202 are removed and a second epitaxial layer is formed, and the top surface of the second epitaxial layer is flush with the top surface of the semiconductor top layer 203 in the SOI region outside the mixed region.

[0059] As Figure 4BAs shown, a hard mask layer 204 is formed on the surface of the semiconductor top layer 203.

[0060] In an embodiment of the present invention, the hard mask layer 204 is formed by stacking a second oxide layer and a third nitride layer.

[0061] The thickness of the second oxide layer is The thickness of the third nitride layer is

[0062] The second oxide layer is formed by a diffusion process or a chemical vapor deposition process.

[0063] The third nitride layer is HCD silicon nitride formed by a diffusion process. HCD represents hexachloroethyldisilane, and HCD silicon nitride represents silicon nitride formed using HCD as the silicon source. The N source is usually ammonia.

[0064] Step Two: As Figure 4D shown, the hard mask layer 204 is patterned and etched to form a first opening, and the first opening exposes the surface of the semiconductor top layer 203.

[0065] In an embodiment of the present invention, the patterning and etching process in Step Two includes the following sub-steps:

[0066] Step 21: As Figure 4C shown, a photolithography process is performed to form a graphic structure of a photoresist 205, and the graphic structure of the photoresist 205 defines the formation area of the first opening. Figure 4C Only the graphic structure of the photoresist 205 near one side of the first opening is shown in

[0067] Step 22: As Figure 4D shown, the hard mask layer 204 is etched according to the photolithography definition to form the first opening.

[0068] The etching process in Step 22 includes: performing dry etching and stopping on the second oxide layer; performing wet etching to remove the second oxide layer. Alternatively, the etching process in Step 22 includes: performing dry etching with the semiconductor top layer 203 as the stopping layer to remove both the third nitride layer and the second oxide layer.

[0069] Step Three: As Figure 4E shown, selective epitaxial growth is performed to form a first epitaxial layer 206 on the surface of the semiconductor top layer 203 exposed by the first opening. The first epitaxial layer 206 grows from the surface of the semiconductor top layer 203 from bottom to top, and the first epitaxial layer 206 does not grow on the side surface of the first opening. After the first epitaxial layer 206 is formed, a first notch 207 is formed at the side surface of the first opening.

[0070] In an embodiment of the present invention, the material of the first epitaxial layer 206 includes silicon or germanium.

[0071] The thickness of the first epitaxial layer 206 is

[0072] Step Four: As Figure 4F shown, perform an oxidation process to oxidize the entire first epitaxial layer 206 and also oxidize the semiconductor top layer 203 at the bottom of the first notch 207, and finally form a first oxide layer 208. At the bottom of the first notch 207, the first oxide layer 208 will penetrate through the semiconductor top layer 203, and the area where the first oxide layer 208 penetrates through the semiconductor top layer 203 is the isolation groove 209.

[0073] In an embodiment of the present invention, the oxidation process adopts a rapid thermal oxidation process.

[0074] The oxidation process in Step Four includes the following sub-steps:

[0075] Perform thermal oxidation at a temperature of 1050 °C to 1100 °C and a time of 180 s to 240 s;

[0076] Perform thermal annealing at a temperature of 1050 °C to 1100 °C and a time of 60 s to 120 s.

[0077] The specific amount of oxidant, reaction temperature, and time can be obtained according to requirements and through a Design Of Experiment (DOE).

[0078] Step Five: As Figure 4G shown, remove the hard mask layer 204 and the first oxide layer 208 to expose the top surface of the semiconductor top layer 203 and form an isolation groove 209 at the position where the first oxide layer 208 penetrates through the semiconductor top layer 203. The semiconductor top layer 203 between the isolation grooves 209 serves as the active region.

[0079] In an embodiment of the present invention, the critical dimension of the isolation groove 209 formed in Step Five is less than 2 times the thickness of the semiconductor top layer 203.

[0080] After that, semiconductor devices such as NMOS and PMOS can be formed in the active region.

[0081] As Figure 5 shown, it is a top view of a semiconductor device formed by using the isolation structure formed Figure 4G ; Figure 5Two adjacent semiconductor devices 210a and 210b are shown, and the semiconductor devices 210a and 210b respectively include corresponding gate structures 211 and source and drain regions formed on both sides of the gate structures 211. The isolation structure between the semiconductor devices 210a and 210b is formed in the isolation groove 209, and the width of the isolation structure is the width d201 of the isolation groove 209. And Figure 2 different from the width d101 of the existing method in [reference] which is defined by a lithography process, the width d201 formed in the embodiments of the present invention is determined by an epitaxial growth process and an oxidation process, and through process adjustment, the width d201 can be controlled below 20 nm.

[0082] Different from the prior art in which it is necessary to define the formation region of the isolation structure of the active region by lithography and then form the isolation structure through trench etching and trench filling processes, in the embodiments of the present invention, during the process of selectively epitaxially growing the first epitaxial layer 206 in the first opening, the first epitaxial layer 206 only grows on the surface of the semiconductor top layer 203 exposed at the bottom of the first opening and does not grow on the side surfaces of the first opening. Finally, the first epitaxial layer 206 has the characteristics of being thick in the middle and thin at both ends. The thinness at both ends means that the thickness of the first epitaxial layer 206 at the side surfaces of the first opening gradually thins from the middle to the edge, so that a first notch 207 is automatically formed at the side surfaces of the first opening; then an oxidation process is performed to completely oxidize the first epitaxial layer 206. Since the thickness of the first epitaxial layer 206 at the bottom of the first notch 207 is thinned, under the condition that the first epitaxial layer 206 in the middle region is completely oxidized, the semiconductor top layer 203 at the bottom of the first epitaxial layer 206 at the first notch 207 will also be oxidized and the first oxide layer 208 will penetrate through the semiconductor top layer 203. After that, removing the first oxide layer 208 can form the isolation groove 209 passing through the semiconductor top layer 203, that is, the isolation groove 209 will cut off the semiconductor top layer 203, so that the active region can be isolated. Since the isolation groove 209 in the embodiments of the present invention is formed through the epitaxial growth process, oxidation process and removal process of the first oxide layer 208 of the first epitaxial layer 206 in the first opening, and these processes do not require lithography definition, the size of the isolation groove 209 is not limited by the lithography process. Finally, ultra-small gap cutting of the semiconductor top layer 203 can be realized, so that the critical dimension of the isolation structure of the active region can be reduced, the effective utilization area of the SOI can be saved, the density of the semiconductor device can be increased, and the chip manufacturing cost can be reduced.

[0083] The present invention has been described in detail through specific embodiments above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many deformations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A method for isolating an active region of an SOI, characterized in that, it includes the following steps: Step 1: Provide an SOI substrate structure, the SOI substrate includes a semiconductor body layer, a buried dielectric layer, and a semiconductor top layer, the buried dielectric layer is formed on the surface of the semiconductor body layer, and the semiconductor top layer is formed on the surface of the buried dielectric layer; Form a hard mask layer on the surface of the semiconductor top layer; Step 2: Pattern etch the hard mask layer to form a first opening, and the first opening exposes the surface of the semiconductor top layer; Step 3: Perform selective epitaxial growth to form a first epitaxial layer on the surface of the semiconductor top layer exposed by the first opening. The first epitaxial layer grows from the surface of the semiconductor top layer from bottom to top, and the first epitaxial layer does not grow on the side surface of the first opening. After the first epitaxial layer is formed, a first notch will be formed at the side surface of the first opening; Step 4: Perform an oxidation process to oxidize the entire first epitaxial layer and also oxidize the semiconductor top layer at the bottom of the first notch and finally form a first oxide layer. At the bottom of the first notch, the first oxide layer will penetrate through the semiconductor top layer; Step 5: Remove the hard mask layer and the first oxide layer to expose the top surface of the semiconductor top layer and form isolation grooves at the positions where the first oxide layer penetrates through the semiconductor top layer. The semiconductor top layer between the isolation grooves serves as the active region.

2. The method for isolating an active region of an SOI according to claim 1, characterized in that: The SOI substrate is an FDSOI substrate. When the semiconductor device formed in the semiconductor top layer operates, the entire thickness of the semiconductor top layer at the bottom of the gate structure will be completely depleted.

3. The method for isolating an active region of an SOI according to claim 1 or 2, characterized in that: The material of the semiconductor body layer includes silicon or germanium.

4. The method for isolating an active region of an SOI according to claim 1 or 2, characterized in that: The material of the buried dielectric layer includes silicon oxide, high-k dielectric materials.

5. The method for isolating an active region of an SOI according to claim 1 or 2, characterized in that: The material of the semiconductor top layer includes silicon or germanium.

6. The method for isolating an active region of an SOI according to claim 2, characterized in that: The thickness of the semiconductor top layer reaches 5nm - 20nm.

7. The method for isolating an active region of an SOI according to claim 2, characterized in that: The hard mask layer is formed by stacking a second oxide layer and a third nitride layer.

8. The method for isolating an active region of an SOI according to claim 7, characterized in that: The thickness of the second oxide layer is The thickness of the third nitride layer is 9. The method for isolating an active region of an SOI according to claim 7, characterized in that: In step 1, the second oxide layer is formed by using a diffusion process or a chemical vapor deposition process; The third nitride layer is HCD silicon nitride formed by using a diffusion process and using HCD as the silicon source, and HCD represents hexachloroethylsilane.

10. The method for isolating an active region of an SOI according to claim 7, characterized in that: The patterning etch process in step 2 includes the following sub-steps: Step 21: Define the formation region of the first opening through a lithography process; Step 22: Etch the hard mask layer according to the lithography definition to form the first opening.

11. The isolation method for the active region of SOI as claimed in claim 10, characterized in that: The etching process in Step 22 includes: Performing dry etching and stopping on the second oxide layer; Performing wet etching to remove the second oxide layer; Or, the etching process in Step 22 includes: performing dry etching with the semiconductor top layer as the stopping layer to remove both the third nitride layer and the second oxide layer.

12. The isolation method for the active region of SOI as claimed in claim 2, characterized in that: The material of the first epitaxial layer includes silicon or germanium.

13. The isolation method for the active region of SOI as claimed in claim 12, characterized in that: The thickness of the first epitaxial layer is 14. The isolation method for the active region of SOI as claimed in claim 12, characterized in that: The oxidation process in Step Four adopts a rapid thermal oxidation process.

15. The isolation method for the active region of SOI as claimed in claim 14, characterized in that: The oxidation process in Step Four includes the following sub-steps: Performing thermal oxidation at a temperature of 1050°C to 1100°C and a time of 180 s to 240 s; Performing thermal annealing at a temperature of 1050°C to 1100°C and a time of 60 s to 120 s.

16. The isolation method for the active region of SOI as claimed in claim 2, characterized in that: The critical dimension of the isolation groove formed in Step Five is less than twice the thickness of the semiconductor top layer.

17. The isolation method for the active region of SOI as claimed in claim 2, characterized in that: The SOI substrate provided in Step One further includes a mixed region, in which the semiconductor top layer and the dielectric buried layer are removed and a second epitaxial layer is formed, and the top surface of the second epitaxial layer is flush with the top surface of the semiconductor top layer in the SOI region outside the mixed region.

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