Semiconductor process and semiconductor structure

Abstract

The present application provides a semiconductor process and a semiconductor structure, the semiconductor process comprising: providing a first substrate and a second substrate, the first substrate comprising a first substrate, a trap-rich layer and a dense layer stacked in sequence, and the second substrate comprising a second substrate and an active layer stacked in sequence; forming a dielectric layer on the exposed surface of the first substrate to form a first bonding substrate, and / or forming a dielectric layer on the exposed surface of the second substrate to form a second bonding substrate; using the dielectric layer as a bonding interface, bonding one of the following: the first substrate and the second bonding substrate, the first bonding substrate and the second substrate, the first bonding substrate and the second bonding substrate to obtain a bonding structure; removing the second substrate of the bonding structure to expose the active layer. The present application can obtain a trap-rich layer with a relatively flat surface by forming a dense layer on the trap-rich layer.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular, to a semiconductor process and a semiconductor structure. Background Art

[0002] With the continuous development of microelectronics technology, the requirements for materials in the research and development of high-performance and integrated multifunctional ICs (Integrated Circuit Chips) are getting higher and higher. Silicon-on-Insulator SOI (Silicon-on-Insulator) material is a new type of integrated circuit material, which is praised by many scholars as "a new silicon-based integrated circuit technology in the 21st century". Compared with bulk silicon, SOI has the advantages of no latch-up, high speed, low voltage, low power consumption and radiation resistance. In addition, the requirements for high integration have led to the continuous reduction in the size of metal oxide semiconductor field effect transistors MOSFET, and the corresponding gate oxide thickness has also been continuously reduced.

[0003] In the prior art, in the process of manufacturing HR (High Resistivity) SOI, in order to alleviate the problems of surface roughness and charge capture uniformity caused by recrystallization, a sufficiently thick polysilicon layer is set on the HR silicon substrate, and then a certain thickness of polysilicon is removed through a planarization step, so that the thickness of the removed polysilicon layer reaches a predetermined thickness. This increases the process complexity of HR SOI.

[0004] Therefore, a method is urgently needed to simplify the manufacturing process of HR SOI in the prior art.

[0005] The above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain certain information that does not form the prior art known in this country for those skilled in the art. Summary of the invention

[0006] The main purpose of the present application is to provide a semiconductor process and a semiconductor structure to solve the problem that the manufacturing process of HR SOI in the prior art is relatively complicated.

[0007] According to one aspect of an embodiment of the present invention, a semiconductor process is provided, including: providing a first substrate and a second substrate, the first substrate including a first substrate, a trap-rich layer and a dense layer stacked in sequence, and the second substrate including a second substrate and an active layer stacked in sequence; forming a dielectric layer on an exposed surface of the first substrate to form a first bonding substrate, and / or forming the dielectric layer on an exposed surface of the second substrate to form a second bonding substrate; using the dielectric layer as a bonding interface, bonding one of the following: the first substrate and the second bonding substrate, the first bonding substrate and the second substrate, and the first bonding substrate and the second bonding substrate to obtain a bonding structure; removing the second substrate of the bonding structure to expose the active layer.

[0008] Optionally, providing the first base includes: providing the first substrate; introducing a predetermined gas into a reaction chamber where the first substrate is located to form the trap-rich layer on the exposed surface of the first substrate, the predetermined gas including at least one of silane, disilane, trisilane, methane and methylsilane; depositing a dense material on the exposed surface of the trap-rich layer in a temperature range of 300°C to 1000°C to form the dense layer.

[0009] Optionally, providing the second substrate includes: providing a second preliminary substrate, the second preliminary substrate including a second substrate and a preliminary active layer stacked in sequence; forming a radio frequency component in the preliminary active layer, or forming the radio frequency component on an exposed surface of the preliminary active layer, to obtain the active layer.

[0010] Optionally, providing the second preliminary base comprises: providing a second preliminary substrate; forming an ion layer in the second preliminary substrate, wherein the ion layer separates the second preliminary substrate into the second substrate and the preliminary active layer along a predetermined direction, wherein the predetermined direction is perpendicular to the thickness direction of the second preliminary substrate; and removing the second substrate of the bonding structure comprises: performing heat treatment on the bonding structure so that the bonding structure is broken along the ion layer to remove the second substrate.

[0011] Optionally, after providing the first substrate and the second substrate, a dielectric layer is formed on the exposed surface of the first substrate, and before forming the first bonding substrate, the semiconductor process also includes: annealing the first substrate; removing the dense layer, forming a dielectric layer on the exposed surface of the first substrate, and forming the first bonding substrate, including: forming the dielectric layer on the exposed surface of the trap-rich layer to form the first bonding substrate.

[0012] Optionally, performing annealing treatment on the first substrate includes: annealing the first substrate at a temperature range of 500° C. to 1500° C.

[0013] Optionally, the material of the trap-rich layer includes amorphous silicon or polycrystalline silicon, and the material of the dense layer includes at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0014] Optionally, a material of the first substrate includes at least one of silicon carbide, germanium, and single crystal silicon with a resistivity greater than 100 ohm·cm.

[0015] Optionally, the thickness of the trap-rich layer is 100 nm to 2000 nm, the thickness of the dielectric layer is 0.1 nm to 20 nm, and the thickness of the dense layer is 5 nm to 200 nm.

[0016] According to another aspect of an embodiment of the present invention, a semiconductor structure is further provided. The semiconductor structure is manufactured by using any one of the semiconductor processes described above.

[0017] According to an embodiment of the present invention, in the semiconductor process, the second substrate includes a second substrate and an active layer stacked in sequence, and the first substrate includes a first substrate, a trap-rich layer and a dense layer stacked in sequence, and the dense layer can suppress the deformation of the surface of the trap-rich layer due to recrystallization during the high temperature process, and ensure that the surface of the trap-rich layer away from the first substrate is relatively flat and has a low surface roughness; then, a dielectric layer is formed on the first substrate and / or on the second substrate, and the two substrates formed with the dielectric layer are bonded to obtain a bonding structure, which includes three situations, namely, the first situation, the dielectric layer is formed on the first substrate to form a first bonding substrate, and the first bonding substrate and the second substrate are bonded; the second situation, the dielectric layer is formed on the second substrate to form a second bonding substrate, and the first substrate and the second bonding substrate are bonded; the third situation, the dielectric layers are formed on the first substrate and the second substrate respectively, to form a first bonding substrate and a second bonding substrate, and the first bonding substrate and the second bonding substrate are bonded; finally, the second substrate in the bonding structure is removed to expose the active layer. Compared with the prior art, in which a thicker polysilicon layer is formed on the first substrate and then the polysilicon layer is flattened to obtain a trap-rich layer, which results in a more complicated manufacturing process, the semiconductor process of the present application forms a dense layer on the trap-rich layer to obtain a trap-rich layer with a relatively flat surface, thus ensuring a relatively simple manufacturing process and a low process cost. In addition, the thickness of the trap-rich layer of the present application is relatively small, which ensures that its charge capture capability is relatively strong and the performance of the obtained semiconductor structure is relatively good. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 A schematic diagram of a semiconductor process generation process according to an embodiment of the present application is shown;

[0020] Figures 2 to 5 A schematic diagram of a structure formed after different process steps of a semiconductor process according to the present application is shown;

[0021] Figure 6 A schematic diagram of a semiconductor structure according to an embodiment of the present application is shown.

[0022] The above drawings include the following reference numerals:

[0023] 100, first substrate; 101, trap-rich layer; 102, dense layer; 200, second substrate; 201, active layer; 202, ion layer; 300, dielectric layer. DETAILED DESCRIPTION

[0024] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0025] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0026] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0027] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0030] As mentioned in the background technology, the manufacturing process of HR SOI in the prior art is relatively complicated. In order to solve the above problems, in a typical implementation of the present application, a semiconductor process and a semiconductor structure are provided.

[0031] According to an embodiment of the present application, a semiconductor process is provided.

[0032] Figure 1 1 is a flow chart of a semiconductor process according to an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0033] Step S101, providing a first substrate and a second substrate, such as Figure 2 As shown, the first substrate comprises a first substrate 100, a trap-rich layer 101 and a dense layer 102 stacked in sequence, as shown in FIG. Figure 4 As shown, the second base comprises a second substrate 200 and an active layer 201 which are stacked in sequence;

[0034] Step S102, forming a dielectric layer on the exposed surface of the first substrate to form a first bonding substrate, and / or, as Figure 4 As shown, the dielectric layer 300 is formed on the exposed surface of the second substrate to form a second bonding substrate;

[0035] Step S103, using the dielectric layer 300 as a bonding interface, bonding one of the following: the first substrate and the second bonding substrate, the first bonding substrate and the second substrate, or the first bonding substrate and the second bonding substrate, to obtain Figure 5 The bonding structure shown;

[0036] Step S104, removing the second substrate 200 of the bonding structure to expose the active layer 201, and obtaining Figure 6 The structure shown.

[0037] In the above semiconductor process, the second substrate includes a second substrate and an active layer stacked in sequence, and the first substrate includes a first substrate, a trap-rich layer and a dense layer stacked in sequence, and the dense layer can suppress the deformation of the surface of the trap-rich layer due to recrystallization during the high temperature process, and ensure that the surface of the trap-rich layer away from the first substrate is relatively flat and has a low surface roughness; then, a dielectric layer is formed on the first substrate and / or on the second substrate, and the two substrates formed with the dielectric layer are bonded to obtain a bonding structure, which includes three situations. The first one is: The dielectric layer is formed on the first substrate to form a first bonding substrate, and the first bonding substrate and the second substrate are bonded; the second is to form a dielectric layer on the second substrate to form a second bonding substrate, and the first substrate and the second bonding substrate are bonded; the third is to form dielectric layers on the first substrate and the second substrate respectively to form a first bonding substrate and a second bonding substrate, and the first bonding substrate and the second bonding substrate are bonded; finally, the second substrate in the bonding structure is removed to expose the active layer. Compared with the problem of forming a thicker polysilicon layer on the first substrate and then flattening the polysilicon layer to obtain a trap-rich layer in the prior art, which causes a more complicated manufacturing process, the semiconductor process of the present application can obtain a trap-rich layer with a relatively flat surface by forming a dense layer on the trap-rich layer, which ensures that the manufacturing process is relatively simple and the process cost is relatively low. In addition, the thickness of the trap-rich layer of the present application is relatively small, which ensures that its charge capture ability is relatively strong and the performance of the obtained semiconductor structure is relatively good.

[0038] Specifically, the dense layer is a functional layer made of a material with high density.

[0039] According to a specific embodiment of the present application, the material of the above-mentioned trap-rich layer includes amorphous silicon or polycrystalline silicon. In a more specific embodiment, the material of the above-mentioned trap-rich layer is amorphous silicon or polycrystalline silicon. Providing the above-mentioned first base includes: providing the above-mentioned first substrate 100; introducing a predetermined gas into the reaction chamber where the above-mentioned first substrate 100 is located to form the above-mentioned trap-rich layer 101 on the exposed surface of the above-mentioned first substrate 100, and the above-mentioned predetermined gas includes at least one of silane, disilane, trisilane, methane and methylsilane; depositing a dense material on the exposed surface of the above-mentioned trap-rich layer 101 in the temperature range of 300°C to 1000°C to form the above-mentioned dense layer 102, and obtaining the above-mentioned Figure 2The first substrate is shown in FIG. In this way, the first substrate can be obtained relatively simply and quickly.

[0040] In a specific embodiment, during the process of introducing the predetermined gas into the reaction chamber where the first substrate is located, the temperature of the reaction chamber is in the range of 500°C to 900°C.

[0041] In the actual application process, any feasible method in the prior art can be used to form the above-mentioned trap-rich layer and the above-mentioned dense layer. In another specific embodiment, the above-mentioned trap-rich layer is formed on the exposed surface of the above-mentioned first substrate by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The above-mentioned dense layer is deposited on the exposed surface of the above-mentioned trap-rich layer by low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition (HDPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

[0042] In actual application, the material of the dense layer can be any feasible material in the prior art. According to a specific embodiment of the present application, the material of the dense layer includes at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0043] In order to further ensure that the process of obtaining the above-mentioned second substrate is relatively simple, according to another specific embodiment of the present application, the above-mentioned second substrate is provided, including: providing a second preliminary substrate, the above-mentioned second preliminary substrate including a second substrate and a preliminary active layer stacked in sequence; forming a radio frequency component in the above-mentioned preliminary active layer, or forming the above-mentioned radio frequency component on the exposed surface of the above-mentioned preliminary active layer, to obtain the above-mentioned active layer.

[0044] The active layer may include semiconductor materials, dielectric materials, ferroelectric materials and / or substructures, and the active layer may include at least one cavity and at least one suspended element on the cavity.

[0045] According to a specific embodiment of the present application, after obtaining the above-mentioned bonding structure, the above-mentioned bonding structure can be heated to enhance the bonding strength. The heating temperature is generally 10° C. to 125° C., and the heating duration is 10s to 2h.

[0046] According to another specific embodiment of the present application, Figure 4 As shown, providing the above-mentioned second preliminary base includes: providing a second preliminary substrate; forming an ion layer 202 in the above-mentioned second preliminary substrate, the above-mentioned ion layer 202 divides the above-mentioned second preliminary substrate into the above-mentioned second substrate 200 and the above-mentioned preliminary active layer along a predetermined direction, and the above-mentioned predetermined direction is perpendicular to the thickness direction of the above-mentioned second preliminary substrate; removing the above-mentioned second substrate of the above-mentioned bonding structure includes: performing heat treatment on the above-mentioned bonding structure so that the above-mentioned bonding structure is broken along the above-mentioned ion layer to remove the above-mentioned second substrate.

[0047] Specifically, an ion layer may be formed in the second preliminary substrate by implanting substances into the second preliminary substrate.

[0048] Of course, removing the second substrate of the bonding structure is not limited to the above method, and those skilled in the art may use any feasible method in the prior art to remove the second substrate. In another specific embodiment of the present application, removing the second substrate of the bonding structure to expose the active layer comprises: etching the bonding structure to remove the second substrate to expose the active layer. In another specific embodiment, removing the second substrate of the bonding structure to expose the active layer comprises: chemically mechanically polishing the bonding structure to remove the second substrate to expose the active layer.

[0049] According to another specific embodiment of the present application, after providing the first substrate and the second substrate, a dielectric layer is formed on the exposed surface of the first substrate, and before forming the first bonding substrate, the semiconductor process further includes: annealing the first substrate; removing the dense layer 102 to obtain Figure 3 The structure shown in FIG. 1 forms a dielectric layer on the exposed surface of the first substrate to form a first bonding substrate, including: forming the dielectric layer on the exposed surface of the trap-rich layer to form the first bonding substrate.

[0050] In the actual application process, the dielectric layer is formed on the exposed surface of the first substrate, including: oxidizing the first substrate to form the dielectric layer, that is, oxidizing the trap-rich layer to form the dielectric layer. Of course, chemical deposition can also be used to form the dielectric layer on the exposed surface of the first substrate. When the dielectric layers are formed on the exposed surface of the first substrate and the exposed surface of the second substrate, the first bonding substrate and the second bonding substrate are obtained respectively, and the first bonding substrate and the second bonding substrate are bonded to obtain the bonding structure, the two dielectric layers in the bonding structure form a buried dielectric layer.

[0051] In a specific embodiment, annealing the first substrate includes annealing the first substrate at a temperature range of 500°C to 1500°C. The annealing may be performed by furnace annealing or rapid annealing. Removing the dense layer includes etching the annealed first substrate to remove the dense layer 102, and obtaining Figure 3 The structure shown in FIG. 1 is a block diagram of a structure of a substrate. The etching method may be dry etching or wet etching.

[0052] It should be noted that each step in the above-mentioned implementation method of forming the first substrate and the second substrate can be implemented in a feasible manner in the prior art. The substrate in the above-mentioned substrate can be selected according to the actual needs of the device, and may include a silicon substrate, a germanium substrate, or a silicon germanium substrate. In other embodiments, the above-mentioned substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a bulk substrate made of a material, or a composite material substrate made of a stack of different materials, and at least one single crystal material is located at the main surface of the substrate. Of course, it can also be other substrates feasible in the prior art. In a specific embodiment, the material of the above-mentioned first substrate includes at least one of silicon carbide, germanium, and single crystal silicon with a resistivity greater than 100 ohm·cm.

[0053] In order to ensure that the insertion loss and harmonic distortion required by the radio frequency switch in the obtained semiconductor structure are small and the isolation performance is good, the material of the first substrate includes single crystal silicon with a resistivity greater than 100 ohm·cm.

[0054] In the actual application process, in order to obtain a semiconductor structure with better performance by the semiconductor process, the thickness of the trap-rich layer is 100nm to 2000nm, the thickness of the dielectric layer is 0.1nm to 20nm, and the thickness of the dense layer is 5nm to 200nm. Of course, the thickness of the trap-rich layer, the dielectric layer and the dense layer is not limited to the above thickness range, and those skilled in the art can determine the thickness of the trap-rich layer, the dielectric layer and the dense layer according to actual conditions. In another specific embodiment, the thickness of the trap-rich layer can also be 10nm to 500nm. In this way, the trap-rich layer can more efficiently capture the charges present on the surface.

[0055] According to another aspect of an embodiment of the present invention, a semiconductor structure is further provided. The semiconductor structure is manufactured by using any of the above-mentioned semiconductor processes.

[0056] The above-mentioned semiconductor structure is manufactured by any of the above-mentioned semiconductor processes. Compared with the prior art in which a thicker polysilicon layer is formed on the first substrate and then the polysilicon layer is flattened to obtain a trap-rich layer, which causes a more complicated manufacturing process, the above-mentioned semiconductor process of the present application forms a dense layer on the trap-rich layer. The above-mentioned dense layer can suppress the deformation of the surface of the above-mentioned trap-rich layer due to recrystallization during the high temperature process, and ensure that the surface of the above-mentioned trap-rich layer away from the above-mentioned first substrate is relatively flat and has a lower surface roughness, thereby obtaining a trap-rich layer with a relatively flat surface, which ensures that the manufacturing process of the above-mentioned semiconductor structure is relatively simple and the process cost is relatively low. In addition, the thickness of the above-mentioned trap-rich layer of the present application is relatively small, which ensures that its charge capture ability is relatively strong and the performance of the obtained semiconductor structure is relatively good.

[0057] In a specific embodiment, the semiconductor structure is HR SOI.

[0058] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0059] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0060] 1) In the semiconductor process described above in the present application, the second substrate comprises a second substrate and an active layer stacked in sequence, and the first substrate comprises a first substrate, a trap-rich layer and a dense layer stacked in sequence, wherein the dense layer can suppress deformation of the surface of the trap-rich layer due to recrystallization during high temperature, and ensure that the surface of the trap-rich layer away from the first substrate is relatively flat and has a low surface roughness; then, a dielectric layer is formed on the first substrate and / or on the second substrate, and the two substrates formed with the dielectric layer are bonded to obtain a bonding structure, which includes three situations, the first One is to form the dielectric layer on the first substrate to form a first bonding substrate, and bond the first bonding substrate to the second substrate; the second is to form a dielectric layer on the second substrate to form a second bonding substrate, and bond the first substrate to the second bonding substrate; the third is to form dielectric layers on the first substrate and the second substrate respectively to form a first bonding substrate and a second bonding substrate, and bond the first bonding substrate to the second bonding substrate; finally, remove the second substrate in the bonding structure to expose the active layer. Compared with the problem of forming a thicker polysilicon layer on the first substrate and then flattening the polysilicon layer to obtain a trap-rich layer in the prior art, which causes a more complicated manufacturing process, the semiconductor process of the present application can obtain a trap-rich layer with a relatively flat surface by forming a dense layer on the trap-rich layer, which ensures that the manufacturing process is relatively simple and the process cost is relatively low. In addition, the thickness of the trap-rich layer of the present application is relatively small, which ensures that its charge capture ability is relatively strong and the performance of the obtained semiconductor structure is relatively good.

[0061] 2) The semiconductor structure mentioned above in the present application is manufactured by any of the above-mentioned semiconductor processes. Compared with the prior art in which a thicker polysilicon layer is formed on the first substrate and then the polysilicon layer is flattened to obtain a trap-rich layer, which causes a more complicated manufacturing process, the semiconductor process of the present application forms a dense layer on the trap-rich layer. The dense layer can suppress the deformation of the surface of the trap-rich layer due to recrystallization during the high temperature process, and ensure that the surface of the trap-rich layer away from the first substrate is relatively flat and has a lower surface roughness, thereby obtaining a trap-rich layer with a relatively flat surface, which ensures that the manufacturing process of the semiconductor structure is relatively simple and the process cost is relatively low. In addition, the thickness of the trap-rich layer of the present application is relatively small, which ensures that its charge capture ability is relatively strong and the performance of the obtained semiconductor structure is relatively good.

[0062] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor process, characterized in that: include: Providing a first substrate and a second substrate, wherein the first substrate comprises a first substrate, a trap-rich layer, and a dense layer stacked in sequence, and the second substrate comprises a second substrate and an active layer stacked in sequence; forming a dielectric layer on an exposed surface of the first substrate to form a first bonding substrate, and / or forming the dielectric layer on an exposed surface of the second substrate to form a second bonding substrate; Using the dielectric layer as a bonding interface, bonding one of the following: the first substrate and the second bonding substrate, the first bonding substrate and the second substrate, and the first bonding substrate and the second bonding substrate to obtain a bonding structure; removing the second substrate of the bonding structure so that the active layer is exposed, After providing the first substrate and the second substrate, forming a dielectric layer on the exposed surface of the first substrate and before forming the first bonding substrate, the semiconductor process further includes: performing annealing treatment on the first substrate; removing the dense layer, Forming a dielectric layer on the exposed surface of the first substrate to form a first bonding substrate, comprising: The dielectric layer is formed on the exposed surface of the trap-rich layer to form the first bonding substrate.

2. The semiconductor process according to claim 1, characterized in that: Providing the first substrate, including: providing the first substrate; Introducing a predetermined gas into a reaction chamber where the first substrate is located to form the trap-rich layer on the exposed surface of the first substrate, wherein the predetermined gas comprises at least one of silane, disilane, trisilane, methane and methylsilane; A dense material is deposited on the exposed surface of the trap-rich layer within a temperature range of 300° C. to 1000° C. to form the dense layer.

3. The semiconductor process according to claim 1, characterized in that: Providing the second substrate, comprising: Providing a second preliminary substrate, wherein the second preliminary substrate comprises a second substrate and a preliminary active layer stacked in sequence; A radio frequency component is formed in the prepared active layer, or the radio frequency component is formed on an exposed surface of the prepared active layer to obtain the active layer.

4. The semiconductor process according to claim 3, characterized in that: Providing the second prepared substrate includes: providing a second preliminary substrate; forming an ion layer in the second preliminary substrate, wherein the ion layer separates the second preliminary substrate into the second substrate and the preliminary active layer along a predetermined direction, wherein the predetermined direction is perpendicular to the thickness direction of the second preliminary substrate, and removing the second substrate of the bonding structure, comprising: The bonding structure is thermally treated so that the bonding structure is broken along the ion layer to remove the second substrate.

5. The semiconductor process according to claim 1, characterized in that: Annealing the first substrate comprises: The first substrate is annealed at a temperature ranging from 500° C. to 1500° C.

6. The semiconductor process according to any one of claims 1 to 4, characterized in that: The material of the trap-rich layer includes amorphous silicon or polycrystalline silicon, and the material of the dense layer includes at least one of silicon oxide, silicon nitride and silicon oxynitride.

7. The semiconductor process according to any one of claims 1 to 4, characterized in that: The material of the first substrate includes at least one of silicon carbide, germanium, and single crystal silicon with a resistivity greater than 100 ohm·cm.

8. The semiconductor process according to any one of claims 1 to 4, characterized in that The thickness of the trap-rich layer is 100 nm to 2000 nm, the thickness of the dielectric layer is 0.1 nm to 20 nm, and the thickness of the dense layer is 5 nm to 200 nm.

9. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by using the semiconductor process described in any one of claims 1 to 8.

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