Patterned material including carbon-containing layer and method for semiconductor device manufacturing

Abstract

The present disclosure relates to patterned materials including carbon-containing layers and methods for semiconductor device manufacturing. In one exemplary aspect, the present disclosure relates to a method for photolithographic patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterned layer is formed by depositing a first layer having an organic component having a composition including at least 50 atomic percent carbon, depositing a second layer including silicon, and depositing a photosensitive layer on the second layer. In some embodiments, the first layer is deposited by an ALD, CVD, or PVD process.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and more specifically, to patterned materials including carbon-containing layers and methods for semiconductor device manufacturing. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs with increasingly greater functionality and smaller geometry. In general, the minimum feature size, now commonly referred to as the critical dimension, is a measure of the smallest component (or line) that can be created using a manufacturing process. As component sizes shrink, the features of the ICs become increasingly smaller, and more and more components are packed into a given area. This scaling of the IC allows for the incorporation of more and more functionality into the same chip area, and thus allows for the creation of more and more powerful ICs.

[0003] As semiconductor manufacturing processes desire smaller process windows, the desired spacing (i.e., pitch) between elements of a device decreases and becomes increasingly difficult to achieve using traditional optical masks and lithography equipment. Advances in lithography tools can help meet the scaling requirements of smaller scale processes. For example, extreme ultraviolet (EUV) lithography and immersion lithography have been used to support the critical dimension (CD) requirements of smaller devices. In addition, patterning methods themselves have evolved to drive the formation of features of the desired CD below the capabilities of the lithography equipment itself. While lithography equipment and patterning advances are suitable in many respects, further advances are desired. SUMMARY

[0004] According to one embodiment of the present disclosure, a method for lithographic patterning is provided, comprising: providing a substrate; forming a target layer over the substrate; and forming a patterned layer, wherein forming the patterned layer comprises: depositing a first layer having a composition comprising at least 50 atomic percent carbon; depositing a second layer comprising silicon; and depositing a photoactive layer on the second layer.

[0005] According to another embodiment of the disclosure, there is provided a method for lithographic patterning, comprising: providing a target layer; depositing a carbon-containing layer over the target layer using a deposition process that provides a precursor that is transported towards a surface and chemically modifies the precursor to obtain the carbon-containing layer on the surface, wherein the carbon-containing layer has at least 50% carbon; forming a silicon-containing layer on the carbon-containing layer; forming a resist layer over the silicon-containing layer; exposing a portion of the resist layer to radiation to provide a patterned resist layer; etching a portion of the silicon-containing layer that is not covered by the patterned resist layer to form a patterned silicon-containing layer; after etching the portion of the silicon-containing layer, etching a portion of the carbon-containing layer that is not covered by the patterned silicon-containing layer to form a patterned carbon-containing layer; and using the patterned carbon-containing layer to define a pattern in the target layer.

[0006] According to yet another embodiment of the disclosure, there is provided a method of patterning a semiconductor device, the method comprising: depositing an amorphous carbon layer over a substrate; depositing a silicon-containing layer directly on the amorphous carbon layer; spin coating a photo-sensitive layer over the silicon-containing layer; and using a lithographic process, patterning the photo-sensitive layer to provide a first opening; etching the silicon-containing layer through the first opening; using the etched silicon-containing layer as a masking element during etching of the deposited amorphous carbon layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] The disclosure can best be understood by reading the following detailed description in conjunction with the accompanying drawings, in which:

[0008] FIG. 1 A flowchart illustrating an embodiment of a method of lithographic patterning according to aspects of the disclosure is shown.

[0009] FIG. 2 , FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 , FIG. 9 , FIG. 10 , FIG. 11 , FIG. 12 , FIG. 13 , FIG. 14 , FIG. 15 and FIG. 16 A cross-sectional view of an example device 200 is provided, aspects of which are fabricated according to the methods of FIG. 1

[0010] ​FIG. 17 A cross-sectional view of another example device having an adhesion layer and having aspects fabricated according to the method of FIG. 1

[0011] FIG. 18 A cross-sectional view of another example device having a patterned layer and having aspects fabricated according to the method of FIG. 1

[0012] FIG. 19 FIG. 20A FIG. 20B FIG. 21A FIG. 21B FIG. 22 FIG. 23A FIG. 23B FIG. 24A FIG. 24B FIG. 25A FIG. 25B FIG. 26A FIG. 26B FIG. 27A FIG. 27B FIG. 28A FIG. 28B FIG. 29A FIG. 29B A cross-sectional view of an example device 1900 having aspects fabricated according to the method of FIG. 1

[0013] FIG. 30 A schematic view of a partial deposition tool that can be used in accordance with aspects of the disclosure is provided.DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, a first feature can be formed over or on a second feature, which can include embodiments where the first feature and the second feature are formed in direct contact, and can also include embodiments where additional features can be formed between the first feature and the second feature, such that the first feature and the second feature can not be in direct contact. In addition, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0015] ​​​​​​​​​​​​​​​​​​​​​​Furthermore, spatially relative terms (for example, "beneath", "below", "lower", "above", "upper", and the like) can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] As the pitch of the elements of semiconductor devices continues to decrease and the size of the features continues to shrink, there is a need to improve patterning methods and materials to provide high quality, increased patterning density, and reduced critical dimension (CD) devices. The present disclosure provides material compositions, material stacks, and methods of implementing the compositions and stacks that can improve patterning metrics, including line width roughness (LWR) and local critical dimension uniformity (LCDU) in some embodiments. In some embodiments, these improvements drive the formation of materials using compositions and / or deposition methods that produce high density materials, increased stiffness materials, improved elastic modulus materials, and / or high etch selectivity materials for one or more aspects of patterning. The use of these properties, alone or in combination, can improve LWR and LCDU.

[0017] One feature of semiconductor devices that implement strict size and pitch requirements is back end of line (BEOL) features. BEOL features include those wiring or metallization layers that provide interconnects between various devices of a substrate. In some embodiments, trenches or via openings are patterned into a dielectric layer. By controlling the configuration of the trenches and via openings, when the trenches or openings are subsequently filled with a conductive material, the wiring of the interconnects of the device is provided.

[0018] Reference FIG. 1FIG. 1 illustrates a method 100 of patterning a layer. The method 100 can be used to pattern a layer of a semiconductor device. The semiconductor device can include SRAM and / or other logic circuitry, passive components, or active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), CMOS transistors, bipolar junction transistors (BJTs), lateral diffusion MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. Exemplary NFETs and PFETs include multi-gate devices (e.g., fin-type field effect transistors (FinFETs)), gate-all-around (GAA) devices, and / or other suitable device types. The semiconductor device can be included in a microprocessor, memory, and / or other IC device. In some embodiments, the semiconductor device is part of an IC chip, a system on a chip (SoC), or a portion thereof.

[0019] The method 100 can be implemented in whole or in part by systems employing deep ultraviolet (DUV) lithography, extreme ultraviolet (EUV) lithography, electron beam (e-beam) lithography, x-ray lithography, and other lithography processes to improve pattern size precision. Additional operations can be provided before, during, and after the method 100, and some of the operations described can be replaced, eliminated, or moved to a different order for additional embodiments of the method. The method 100 is an example and is not intended to limit the present disclosure to beyond the scope of the claims. The method 100 is described below in connection with FIG. 2 to FIG. 16 FIGS. 1-4.

[0020] The method 100 begins at block 102, where one or more target layers are provided for patterning. The target layer(s) are any layer(s) that need to be patterned. By patterning the target layer(s), the target layer(s) are configured into a plurality of features (composed of the target layer) with openings interposed between the features. The pattern can be for various semiconductor device features, such as interconnect lines, gate structures, isolation structures, active regions, and similar features. In some embodiments, the target layer pattern is provided with a resolution that is below the resolution limit of the lithography equipment due to patterning methods such as multiple patterning techniques.

[0021] In some embodiments, the target layer(s) are provided over a semiconductor structure. The semiconductor structure includes a semiconductor substrate, and in some embodiments includes various layers or features disposed on the semiconductor substrate. In one embodiment, the semiconductor substrate includes silicon. Alternatively or additionally, the substrate includes another elemental semiconductor, such as germanium; a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide); an alloy semiconductor (e.g., silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations of the foregoing). Alternatively, the substrate is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be fabricated using separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods. Within or on the substrate, there can be various features associated with semiconductor devices. These features can include transistor features such as gate structures and source / drain regions; isolation features; interconnect features, such as metallization layers and vias; and / or other features.

[0022] As just one example, FIG. 2 A semiconductor structure 202 is shown. The semiconductor structure 202 includes a base substrate 201 on which a plurality of active devices 203 are formed. The illustrated devices include gate structures 205 and source / drain features 207, with intervening isolation features 209. A multilayer interconnect (MLI) 213 is formed over the devices 203. The MLI 213 can include a dielectric layer 211 formed over the devices, as well as exemplary contacts 215 that extend to the source / drain features 207. The MLI 213 includes various other metallization layers, vertically extending vias, and intervening isolation layers that connect various features of the devices 203 (as described below).

[0023] The gates 205 are configured to implement desired functionality according to design requirements of the associated devices, such as to provide a p-type work function or an n-type work function. The gates 205 can include a gate dielectric layer and a gate electrode (e.g., a work function layer and a body conductive layer). The gate structures 205 can include many other layers, such as a cap layer, an interface layer, a diffusion layer, a barrier layer, a hardmask layer, or combinations of the foregoing.

[0024] The gate dielectric layer(s) of the gate structure can include a high-k dielectric layer including a high-k dielectric material, which refers to a dielectric material having a dielectric constant greater than that of silicon dioxide (k ~ 3.9). For example, the high-k dielectric layer includes HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3(BTO), (Ba,Sr)TiO3(BST), Si3N4, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other high-k dielectric materials suitable for metal gate stacks, or combinations of the foregoing. The high-k dielectric layer is formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations of the foregoing. The gate electrode layer(s) of the gate structure are formed over the gate dielectric; the gate electrode includes a conductive material, such as, for example, polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations of the foregoing. In some embodiments, the gate electrode includes a work function layer and a bulk conductive layer. The work function layer is a conductive layer that is tuned to have a desired work function (e.g., an n-type work function or a p-type work function), and the bulk conductive layer is a conductive layer formed over the work function layer. In some embodiments, the work function layer includes an n-type work function material, such as, for example, Ti, silver, manganese, zirconium, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function materials, or combinations of the foregoing. In some embodiments, the work function layer includes a p-type work function material, such as, for example, ruthenium, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations of the foregoing. The bulk (or fill) conductive layer includes a suitable conductive material, such as, for example, Al, W, Ti, Ta, polysilicon, Cu, metal alloys, other suitable materials, or combinations of the foregoing. The gate electrode is formed by any of the processes described herein, such as ALD, CVD, PVD, electroplating, other suitable processes, or combinations of the foregoing.

[0025] The source / drain features 207 include doped regions suitable for providing the features of a semiconductor device, such as n-type dopants and / or p-type dopants. In some embodiments, the source / drain features 207 include epitaxial material. The epitaxial process can use CVD deposition techniques (e.g., LPCVD, VPE, and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, for n-type transistors, the epitaxial source / drain features include silicon, which can be doped with carbon, phosphorous, arsenic, other n-type dopants, or combinations thereof (e.g., forming Si:C epitaxial source / drain features, Si:P epitaxial source / drain features, or Si:C:P epitaxial source / drain features). In some embodiments, for p-type transistors, the epitaxial source / drain features include silicon germanium or germanium, which can be doped with boron, other p-type dopants, or combinations thereof (e.g., forming Si:Ge:B epitaxial source features).

[0026] In some implementations, the isolation features 209 are shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, local oxidation of silicon (LOCOS) structures, other suitable isolation structures, or combinations thereof. The isolation features 209 can include a multi-layer structure of suitable dielectrics (e.g., oxides).

[0027] The dielectric layer 211 can be an interlayer dielectric (ILD) portion of the MLI. The dielectric layer 211 can include dielectric materials including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BSG, BPSG, FSG, xerogel, aerogel, amorphous fluorocarbon, parylene, BCB-based dielectric materials, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the dielectric layer 211 includes a dielectric material having a dielectric constant less than that of silicon dioxide (e.g., k < 3.9). In some embodiments, the dielectric layer 211 includes a dielectric material having a dielectric constant less than about 2.5 (i.e., an extremely low-k (ELK) dielectric material), such as silicon dioxide (SiO2) (e.g., porous silicon dioxide), silicon carbide (SiC), and / or carbon-doped oxides (e.g., SiCOH-based materials (e.g., having Si-CH3 bonds)), each of which is tuned / configured to have a dielectric constant less than about 2.5. The dielectric layer 211 can include a multi-layer structure having multiple dielectric materials.

[0028] As discussed above, the MLI 213 includes insulating layers and conductive layers. The MLI 213 electrically couples various devices (e.g., p-type transistors and / or n-type transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate electrodes and / or epitaxial source / drain features of p-type transistors and / or n-type transistors) disposed on the semiconductor structure 202 so that the various devices and / or components can operate as required by the design of the semiconductor device. The MLI 213 includes a combination of dielectric layers and conductive layers (e.g., metal layers) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect features (e.g., device-level contacts and / or vias) and / or horizontal interconnect features (e.g., wires). The vertical interconnect features generally connect horizontal interconnect features in different layers (or different planes) of the MLI 213. During operation, the interconnect features are configured to route signals between devices and / or components of devices, and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to the devices and / or components of devices.

[0029] In some embodiments, other features are present on the semiconductor structure 202, including other portions of active or passive devices and interconnects for these portions. In other embodiments, some or all of the various features or devices discussed above are omitted. For example, in one embodiment, the semiconductor structure 202 includes a substrate 201 (e.g., a silicon substrate), and the substrate itself is the target layer to be patterned.

[0030] In some implementations, the block 102 includes forming one or more target layers over a semiconductor structure. In one embodiment, the target layer is an interlayer dielectric (ILD) of a multilayer interconnect (MLI), such as the ILD layers discussed above. The target layer can be an ILD layer of a higher MLI layer, such as ILD-1 and ILD-3, with the numerical designation providing the number of layers above the semiconductor device. The semiconductor device can have any number of metallization / ILD layers, in many implementations exceeding 5 or 10 layers. Other examples of target layers are also possible, including semiconductor substrates, other dielectric layers, semiconductor layers, conductive layers, and / or other suitable layers implemented in semiconductor manufacturing.

[0031] Referring to FIG. 3 In the example of FIG. 3, a target layer 302 is provided on the semiconductor structure 202. In one embodiment, the target layer 302 is an interlayer dielectric (ILD) portion of a MLI. The target layer can be provided using a deposition process (e.g., CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, HARP, HDP, other suitable methods, or combinations of the foregoing).

[0032] In one embodiment, target layer 302 is an ILD layer comprising a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxides, PSG, BSG, BPSG, FSG, desiccant, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric materials, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer comprises a dielectric material having a low-k dielectric or an ELK dielectric. Target layer 302 may comprise a multilayer structure having a variety of dielectric materials.

[0033] In other embodiments, the target layer 302 may be another dielectric layer, a conductive layer (e.g., interconnects, capacitor plates, electrodes of memory cells, etc.), and / or a semiconductor layer (e.g., gate features, fin structures, epitaxial layers, etc.). In one embodiment, the target layer 302 is part of a semiconductor substrate, such as substrate 201. In one embodiment, the semiconductor structure 202 includes only substrate 201, such that the target layer is formed directly on substrate 201. Alternatively, the target layer 301 is part of substrate 201, such that no additional features of the semiconductor structure 202 (e.g., 203-215) are omitted.

[0034] Then, method 100 proceeds to block 104, where one or more masking layers are formed over the target layer. The masking layer may include a hard mask material. In some embodiments, the masking layer may be a sacrificial layer for patterning and / or protecting the underlying layers. In some embodiments, the masking layer may be a multilayer structure. In another embodiment, the masking layer is a three-layer structure that includes a hard mask layer (e.g., a metal-containing organic layer) between dielectric material layers. The masking layer may include one or more anti-reflective coatings.

[0035] refer to FIG. 3 For example, a masking layer 304 is formed over the target layer 302. In one embodiment, the masking layer 304 includes a first layer 304A, a second layer 304B, and a third layer 304C. In some embodiments, the first layer 304A and the third layer 304C comprise silicon oxide or another dielectric material. In some embodiments, the second layer 304B comprises a hard mask material, such as a metallic hard mask material. In one embodiment, the metallic hard mask material is TiN. Other exemplary metallic hard mask materials include Ti, Ta, W, TaN, WN, and / or other suitable components. In other embodiments, the second layer 304B is an organic hard mask. In other embodiments, the hard mask layers are configured differently based on lithography requirements.

[0036] In some embodiments, the thickness of the first 304A layer and / or the third 304C layer is approximately arrive between about 1000 A and 2000 A. In another embodiment, the thickness of the first layer 304A and / or the third layer 304C is between about 500 A and 1000 A. between about 1000 A and 2000 A. In another embodiment, the thickness of the second layer 304B is between about 500 A and 1000 A. between about 1000 A and 2000 A. In another embodiment, the thickness of the second layer 304B is between about 500 A and 1000 A. between about 1000 A and 2000 A. In another embodiment, the thickness of the second layer 304B is between about 500 A and 1000 A.

[0037] The method 100 then proceeds to block 106, where a first layer of a multi-layer patterned stack is deposited. In some embodiments, the multi-layer patterned stack can include three layers as described below. For example, the three layers can include a top or image layer, a middle or transfer layer, and a bottom or base layer. These layers are discussed in terms of deposition order, i.e., bottom to top order with respect to blocks 106, 108, and 110 of the method 100. In some embodiments, the multi-layer patterned stack provides an organic / inorganic / organic layer stack.

[0038] ​​​In one embodiment, block 106 deposits a first layer (e.g., a base layer or a bottom layer) of the multi-layer patterned stack as a carbon-containing layer. The first layer can include a carbon-based material having a carbon (C) composition greater than fifty (50) atomic percent. Other components of the carbon-containing layer include hydrogen (e.g., amorphous hydrogenated carbon). In one embodiment, the carbon-based layer is amorphous carbon (a-carbon). In some embodiments, when the carbon-containing layer is formed, no other atomic constituents are intentionally deposited, e.g., other than carbon and hydrogen. For example, the atomic percent of carbon can be between about 50% to 75%, while the remaining 50% to 25 atomic percent can be hydrogen. In another embodiment, the atomic percent of carbon is about 65 atomic percent, while the atomic percent of hydrogen is about 35 atomic percent. In some implementations, the first layer of carbon-containing material is deposited by a chemical vapor deposition (CVD) process such as plasma-enhanced CVD (PECVD). Other CVD processes include high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), sub-atmospheric vapor deposition (SAVCD), or other suitable methods. In one embodiment, the first layer of carbon-containing material is deposited by a physical vapor deposition (PVD) such as plasma-enhanced (PE) PVD. Other PVD processes include sputtering, e-beam, thermal evaporation, or other suitable methods. In one embodiment, the first layer of carbon-containing material is deposited by atomic layer deposition (ALD) such as plasma-enhanced (PE) ALD.

[0039] Deposition of the carbon-containing layer (e.g., PVD, ALD, CVD process) can be characterized as using a process(es) in which molecules of a compound used as a precursor are delivered to a target surface and chemically modified to obtain a desired film. These deposition processes are in contrast to spin coating processes or dip coating processes. In one embodiment, the precursor used to form the carbon-containing layer is delivered in a gaseous form. The following table provides an exemplary normalized comparison of a spin-on bottom anti-reflective coating to an a-carbon layer that can be deposited, e.g., by a CVD, ALD, or PVD process.

[0040]

[0041]

[0042] In some embodiments, the deposition of the carbon-containing layer by the above- described methods includes providing a precursor reactive gas and an inert gas. Example precursors include carbon-containing compounds. In one embodiment, the precursors include at least one of methane (CH4), acetylene (C2H2), or propylene (C3H6). Example inert gases include nitrogen, argon, helium, xenon, other suitable carrier gas constituents, or combinations thereof. In one embodiment, the inert gas includes at least one of argon (Ar) or helium (He). The carbon-containing layer can be deposited by introducing the gaseous precursors (along with the inert gas) into a chamber provided with a heated semiconductor structure. The reaction between the precursors (and / or between the precursors and the surface of the semiconductor structure) produces a solid film layer of carbon-containing material on the semiconductor structure. The process can be performed by the tools shown below. FIG. 30

[0043] The deposition process of the carbon-containing first layer of the multi-layer patterned stack can include a process temperature between room temperature (RT) and 600 degrees Celsius. The deposition process of the carbon-containing first layer of the multi-layer patterned stack can include a process pressure between about zero (0) and 100 Torr. The pressure and / or temperature are selected to control dissociation of the precursors and excitation of carbon atoms. In one embodiment, the process temperature is the temperature of the wafer and / or the processing chamber. The power of the deposition (e.g., plasma generation) can be between about 10 Mhz and 25 MHz. The power is selected to provide a supply of plasma and proper dissociation and reaction of the precursors. The greater the power, the higher the degree of dissociation, but there can be a risk of arcing or other issues with tool performance.

[0044] In some embodiments, the carbon-containing first layer is deposited to a thickness of less than In another embodiment, the thickness of the carbon-containing film is between about and In one embodiment, the thickness of the carbon-containing film is between about and The thickness of the carbon-containing layer can be selected based on etch selectivity to surrounding layers, adjustments to the etch process, underlying topography, and / or other criteria. For example, topography having a high aspect ratio underneath the carbon-containing first layer can require an increased thickness to properly cover the topography. In one embodiment, the etch selectivity between the carbon-containing layer and underlying layers (e.g., masking layers, target layers, intermediate layers) can affect the thickness, for example, a greater thickness can be required for cases of reduced selectivity between the carbon-containing layer and the target layer.

[0045] ​In some embodiments, prior to forming the carbon-containing layer, another layer is formed between the hard mask and the carbon-containing layer. In some implementations, the layer is a mandrel layer, e.g., a layer used to form a mandrel in a double patterning process. In other embodiments, e.g., in a single patterning process, the carbon-containing layer is deposited directly on the masking layer (e.g., 304C).

[0046] Referring to FIG. 4 In an example, a bottom layer 402 is formed over the semiconductor structure 202. The bottom layer 402 can be a carbon-containing layer as described above. For example, in some embodiments, the bottom layer 402 is amorphous carbon. The bottom layer 402 can be deposited by one of a PVD, ALD, or CVD process, as described above.

[0047] The method 100 then proceeds to block 108, where a second layer of a multi-layer patterning stack is deposited. The second layer of the multi-layer patterning stack can be a silicon-containing layer. In some embodiments, the second layer of the multi-layer patterning stack is a silicon-containing hard mask layer. In one embodiment, the second layer is a spin-on glass layer (SOG). In some embodiments, the second layer is a silicon-based material as discussed in the following paragraph(s).

[0048] In some embodiments, the second layer can include a silicon-based material having greater than fifty (50) atomic percent of a silicon (Si) component. Other components of the silicon-containing layer include hydrogen. In one embodiment, the second layer that is silicon-containing is amorphous silicon. In some implementations, the second layer of silicon-containing material is deposited by a chemical vapor deposition (CVD) process such as plasma enhanced CVD (PECVD). Other CVD processes include high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), sub-atmospheric vapor deposition (SAVCD), other suitable methods. In one embodiment, the second layer of silicon-containing material is deposited by a physical vapor deposition (PVD) such as plasma enhanced (PE) PVD. Other PVD processes include sputtering, e-beam, thermal evaporation. In one embodiment, the second layer of silicon-containing material is deposited by an atomic layer deposition (ALD) such as plasma enhanced (PE) ALD. Deposition of the silicon-containing layer (e.g., PVD, ALD, CVD processes) can be characterized as using a process(es) in which molecules of a compound used as a precursor are delivered to a substrate surface and chemically modified to obtain the desired film. These deposition processes are in contrast to spin-on or dip-coating processes.

[0049] In some embodiments, the deposition of the silicon-containing layer by the methods discussed above includes providing a precursor reactive gas and an inert gas. Example precursors include silicon-containing compounds. Example inert gases include nitrogen, argon, helium, xenon, other suitable carrier gas constituents, or combinations of the foregoing. In one embodiment, the precursor includes at least one of silane (SiH4) or disilane (Si2H6). In one embodiment, the inert gas includes at least one of argon (Ar) or helium (He). The silicon-containing layer can be deposited by introducing the gaseous precursor (along with the inert gas) into a chamber provided with a heated semiconductor structure. The reaction between the precursor (and / or the surface of the semiconductor structure) forms a solid film layer of silicon-containing material on the semiconductor structure. The process can be performed by tools such as those illustrated below. FIG. 30

[0050] The deposition process of the second silicon-containing layer of the multi-layer patterned stack can include a process temperature between room temperature (RT) and 600 degrees Celsius. The deposition process of the second silicon-containing layer of the multi-layer patterned stack can include a process pressure between about zero (0) and 100 Torr. In one embodiment, the temperature and / or pressure are determined to provide suitable dissociation of the precursor and / or excitation of the silicon atoms. In one embodiment, the process temperature is the temperature of the wafer and / or the processing chamber. The power of the deposition can be between about 10 MHz and 25 MHz. The power is selected to provide suitable dissociation and reaction of the precursor. The greater the power, the greater the degree of dissociation, but there can be a risk of arcing or other issues with the tool performance.

[0051] In some embodiments, the second silicon-containing layer is deposited to have a thickness of less than In another embodiment, the thickness of the silicon-containing film is between about and In one embodiment, the thickness of the silicon-containing film is between about and The thickness of the silicon-containing layer can be selected based on the etch selectivity to surrounding layers and adjustments to the etch process to provide suitable pattern transfer performance.

[0052] In some embodiments, the silicon-containing layer is deposited directly on the carbon- containing layer. Thus, in some embodiments, the amorphous carbon layer directly interfaces with the amorphous silicon layer to provide a base layer and an intermediate layer of a three-layer stack. In some embodiments, these depositions of blocks 106 and 108 are performed in situ, for example in tools such as those illustrated below. FIG. 30 In some embodiments, block 106 is provided in tools such as those illustrated below. FIG. 30 In some embodiments, block 108 includes spin-on silicon layers.

[0053] ​In one embodiment, the interface between the silicon-containing layer and the carbon- containing layer can be a discrete interface transitioning from a-C to a-Si. In some embodiments, a structure is formed in which the ratio of C to Si varies continuously.

[0054] In some implementations of the method 100, the silicon-containing layer is deposited as amorphous silicon by, for example, a CVD, PVD, or ALD process. In some embodiments, the amorphous silicon material is subsequently modified. For example, during a subsequent patterning step, an etching process can modify the composition (a-Si) in whole or in part. For example, when an etching gas containing oxygen (e.g., O2) is used, the silicon-containing layer can absorb oxygen atoms. Further, when an etching process (e.g., including an etching gas containing oxygen) etches the underlying carbon-containing layer, the silicon-containing layer can absorb oxygen and / or carbon that converts some or all of the deposited a-Si material to a SiO2polymer composition.

[0055] Referring to FIG. 5 In one example, an intermediate layer 502 is formed over the semiconductor structure 202. In one embodiment, the intermediate layer 502 includes silicon. In another embodiment, the intermediate layer 502 is a SOG material. In other embodiments, the intermediate layer 502 is a silicon-containing layer as described above that includes more than 50 atomic % Si and is deposited by at least one of PVD, ALD, or CVD. For example, in some embodiments, the intermediate layer 502 is amorphous silicon.

[0056] The method 100 then proceeds to block 110, at which a photo-sensitive layer of a multi-layer patterning stack is deposited. The photo-sensitive layer can also be referred to as a photoresist or simply a resist. The resist layer can be deposited by a spin-on process. For example, spin-on can include coating a liquid polymer material onto the semiconductor structure 202 (e.g., the intermediate layer 502). In one embodiment, the resist layer is a radiation-sensitive material for a desired wavelength, such as, for example, a photoresist including an I-line resist, a DUV resist including a krypton fluoride (KrF) resist and an argon fluoride (ArF) resist, an EUV resist, an electron beam (e-beam) resist, and an ion beam resist. In another embodiment, the resist is a 193-nm resist. In another embodiment, the resist is an EUV resist sensitive to a 13.5 nm wavelength exposure for an EUV lithography process. In one embodiment, the resist is sensitive to EUV radiation and is further used for negative tone development (NTD), i.e., its solubility in a NTD developer decreases with EUV radiation.

[0057] The resist layer can include a polymeric back-bone and one or more photoactive components (for the wavelength of radiation used to pattern the resist layer). The wavelengths include those associated with photolithography processes such as deep ultraviolet (DUV) photolithography, extreme ultraviolet (EUV) photolithography, electron beam (e-beam) photolithography, x-ray photolithography, and / or other photolithography processes. In one embodiment, a resist that employs chemical amplification is commonly referred to as a "chemically amplified resist" (CAR). A photoresist includes a polymer that resists etching or ion implantation, an acid-generating compound (e.g., a photoacid generator (PAG)), and a solvent. In some examples, the polymer also includes at least one acid-labile group (ALG) that reacts with the acid. In some embodiments, the resist includes a polymer that chemically amplifies, for example, through polyhydroxystyrene (PHS) groups that provide, for example, sensitivity to EUV photolithography. In some implementations, a non-chemically amplified resist is provided, for example, a polymethyl methacrylate (PMMA) resist. While many resist options are organic, inorganic resists are also possible.

[0058] In some embodiments, the resist layer is formed directly on the intermediate layer (e.g., a-Si). In some embodiments, a small amount of silicon oxide (e.g., native SiO2) is formed on top of the a-Si layer and the resist layer is formed on it. In other embodiments, for example as discussed below, an adhesion layer is interposed between the resist layer and the intermediate layer.

[0059] Referring to FIG. 6 In an example, a resist layer 602 is deposited. The resist layer 602, the intermediate layer 502, and the bottom layer 402 provide a multi-layer patterning stack 604, specifically a three-layer stack.

[0060] Then, the method 100 proceeds to block 112, at which the photo-sensitive layer is patterned using a photolithography technique. Following the deposition of the resist layer (which can be conformal), in some embodiments, the photolithography process includes performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process. During the exposure process, the resist layer is exposed to radiant energy (e.g., ultraviolet (UV), deep ultraviolet (DUV), or extreme ultraviolet (EUV) light), where the mask blocks, transmits, and / or reflects the radiation to the resist layer according to the mask pattern and / or mask type (e.g., binary mask, phase shift mask, or EUV mask) of the mask, such that an image is projected onto the resist layer (which corresponds to the mask pattern). In some embodiments, the method includes using immersion lithography. As the resist layer is sensitive to the radiant energy (as described above), during the development process, the exposed portions of the resist layer undergo a chemical change and the exposed (or unexposed) portions of the resist layer dissolve according to the properties of the resist layer and the properties of the developer used in the development process. That is, in photolithographic patterning, after the resist film is exposed to radiation such as EUV radiation (or alternatively other radiation, such as electron beams), it is developed in a developer (a chemical solution). The developer removes some portions of the resist film (e.g., the exposed portions in a positive photoresist or the unexposed portions in a negative photoresist), thereby forming a resist pattern that can include a line pattern and / or a trench pattern. After development, the patterned resist layer includes a resist pattern corresponding to the mask. Note that, in some embodiments, the carbon-containing layer and the silicon-containing layer are not affected by the exposure or development (e.g., no chemical change).

[0061] Referring to FIG. 7 the example of FIG. 6A, the resist layer 602 is patterned to form a series of masking element features 602’ (consisting of exposed and developed resist) and intervening openings. In one embodiment, the pattern is provided by EUV photolithography techniques as described above.

[0062] The method 100 then proceeds to block 114, at which the pattern of the photo- sensitive layer is etched into the remaining layers of the multi-layer patterned stack to form the masking elements. FIG. 8 、 FIG. 9 、 FIG. 10 and FIG. 11An etching process(es) is / are illustrated that are used to create mask elements by etching the pattern of the resist layer 602' into the underlying intermediate layer 502 and the base layer 402 of the three-layer patterned stack 604. The etching process(es) can include a reactive ion etch or a plasma etch system. Dry etching processes can implement etching gases including hydrogen (e.g., H2and / or CH4), etching gases including nitrogen (e.g., N2and / or NH3), etching gases including chlorine (e.g., Cl2, CHCl3, CCl4, and / or BCl3), etching gases including oxygen (e.g., O2), etching gases including fluorine (e.g., F2, CH3F, CH2F2, CHF3, CF4, C2F6, SF6, and / or NF3), etching gases including bromine (e.g., Br, HBr, CH3Br, CH2, Br2, and / or CHBr3), etching gases including iodine, other suitable etching gases, or combinations of the foregoing. In some embodiments, a dry etching process can use a carrier gas to deliver the etching gas. Carrier gases include nitrogen, argon, helium, xenon, other suitable carrier gas compositions, or combinations of the foregoing.

[0063] In some implementations, the first step of block 114 is a "descum process." For example, if the fidelity to the desired pattern is incomplete, the descum process can remove (residual) portions of resist from areas where resist is not desired. This process removes undesired residual resist material while also reducing the height of the desired patterned resist. In some embodiments, the descum process can slightly etch the underlying intermediate layer of the multi-layer patterned stack. FIG. 8 A configuration of the multi-layer patterned stack after a descum process that includes a slight etch of the intermediate layer 502 is shown. The height of the resist features 602' has been reduced, and in some implementations, the top surface is rounded. A variety of etching conditions can be selected for this descum step, such as an O2 / Ar-based descum, a CF4 / CHF3-based descum, and / or other suitable etchants.

[0064] Block 114 can be performed to include an etching process of the intermediate layer or the silicon-containing layer. In one embodiment, the etching process provides an etch that is selective to the silicon-containing layer (e.g., selective to SOG or selective to amorphous silicon depending on the composition selected). The etching process patterns the silicon-containing intermediate layer according to the pattern of the resist. Referring to the example of FIG. 5B, the intermediate layer 502 is etched to provide a patterned intermediate layer 502'. The etching of the intermediate layer 502 can stop at the top surface of the base layer 402. In some implementations, the patterned intermediate layer 502' includes tapered sidewalls, e.g., due to a directional etch. FIG. 9 ​

[0065] Block 114 can be performed to include an etching process for the underlying or carbon-containing layer. In one embodiment, the etching process provides selective etching of the carbon-containing layer (e.g., selective etching for amorphous carbon). The etching process patterns the carbon-containing underlying layer according to a pattern of the resist and / or a patterned intermediate layer. In some embodiments, the resist layer 602' is removed during the etching process of the underlying layer 402. For example, if the components of the underlying layer 402 and the resist layer 602 are similar (e.g., based on organic carbon), the etchant can remove components of both. Reference FIG. 10 For example, the underlayer 402 is etched to provide a patterned underlayer 402'. The etching of the underlayer 402 may stop at the top surface of the masking layer 304. The patterned underlayer 402' (e.g., a patterned α-carbon layer) may have improved line edge roughness (LER) because beneficial properties (e.g., density, modulus, hardness) are achieved for its composition during the deposition step, as described above.

[0066] Another benefit of some embodiments of method 100 is that the patterned intermediate layer 502' may be less lost after the etching process used to pattern the bottom layer 402. In some embodiments, the a-Si deposited layer is not provided, for example, by ALD, PVD, or CVD as described above, and the patterned intermediate layer 502' can be completely removed from the device (e.g., SOG). In embodiments where a-Si is provided as a silicon-containing layer, the patterned intermediate layer 502' may retain at least 5 nm of height h1. In some embodiments, a height h1 of approximately 5–15 nm is retained. See also FIG. 10 The remaining intermediate layer 502' is shown. In one embodiment, the ratio of h1 to h2 is approximately 1:2.5 to 1:5. In one embodiment, the ratio of h1 to d1 is 2:1 to 10:1.

[0067] In some embodiments of method 100 and block 114, the resulting patterned carbon-containing layer and / or the resulting patterned silicon-containing layer may be modified, which involves reducing the width of the features. (See reference...) FIG. 11In the example of FIG. 4B, the width (x-direction) of the patterned features 402' is reduced to provide finer features (w2). The width of the patterned silicon-containing layer 502' above can similarly be reduced. The trimming can be performed by an appropriate etching process, such as an isotropic etch, to achieve the desired dimensions (e.g., critical dimensions). In some embodiments, the trimming process can reduce the dimensions below the lithographic limit of the process implemented in the block 112. The trimming can reduce the width, for example, by 10% to 30%. It should be noted that if the resulting width w2 is too fine, the aspect ratio of the patterned features 402' can be at risk of collapse of the feature. In some embodiments, the underlying layer(s) are then patterned using the trimmed patterned features 402' of the bottom layer of the multi-layer patterned stack.

[0068] Then, the method 100 proceeds to block 116, at which the resulting patterned features of the multi-layer patterning stack are used as masking elements during patterning of an underlying layer, such as a masking layer. The patterning of the underlying layer depends on the patterning method implemented by the method 100. In some embodiments, the masking elements provided by the patterned multi-layer patterning stack can be used to directly pattern a target layer, and thus, block 116 is omitted from the method 100. In some embodiments, the masking elements provided by the patterned multi-layer patterning stack can be used to directly pattern other patterned layers (e.g., underlying masking layer(s) (e.g., metal hard mask)) that are in turn used to pattern an underlying layer. The etching process(s) can include a reactive ion etch or a plasma etch system. The dry etching process can implement an etching gas including hydrogen (e.g., H2 and / or CH4), an etching gas including nitrogen (e.g., N2 and / or NH3), an etching gas including chlorine (e.g., Cl2, CHCl3, CCl4, and / or BCl3), an etching gas including oxygen (e.g., O2), an etching gas including fluorine (e.g., F2, CH3F, CH2F2, CHF3, CF4, C2F6, SF6, and / or NF3), an etching gas including bromine (e.g., Br, HBr, CH3Br, CH2, Br2, and / or CHBr3), an etching gas including iodine, other suitable etching gases, or a combination thereof. In some embodiments, the dry etching process can use a carrier gas to deliver the etching gas. The carrier gas includes nitrogen, argon, helium, xenon, other suitable carrier gas compositions, or a combination thereof. The wet etching process can use a wet etchant solution including H2SO4 (sulfuric acid), H2O2 (hydrogen peroxide), NH4OH (ammonium hydroxide), HC1 (hydrochloric acid), HF (hydrofluoric acid), DHF (dilute HF), HNO3 (nitric acid), H3PO4 (phosphoric acid), H2O (water) (which can be deionized water (DIW) or ozonated deionized water (DIWO3)), ozone (O3), other suitable chemicals, or a combination thereof.

[0069] Referring to FIG. 12 In the example of FIG. 4, the patterned bottom layer 402’ is used as a masking element to form a patterned layer 304C’ when etching the masking layer 304 (specifically, the dielectric layer 304C). In one embodiment, the etching process is selective to the composition of the dielectric layer 304C, such as being selective to silicon oxide. In some embodiments, the silicon-containing layer 502’ is removed during the etching of the dielectric layer 304C. In some embodiments, the etching process stops at the hard mask layer 304B (e.g., a metal hard mask composition). The etching process can provide a rounded top surface of the patterned carbon-containing layer 402’.

[0070] refer to FIG. 13 For example, during etching of masking layer 304 (specifically, metal hard mask layer 304B), a patterned underlying layer 402' (and a patterned dielectric layer 304C') can be used as an etching mask to form the patterned hard mask layer 304B'. In some embodiments, etching of the metal hard mask layer 304B includes over-etching into the underlying dielectric layer 304A (e.g., silicon oxide). However, the etchant can typically be selective for the material of the hard mask layer 304B'.

[0071] After the metal hard mask layer 304B is processed, a rinsing or cleaning process can be performed. In some embodiments, the rinsing process can remove the patterned carbon-containing layer 402', such as... FIG. 14 As shown. A patterned hard mask layer 304B' is typically suitable for providing a masking element for patterning one or more underlying target layers.

[0072] Then, method 100 proceeds to block 118, where a masking element formed through the previous block is used during the etching of one or more target layers. (See reference...) FIG. 15 For example, the target layer 302 is patterned by an etching process, during which a patterned metal hard mask layer 304B' is used as a masking element defining the pattern to be formed. The patterned target layer 302' is configured to have the same pattern defined in the resist layer 602 above (in some embodiments, this pattern is further defined by a trimming process). It should be noted at this point that although method 100 has been described as providing a single patterning process (one photolithography process), other embodiments of method 100 that include patterning processes using multiple photolithography and etching processes are also possible. For example, dual patterning lithography (DPL) processes (e.g., lithography-etch-lithography-etch (LELE) process, self-aligned dual patterning (SADP) process, spacer-dielectric (SID) SADP process, other dual patterning processes, or combinations thereof), triple patterning processes (e.g., lithography-etch-lithography-etch-lithography-etch (LELELE) process, self-aligned triple patterning (SATP) process, other triple patterning processes, or combinations thereof), other multiple patterning processes (e.g., self-aligned quadruple patterning (SAQP) process), or combinations thereof.

[0073] In some embodiments, the underlying layer 304A has a similar composition as the target layer 302, so the underlying layer 304A is also patterned during the etching process to form a patterned layer 304A'. In other embodiments, the layer 304A is separately patterned to form a patterned layer 304A'. In one embodiment, any remaining portion of the hard mask layer 304 can be stripped after the target layer 302 is patterned.

[0074] In some embodiments, the target layer 302 is an ILD layer, and the patterned target layer 302' can define an opening or trench in which a metallization of an MLI is to be formed. In such embodiments, the method 100 continues with filling the trench with a conductive material, such as a metal, and polishing the conductive material using a process such as chemical mechanical planarization (CMP) to expose the patterned ILD layer, thereby forming a metal line in the ILD layer. This is illustrated in FIG. 16B, which shows the conductive features 1602 that can provide metal interconnect lines. FIG. 16

[0075] In some embodiments, the target layer 302 is a conductive layer to be used for a metal line, and is made of copper, aluminum, etc., or a combination thereof. In other embodiments, the target layer 302 is a dielectric layer, such as a low-k dielectric layer or a polymer layer, etc. In another embodiment, the target layer is a material suitable for forming a gate structure of a gate (or dummy gate structure) of a device, such as polysilicon. In other embodiments, the target layer 302 is a substrate and is made of a semiconductor material such as silicon, germanium, or diamond, etc. In such embodiments, a trench formed in the target layer of the substrate can define an isolation feature between fin structures suitable for manufacturing a fin field effect transistor (FinFET). In one embodiment, the target layer 302 is a mandrel layer. The mandrel layer can be a masking material, such as silicon nitride, oxide, silicon, amorphous silicon, a combination of the foregoing, or any other material that can be patterned and selectively removed. The patterned mandrel layer is then used as part of other patterning processes as part of a multi-patterning process (e.g., applying the method 100 to a dual patterning technique) to, for example, achieve smaller dimensions. The above are non-limiting examples of devices / structures that can be manufactured and / or improved using the method 100 according to aspects of the present disclosure.

[0076] ​In some embodiments, due to the properties of the patterning material and / or the steps described above, the patterned target layer has very smooth edges and sidewalls, and therefore low line edge roughness (LER) and linewidth roughness (LWR) and / or improved local critical size uniformity (LCDU). In some embodiments, this is because the materials and deposition processes (e.g., ALD, CVD, PVD) forming the carbon-containing and / or silicon-containing films provide material layers with high density, improved hardness, desired modulus, high etch selectivity, and / or other benefits. In some embodiments, beneficial properties such as high density are produced because impurities and / or undesirable bonds within the material layer can be dissociated by introducing plasma during the deposition process. Film properties, including density, modulus, hardness, etc., can be varied by deposition process knobs such as gas flow rate (precursor, inert gas), power, process temperature, and substrate temperature.

[0077] In one embodiment of method 100, an additional block is provided where an adhesion layer is formed in a multilayer patterned stack. For example, in one embodiment, the adhesion layer may be formed between an intermediate layer (e.g., a silicon-containing layer) and an upper resist layer. The adhesion layer may comprise a material such as hexamethyldisilazane (HDMS) or a bottom anti-reflective coating (BARC). In some embodiments, the material of the BARC is selected based on the photolithography process to be formed in order to provide suitable anti-reflective properties according to the wavelength of radiation. The thickness of the adhesion layer may be from about 0 angstroms to... Between. In embodiments where the adhesive layer is a surfactant, its thickness can be considered 0 due to its properties as a surface treatment agent. FIG. 17 An adhesion layer 1702 is shown, which is inserted between a patterned resist 602' and an intermediate layer 502 (containing a silicon layer). FIG. 17 and FIG. 7 The process is essentially the same, and method 100 is performed in a similar manner to the one described above when an adhesive layer is present. The adhesive layer may be patterned together with the intermediate layer 502.

[0078] In an embodiment of method 100, topographic structures such as patterned layers can be disposed beneath a multi-layered patterned stack. (See also...) FIG. 18 For example, a multi-layer patterned stack of resist layer 602, intermediate layer 502 and bottom layer 402 is disposed on a plurality of features 1802 provided on masking layer 304.

[0079] like FIG. 18As shown, the bottom layer 402 (carbon-containing layer) directly interfaces with the plurality of features 1802 and fills the gaps therebetween. In some embodiments, the bottom layer 402 is 1.2 to 4 times thicker than the height of the plurality of features 1802. After deposition, e.g., by CVD, PVD, or ALD as described above, the bottom layer 402 can be planarized by an appropriate process such as chemical mechanical polishing (CMP).

[0080] In one embodiment, the plurality of features 1802 are mandrels (e.g., silicon or other sacrificial material) to be used in a multi-patterning scheme such as a dual-patterning technique. For example, the method 100 can be performed using a layer of a target material designed to form the plurality of features 1802. A first multi-layer patterning stack is provided over the target material to pattern the plurality of features 1802. The method 100 can be repeated to form a second multi-layer patterning stack over the plurality of features 1802. The second multi-layer patterning stack can further modify the pattern of the plurality of features 1802 and / or features formed therefrom (e.g., spacer elements formed on sidewalls of the plurality of features 1802).

[0081] Reference is now made to FIG. 19 to FIG. 29B , which shows an embodiment of the method 100 implemented in a multi-patterning scheme that includes multiple photolithography and etching processes to pattern a target layer. FIG. 19 to FIG. 29B Examples of patterning of back end of line (BEOL) features are provided. In particular, metallization layers of a multi-layer interconnect are patterned. The description of the method 100 above applies in full to the description of the embodiments shown. FIG. 19 to FIG. 29B

[0082] FIG. 19 ​A device 1900 is shown having a semiconductor structure 202 on which a plurality of layers are formed. In one embodiment, the semiconductor structure 202 is substantially similar to that discussed above, including, for example, the presence of active devices (e.g., transistors). A first ILD layer 1902 and a first metallization layer 1904 of an MLI are formed over the semiconductor structure 202, where the MLI interconnects the active devices on the semiconductor structure 202. The ILD layer can include a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BSG, BPSG, FSG, xerogel, aerogel, amorphous fluorocarbon, parylene, BCB-based dielectric materials, polyimide, other suitable dielectric materials, or combinations of the foregoing. In some embodiments, the ILD layer 1902 includes a dielectric material having a dielectric constant less than that of silicon dioxide (e.g., k < 3.9). In some embodiments, the ILD layer 1902 includes a dielectric material having a dielectric constant less than about 2.5 (i.e., an extremely low-k (ELK) dielectric material), such as silicon dioxide (SiO2) (e.g., porous silicon dioxide), silicon carbide (SiC), and / or carbon-doped oxides (e.g., SiCOH-based materials (e.g., having Si-CH3bonds)), each of which is tailored / configured to have a dielectric constant less than about 2.5. The dielectric layer 1902 can include a multi-layer structure having a plurality of dielectric materials. The first metallization layer 1904 can be a conductive material, such as copper, aluminum, tungsten, and / or other suitable materials. The first metallization layer 1904 can be a multi-layer structure including, for example, a liner layer, a barrier layer, an adhesion layer, and / or other suitable layers.

[0083] An etch stop layer 1906 is disposed over the ILD layer 1902 and the first metallization layer 1904. In one embodiment, the etch stop layer 1906 includes a plurality of layers. The etch stop layer 1906 can include SiC, SiN, TEOS, hard black diamond (HBD), or other suitable components. Another ILD layer 1908 is disposed over the etch stop layer 1906. The ILD layer 1908 can be a target layer for patterning. For example, in some implementations, trenches will be patterned in the ILD layer 1908, and a conductive material (e.g., copper) will be deposited in these trenches by a damascene or dual damascene process to form a metallization layer. In some embodiments, if the first metallization layer 1904 is a metallization layer M, then the ILD layer 1908 and the metallization layer to be formed within it is a metallization layer M+1. The ILD layer 1908 can be substantially similar to the first ILD layer 1902, and can include the same or different components as the first ILD layer 1902.

[0084] A hard mask layer 1910 is provided over the target ILD layer 1908. In some embodiments, the hard mask layer 1910 is substantially similar to the masking layer 304. In one embodiment, the hard mask layer 1910 includes a first layer 1910A, a second layer 1910B, and a third layer 1910C. In one embodiment, the third layer 1910C is a dielectric layer such as TEOS. In one embodiment, the second layer 1910B is a metallic hard mask layer such as TiN. Other exemplary metallic hard mask materials include Ti, Ta, W, TaN, WN, and / or other suitable compositions. In one embodiment, the first layer 1810A is a nitrogen-free anti-reflective layer (NFARL).

[0085] A mandrel layer 1912 is provided over the hard mask layer 1910. In one embodiment, the mandrel layer 1912 is silicon such as amorphous silicon, polysilicon. The mandrel layer 1912 when patterned is used to provide sacrificial features to reduce the pitch of the patterned features by providing a spacer material over the features / mandrels, providing spacer features on the sidewalls of the mandrels, and subsequently removing the mandrel to allow the spacer features to define the reduced pitch. Mandrel spacer techniques include a self-aligned double patterning (SADP) process that reduces the pitch of the exposed pattern by a factor of two, a self-aligned quadruple patterning (SAQP) process that reduces the pitch of the exposed pattern by a factor of four, and other spacer patterning processes.

[0086] Reference is now made to FIG. 20A and FIG. 20B a first lithography process is performed. In some embodiments, the first lithography process can be referred to as a cut process for defining the spaces between subsequently formed metallization features. FIG. 20A A first lithography process is shown that includes forming a multi-layer patterning stack 604 over the mandrel layer 1912. The multi-layer patterning stack 604 includes a bottom layer (carbon-containing layer) 402, an intermediate layer (silicon-containing layer) 502, and a resist layer that is patterned by the first lithography process to provide a patterned resist layer 602”. The multi-layer patterning stack 604 is substantially similar to that discussed above, including providing a carbon-containing layer 402 (e.g., a-C) deposited by at least one of a CVD, ALD or PVD process. In one embodiment, a silicon-containing layer 502 (e.g., a-Si) is deposited by at least one of a CVD, PVD or ALD process. In one embodiment, the patterned resist layer 602” is formed by an EUV process. In other embodiments, other lithography techniques can be implemented.

[0087] FIG. 21A and FIG. 21B A second lithography process is shown that includes forming a multi-layer patterning stack 604” over the patterned resist layer 602”. The multi-layer patterning stack 604” includes a bottom layer (carbon-containing layer) 402, an intermediate layer (silicon-containing layer) 502, and a resist layer that is patterned by the second lithography process to provide a patterned resist layer 602”’. The multi-layer patterning stack 604” is substantially similar to that discussed above, including providing a carbon-containing layer 402 (e.g., a-C) deposited by at least one of a CVD, ALD or PVD process. In one embodiment, a silicon-containing layer 502 (e.g., a-Si) is deposited by at least one of a CVD, PVD or ALD process. In one embodiment, the patterned resist layer 602”’ is formed by an EUV process. In other embodiments, other lithography techniques can be implemented. FIG. 20A and FIG. 20BThe device 1800 is patterned after an etching process. The etching process patterns the mandrel layer 1912 to form a patterned mandrel layer 1912'. The multilayer patterned layer 604 is used as a masking element during etching to form the patterned mandrel layer 1912'. The multilayer patterned layer 604 can be removed after the etching process.

[0088] Now for reference FIG. 22 Then, a second photolithography process is performed. The second photolithography process can define the portion of the metallized wiring layout that includes the first group of metallized lines. FIG. 22 A second photolithography process is illustrated, which includes forming another multilayer patterned stack 604 on top of the mandrel layer 1912. The multilayer patterned stack 604 includes a bottom layer (carbon-containing layer) 402, an intermediate layer (silicon-containing layer) 502, and a resist layer patterned by the second photolithography process to provide a patterned resist layer 602”'. The multilayer patterned stack 604 is substantially similar to those discussed above, including providing a carbon-containing layer 402 and / or a silicon-containing layer 502 deposited by at least one of CVD, ALD, or PVD processes. The multilayer patterned stack 604 is formed on a feature of morphological variation (patterned mandrel layer 1912'). In one embodiment, the carbon-containing layer 402 is directly in contact with the patterned mandrel layer 1912'. In another embodiment, the amorphous carbon component of the carbon-containing layer 402 is directly in contact with the patterned mandrel layer 1912'. In one embodiment, the patterned resist layer 602”' is formed by an EUV process. In other embodiments, other photolithography techniques may be implemented.

[0089] FIG. 23A and FIG. 23B It shows that in providing FIG. 22 The patterned device 1800 is patterned after an etching process. The etching process patterns the mandrel layer 1912' to form a patterned mandrel layer 1912. FIG. 22 The multi-layer patterned layer 604 is used as a masking element during etching to form the patterned mandrel layer 1912. The multi-layer patterned layer 604 can be removed after the etching process.

[0090] Now for reference FIG. 24A and FIG. 24B A conformal spacer material layer 2402 is formed on a semiconductor structure 202 including a mandrel 1912". The spacer material layer 2402 may include a dielectric material, such as titanium nitride, silicon nitride, silicon oxide, titanium oxide, and / or other suitable materials. The spacer material layer 2402 may be formed by various processes, including deposition processes performed by CVD or PVD processes.

[0091] Now for reference FIG. 25A and FIG. 25B Etching back FIG. 24A andFIG. 24B A conformal spacer material layer 2402 is etched to form spacer elements 2502. The etching process can be an anisotropic etching process, such as an anisotropic etching process by plasma etching. The width of the spacer "s" can be reduced so that it is below the resolution of the lithography technology applied.

[0092] Referring now to FIG. 26A and FIG. 26B a third lithography process is performed. The third lithography process can define a portion of the metallization layout that includes a second set of metallization lines. FIG. 26A and FIG. 26B shows the third lithography process, which includes forming another multi-layer patterned stack 604 over the patterned mandrel layer 1912" and the spacer elements 2502. The multi-layer patterned stack 604 includes a bottom layer (carbon-containing layer) 402, an intermediate layer (silicon-containing layer) 502, and a resist layer that is patterned by the second lithography process to provide a patterned resist layer 602"". The multi-layer patterned stack 604 is substantially similar to that discussed above, including providing a carbon-containing layer 402 and / or a silicon-containing layer 502 deposited by at least one of a CVD, ALD, or PVD process. The multi-layer patterned stack 604 is formed over the topographically varying features (patterned mandrel layer 1912" and spacer elements 2502). In one implementation, the carbon-containing layer 402 directly interfaces with each of the patterned mandrel layer 1912" and the spacer elements 2502. In another implementation, the amorphous carbon component of the carbon-containing layer 402 directly interfaces with each of the patterned mandrel layer 1912" and the spacer elements 2502. In one implementation, the patterned resist layer 602"" is formed by an EUV process. In other implementations, other lithography techniques can be implemented.

[0093] FIG. 27A and FIG. 27B shows the device 1800 after an etching process that provides a pattern of FIG. 26A and FIG. 26B the previously formed patterned mandrel layer 1912". Specifically, the resist 602"" provides openings at which certain portions of the patterned mandrel layer 1912" are removed (e.g., portions between the spacer elements 2502 at the center of the illustrated portion of the device 1800). Thereafter, the masking layer 1910 can be etched according to the pattern provided by the mandrel and spacer elements (i.e., the sum of the first lithography process, the second lithography process, and the third lithography process), thereby providing a patterned masking layer 1910'. The patterned masking layer 1910' includes patterning the hard mask layer 1910B. After patterning to form the patterned masking layer 1910', the overlying layers can be removed.

[0094] FIG. 28Aand FIG. 28B A subsequent step is shown that provides a pattern of trench and via openings in the target ILD layer 1908 according to the pattern of the masking layer 1910', thereby providing a patterned target ILD layer 1908'. The trench and via openings 2802 define the routing of the metallization layers and / or vias in the layers of the MLI structure of the device 1800. Accordingly, the trench and via openings 2802 are subsequently filled with a conductive material to provide FIG. 29A and FIG. 29B interconnects 2902. The interconnects 2902 can include copper, aluminum, alloys, and / or other suitable conductive materials. The interconnects 2902 can include a multi-layer structure including barrier layers, seed layers, and liner layers, among others. Exemplary barrier layers include titanium, titanium nitride, tantalum, tantalum nitride, or other alternatives. Following deposition of the conductive material, various processes such as planarization processes (e.g., CMP) can be formed.

[0095] Accordingly, FIG. 19 to FIG. 29B The series provides exemplary embodiments of the method 100. As shown, the method 100 can be implemented multiple times to pattern a single target layer. In some embodiments, the properties of the multi-layer patterning stack 604 can provide improvements in pattern quality. For example, LWR and / or LCDU can be improved for the patterned carbon-containing layer (in some embodiments, the patterned silicon-containing layer), which allows for improved fidelity of the reproduction of the pattern in the underlying target layer. While not wishing to be bound by any theory, it can be believed that the deposition processes and / or material compositions of the multi-layer patterning stack are capable of providing material properties that allow for improved performance in the patterning process, for example, increased density, hardness, desired modulus, or high etch selectivity.

[0096] FIG. 30 A manufacturing tool 3000 is shown that can be used to perform one or more of the steps of the methods discussed herein. In one embodiment, the manufacturing tool 3000 is a chemical vapor deposition tool. In one embodiment, the manufacturing tool 3000 is an atomic layer deposition tool. In one embodiment, the manufacturing tool 3000 is a physical vapor deposition tool. In particular, the manufacturing tool 3000 can be used to deposit a carbon-containing layer, as described above. In some embodiments, the manufacturing tool 300 can also be used to deposit a silicon-containing layer. Between an upper cathode and a lower cathode, a semiconductor structure such as the semiconductor structure 202 is provided. The semiconductor structure 202 can be in the form of a wafer. The upper electrode is provided with RF power. Heat, pressure, and / or power or plasma applied to the chamber 3002 can aid in the reaction of the precursor gas. The reaction produces a layer on the structure 202. As described above, in some embodiments, the layer is an amorphous carbon layer.

[0097] FIG. 30An exemplary precursor including ethyne for forming a carbon-containing layer is shown. The precursor enters the reaction chamber and dissociates into carbon and hydrogen, which are then deposited or outgassed from the reaction chamber 3002.

[0098] In one exemplary aspect, the disclosure relates to a method for lithographic patterning, the method comprising providing a substrate, forming a target layer over the substrate, and forming a pattern layer. Forming the pattern layer comprises depositing a first layer having a composition comprising at least 50 atomic percent carbon, depositing a second layer comprising silicon, and depositing a photo-sensitive layer over the second layer.

[0099] In another embodiment, the target layer is an interlayer dielectric (ILD) layer formed over the substrate. In some implementations, patterning the photo-sensitive layer defines a metallization layer to be formed in the ILD layer. In one embodiment, depositing the first layer is performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In one embodiment, the photo-sensitive layer is deposited by spin coating. In one embodiment, depositing the first layer comprises forming an amorphous carbon layer. In some embodiments, depositing the composition comprises depositing carbon and hydrogen by at least one of CVD, ALD, or PVD. In one embodiment, depositing the second layer comprising silicon comprises depositing spin-on glass. In another embodiment, depositing the second layer comprises depositing amorphous silicon. In yet another embodiment, the amorphous silicon is deposited by at least one of atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). In one embodiment, the method further comprises depositing an adhesion layer between the second layer and the photo-sensitive layer.

[0100] In another exemplary aspect, the disclosure relates to a method for lithographic patterning. The method comprises providing a target layer, and depositing a carbon-containing layer over the target layer using a deposition process that provides a precursor that is transported toward a surface, and chemically modifying the precursor to obtain the carbon-containing layer on the surface. The carbon-containing layer has at least 50% carbon. A silicon-containing layer is formed on the carbon-containing layer. A resist layer is formed over the silicon-containing layer. A portion of the resist layer is exposed to radiation to provide a patterned resist layer; a portion of the silicon-containing layer not covered by the patterned resist layer is etched to form a patterned silicon-containing layer; after etching the portion of the silicon-containing layer, a portion of the carbon-containing layer not covered by the patterned silicon-containing layer is etched to form a patterned carbon-containing layer. The patterned carbon-containing layer is used to define a pattern in the target layer.

[0101] In one embodiment, the deposition process is chemical vapor deposition (CVD) or physical vapor deposition. In one embodiment, the method further comprises trimming the patterned carbon-containing layer prior to using the patterned carbon-containing layer to define the pattern. In one embodiment, the deposition process is atomic layer deposition (ALD).

[0102] In another example aspect, the disclosure relates to a method of patterning a semiconductor device. The method includes depositing an amorphous carbon layer over a substrate; directly depositing a silicon-containing layer on the amorphous carbon layer; and spin-coating a photo-sensitive layer over the silicon-containing layer. The method continues with patterning the photo-sensitive layer using a lithography process (e.g., EUV) to provide a first opening. The silicon-containing layer is etched through the first opening; the etched silicon-containing layer is used as a masking element during etching the deposited amorphous carbon layer.

[0103] In one embodiment, the method includes depositing a silicon-containing layer that includes forming amorphous silicon. In another embodiment, depositing the amorphous carbon layer includes chemical vapor deposition, atomic layer deposition, or physical vapor deposition. In one embodiment, the etched amorphous carbon layer is used as a masking element to pattern a hard mask layer beneath the amorphous carbon layer. In another embodiment, the patterned hard mask layer is used to define a trench in an interlayer dielectric layer on the substrate.

[0104] The foregoing summary of some embodiments has been presented with the purpose of providing those of ordinary skill in the art with a better understanding of the various aspects of the disclosure. Those of ordinary skill in the art will realize that, in light of the disclosure, they can readily apply the disclosed concepts to design or modify other processes and structures for performing the same functions and / or achieving the same advantages of the embodiments presented herein. Those of ordinary skill in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.

[0105] Example 1 is a method for lithographic patterning, comprising: providing a substrate; forming a target layer over the substrate; and forming a patterning layer, wherein forming the patterning layer comprises: depositing a first layer having a composition that includes at least 50 atomic percent carbon; depositing a second layer that includes silicon; and depositing a photo-sensitive layer on the second layer.

[0106] Example 2 is the method of Example 1, wherein the target layer is an interlayer dielectric (ILD) layer formed over the substrate.

[0107] Example 3 is the method of Example 2, further comprising: patterning the photo-sensitive layer, wherein the patterning defines a metallization layer to be formed in the ILD layer.

[0108] Example 4 is the method of Example 1, wherein depositing the first layer is performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0109] Example 5 is the method of Example 4, wherein depositing the photo-sensitive layer is performed by spin-coating.

[0110] Example 6 is the method of example 1, wherein depositing the first layer having the composition comprises forming an amorphous carbon layer.

[0111] Example 7 is the method of example 1, wherein depositing the composition comprises depositing carbon and hydrogen by at least one of CVD, ALD, or PVD.

[0112] Example 8 is the method of example 1, wherein depositing the second layer comprising silicon comprises depositing spin-on glass.

[0113] Example 9 is the method of example 1, wherein depositing the second layer comprising silicon comprises depositing amorphous silicon.

[0114] Example 10 is the method of example 9, wherein the amorphous silicon is deposited by at least one of atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD).

[0115] Example 11 is the method of example 1, further comprising depositing an adhesion layer between the second layer and the photoactive layer.

[0116] Example 12 is a method for lithographic patterning, comprising: providing a target layer; depositing a carbon-containing layer over the target layer using a deposition process that provides a precursor that is transported toward a surface and chemically modifies the precursor to obtain the carbon-containing layer on the surface, wherein the carbon-containing layer has at least 50% carbon; forming a silicon-containing layer on the carbon-containing layer; forming a resist layer over the silicon-containing layer; exposing a portion of the resist layer to radiation to provide a patterned resist layer; etching a portion of the silicon-containing layer that is not covered by the patterned resist layer to form a patterned silicon-containing layer; after etching the portion of the silicon-containing layer, etching a portion of the carbon-containing layer that is not covered by the patterned silicon-containing layer to form a patterned carbon-containing layer; and using the patterned carbon-containing layer to define a pattern in the target layer.

[0117] Example 13 is the method of example 12, wherein the deposition process is chemical vapor deposition (CVD) or physical vapor deposition.

[0118] Example 14 is the method of example 12, further comprising trimming the patterned carbon-containing layer prior to using the patterned carbon-containing layer to define the pattern.

[0119] Example 15 is the method of example 12, wherein the deposition process is atomic layer deposition (ALD).

[0120] Example 16 is a method of patterning a semiconductor device, the method comprising: depositing an amorphous carbon layer over a substrate; depositing a silicon-containing layer directly on the amorphous carbon layer; spin-coating a photo-sensitive layer over the silicon-containing layer; and using a photolithography process, patterning the photo-sensitive layer to provide a first opening; etching the silicon-containing layer through the first opening; using the etched silicon-containing layer as a masking element during etching of the deposited amorphous carbon layer.

[0121] Example 17 is the method of example 16, wherein depositing the silicon-containing layer comprises forming amorphous silicon.

[0122] Example 18 is the method of example 17, wherein depositing the amorphous carbon layer comprises: chemical vapor deposition, atomic layer deposition, or physical vapor deposition.

[0123] Example 19 is the method of example 16, further comprising: using the etched amorphous carbon layer to pattern a hard mask layer beneath the amorphous carbon layer.

[0124] Example 20 is the method of example 19, further comprising: using the patterned hard mask layer to define a trench in an interlayer dielectric layer on the substrate.

Claims

1. A method for photolithographic patterning, comprising: Provide substrate; A target layer is formed on the substrate; A mask layer is formed on the target layer, wherein the mask layer includes a first dielectric layer, a second dielectric layer, and a hard mask layer located between the first dielectric layer and the second dielectric layer; and A patterned layer is formed on the mask layer, wherein forming the patterned layer includes: The first layer is deposited with a composition comprising at least 50 atomic percent carbon; The deposition includes a second layer of silicon; A photosensitive layer is deposited on the second layer; Patterning the photosensitive layer, the second layer, and the first layer to form a patterned first layer and a patterned second layer; and Trim the patterned first layer and the patterned second layer to reduce their widths.

2. The method according to claim 1, wherein, The target layer is an interlayer dielectric (ILD) layer formed on the substrate.

3. The method according to claim 2, wherein, The patterning defines the metallization layer to be formed in the ILD layer.

4. The method according to claim 1, wherein, The deposition of the first layer is performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

5. The method according to claim 4, wherein, The deposition of the photosensitive layer is performed by spin coating.

6. The method according to claim 1, wherein, Depositing the first layer having the components includes forming an amorphous carbon layer.

7. The method according to claim 1, wherein, Depositing the components includes depositing carbon and hydrogen by at least one of CVD, ALD, or PVD.

8. The method according to claim 1, wherein, The deposition of the second layer, which includes silicon, includes: depositing spin-coated glass.

9. The method according to claim 1, wherein, The deposition of the second layer, which includes silicon, includes: depositing amorphous silicon.

10. The method according to claim 9, wherein, The amorphous silicon is deposited by at least one of atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD).

11. The method according to claim 1, further comprising: An adhesion layer is deposited between the second layer and the photosensitive layer.

12. A method for photolithographic patterning, comprising: Provide the target layer; A mask layer is formed on the target layer, wherein the mask layer includes a first dielectric layer, a second dielectric layer, and a hard mask layer located between the first dielectric layer and the second dielectric layer; A carbon-containing layer is deposited on the mask layer using a deposition process, wherein the deposition process provides a precursor that is delivered toward a surface and the precursor is chemically modified to obtain the carbon-containing layer on the surface, wherein the carbon-containing layer has at least 50% carbon. A silicon-containing layer is formed on the carbon-containing layer; A photoresist layer is formed on the silicon-containing layer; A portion of the resist layer is exposed to radiation to provide a patterned resist layer; The portion of the silicon-containing layer not covered by the patterned resist layer is etched to form a patterned silicon-containing layer; After etching the portion of the silicon-containing layer, the portion of the carbon-containing layer not covered by the patterned silicon-containing layer is etched to form a patterned carbon-containing layer; and The patterned carbon-containing layer is used to define the pattern in the target layer. The method further includes: Before using the patterned carbon-containing layer to define the pattern, the patterned silicon-containing layer and the patterned carbon-containing layer are trimmed to reduce their widths.

13. The method according to claim 12, wherein, The deposition process is chemical vapor deposition (CVD) or physical vapor deposition (PVD).

14. The method according to claim 12, wherein, The deposition process is atomic layer deposition (ALD).

15. A method for patterning a semiconductor device, the method comprising: An interlayer dielectric layer is formed on the substrate; A mask layer is formed on the interlayer dielectric layer, wherein the mask layer includes a first dielectric layer, a second dielectric layer, and a hard mask layer located between the first dielectric layer and the second dielectric layer; An amorphous carbon layer is deposited on the mask layer; A silicon-containing layer is directly deposited on the amorphous carbon layer; A photosensitive layer is spin-coated onto the silicon-containing layer; and The photosensitive layer is patterned using a photolithography process to provide a first opening; The silicon-containing layer is etched through the first opening to form an etched silicon-containing layer; During the etching process of the deposited amorphous carbon layer, an etched silicon-containing layer is used as a masking element to form the etched amorphous carbon layer. Trim the etched silicon-containing layer and the etched amorphous carbon layer to reduce the width of the etched silicon-containing layer and the etched amorphous carbon layer.

16. The method according to claim 15, wherein, Depositing the silicon-containing layer includes forming amorphous silicon.

17. The method according to claim 16, wherein, The deposition of the amorphous carbon layer includes chemical vapor deposition, atomic layer deposition, or physical vapor deposition.

18. The method of claim 15, further comprising: An etched amorphous carbon layer is used to pattern the hard mask layer beneath the amorphous carbon layer.

19. The method of claim 18, further comprising: A patterned hard mask layer is used to define trenches in the interlayer dielectric layer on the substrate.

Images