Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to semiconductor structures and methods of forming the same. One method includes forming a first mandrel and a second mandrel over a dielectric layer, and forming a first spacer and a second spacer on the first mandrel and the second mandrel, respectively. The first spacer and the second spacer are adjacent to each other and have a space between the first spacer and the second spacer. The dielectric layer is etched to form an opening in the dielectric layer, where the opening overlaps the space, and where the first spacer and the second spacer function as part of an etch mask in the etching. A conductive material is filled into the opening. A planarization process is performed on the conductive material.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices, and more particularly to semiconductor structures and methods of forming the same. BACKGROUND

[0002] Metal lines and vias are used to interconnect integrated circuits (e.g., transistors) to form functional circuits. As device sizes decrease, metal lines and vias also become smaller and smaller. Formation of metal lines and vias can require formation of a metal hard mask layer for defining the size and location of the metal lines and / or vias. However, the metal hard mask layer can sometimes be damaged, resulting in defects in the metal lines and / or vias. SUMMARY

[0003] According to one aspect of the present disclosure, a method of forming a semiconductor structure is provided, comprising: forming a first mandrel and a second mandrel over a dielectric layer; forming a first spacer and a second spacer on the first mandrel and the second mandrel, respectively, wherein the first spacer and the second spacer are adjacent to each other and have a first space therebetween; etching the dielectric layer to form an opening in the dielectric layer, wherein the opening overlaps the first space, and wherein the first spacer and the second spacer function as part of an etch mask in the etching; filling a conductive material into the opening; and performing a planarization process on the conductive material.

[0004] According to one aspect of the present disclosure, a method of forming a semiconductor structure is provided, comprising: forming a mandrel over a dielectric layer; forming a first spacer on a sidewall of the mandrel, wherein the first spacer comprises a first sidewall and a second sidewall opposite to each other, wherein the second sidewall contacts the mandrel; etching a first portion of the dielectric layer to form a first opening in the dielectric layer, wherein the first opening has a third sidewall vertically aligned with the first sidewall; filling the first opening with a first conductive material; etching a second portion of the dielectric layer to form a second opening in the dielectric layer, wherein the second opening has a fourth sidewall vertically aligned with the second sidewall, and wherein the first opening and the second opening are located on opposite sides of the mandrel; and filling the second opening with a second conductive material.

[0005] According to one aspect of the disclosure, a method of forming a semiconductor structure is provided, comprising: forming a hard mask over a low-k dielectric layer; forming a plurality of mandrels over the hard mask; forming a plurality of spacers on sidewalls of the plurality of mandrels, wherein first, second, and third spaces separate adjacent spacers of the plurality of spacers, wherein portions of the hard mask are exposed to the first, second, and third spaces; forming a protective layer filled into the first spaces; patterning the protective layer to remove the protective layer from the second and third spaces; forming a patterned etch mask over the protective layer; in a first etch process, etching through first portions of the hard mask and first portions of the low-k dielectric layer directly under the second spaces to form first openings in the low-k dielectric layer, wherein the protective layer and the patterned etch mask are used in combination as an etch mask; and in a second etch process, etching through second portions of the hard mask and second portions of the low-k dielectric layer directly under the third spaces to form second openings in the low-k dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the disclosure can be best understood from the following detailed description when read with the accompanying drawings. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1-3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figures 8-18 , Figure 19A , Figure 19B and Figure 20 show cross-sectional and top views of intermediate stages of forming an interconnect structure including metal lines and vias, according to some embodiments.

[0008] Figure 21 shows a process flow for forming an interconnect structure, according to some embodiments. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature and the second feature are formed in direct contact with each other, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. In addition, the present disclosure can repeat certain

[0010] In addition, spatially relative terms (e.g., "beneath," "below," "lower," "above," "upper," and the like) can be used herein for ease of describing one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can be interpreted accordingly.

[0011] An interconnect structure including metal lines and vias and a method of forming the same are provided. According to some embodiments of the present disclosure, a mandrel is formed, and spacers are formed on the sidewalls of the mandrel. The spaces between the spacers can be used in a first patterning process (of a dual patterning process) to form first metal lines and vias. In addition, the spaces occupied by the mandrel can be used in a second patterning process of the dual patterning process to form second metal lines and vias. The spacers, which are used as part of the etch mask in the dual patterning process, can be formed tall without increasing the lateral dimension, and thus effectively used as the etch mask. Embodiments discussed herein will provide examples to enable making or using the subject matter of the present disclosure, and one of ordinary skill in the art will readily understand modifications that can be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, like reference numerals are used to designate like elements. Although method embodiments can be discussed as being performed in a particular order, other method embodiments can be performed in any logical order.

[0012] Figures 1-3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B ,Figure 7C 、 Figures 8-10 、 Figure 3 、 Figure 21 and Figure 4A shows a cross-sectional view of an intermediate stage of forming an interconnect structure according to some embodiments of the present disclosure. The corresponding process is also reflected schematically in process flow 200, as shown in Figure 21 .

[0013] Figure 4B shows a cross-sectional view of a wafer 10, where the portion shown is a portion of a device chip in wafer 10. According to some embodiments of the present disclosure, wafer 10 is a device wafer that includes active devices (e.g., transistors and / or diodes) and possibly passive devices (e.g., capacitors, inductors, resistors, etc.).

[0014] According to some embodiments of the present disclosure, wafer 10 includes a semiconductor substrate 12 and features formed at a top surface of semiconductor substrate 12. Semiconductor substrate 12 can be formed of a crystalline semiconductor material, such as silicon, germanium, silicon germanium, and / or a III-V compound semiconductor, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. Semiconductor substrate 12 can also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) can be formed in semiconductor substrate 12 to isolate active regions in semiconductor substrate 12. Although not shown, vias can be formed to extend into semiconductor substrate 12, where the vias are used to electrically couple features on opposite sides of semiconductor substrate 12 to one another. Active devices 14 (which can include transistors) are formed at the top surface of semiconductor substrate 12.

[0015] Dielectric layer 16 is further shown in Figure 4A . According to some embodiments of the present disclosure, dielectric layer 16 is formed of a low-k dielectric material having a dielectric constant (k-value) of less than about 3.5, less than about 3.0, or even lower. Dielectric layer 16 can be formed of black diamond (a registered trademark of Applied Materials, Inc.), carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments of the present disclosure, formation of dielectric layer 16 includes depositing a dielectric material that contains a porogen, and then performing a curing process to drive out the porogen, so that the remaining IMD layer 16 is porous.

[0016] Conductive features 22A and 22B are formed in IMD 16. According to some embodiments, each of conductive features 22A and 22B includes a diffusion barrier layer and a copper-containing material over the diffusion barrier layer. The diffusion barrier layer can be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc., and has a function of preventing copper in the copper-containing material from diffusing into IMD 16. Alternatively, conductive features 22A and 22B can be barrier-free, and can be formed of cobalt, tungsten, etc. Conductive features 22A and 22B can have a single damascene structure or a dual damascene structure.

[0017] According to some embodiments, dielectric layer 16 is an intermetallic dielectric (IMD) layer, and conductive features 22A and 22B are metal lines and / or vias. According to alternative embodiments, dielectric layer 16 is an interlayer dielectric layer, and conductive features 22A and 22B are contact plugs. There can or can not be additional features between dielectric layer 16 and device 14, and the additional features are denoted as structure 15, which can include dielectric layers such as a contact etch stop layer, an interlayer dielectric, an etch stop layer, and an IMD. Structure 15 can also include contact plugs, vias, metal lines, etc.

[0018] Dielectric layer 24 is deposited over dielectric layer 16 and conductive lines 22A and 22B. Dielectric layer 24 can function as an etch stop layer (ESL), and is therefore referred to as an etch stop layer or ESL 24 throughout the specification. ESL 24 can include a nitride, a silicon-carbon based material, a carbon-doped oxide, or a metal-containing dielectric (e.g., SiCN, SiOCN, SiOC, AIO x , AlN, AlCN, etc.), or a combination thereof. ESL 24 can be a single layer formed of a homogenous material, or a composite layer including multiple dielectric sub-layers. According to some embodiments of the present disclosure, ESL 24 includes an aluminum nitride (AlN) layer, a SiOC layer over the AlN layer, and an aluminum oxide (AIO x ) layer over the SiOC layer.

[0019] Dielectric layer 26 is deposited over ESL 24. According to some exemplary embodiments of the present disclosure, dielectric layer 26 is formed of a silicon-containing dielectric material (e.g., silicon oxide). Dielectric layer 26 can also be formed of a low-k dielectric material, and is therefore referred to as low-k dielectric layer 26 hereinafter. Low-k dielectric layer 26 can be formed using a material selected from the same set of candidate materials used to form dielectric layer 16. When selected from the same set of candidate materials, the materials of dielectric layers 16 and 26 can be the same as or different from each other.

[0020] A mask layer 28 is formed over the dielectric layer 26. According to some embodiments of the present disclosure, the mask layer 28 is a single layer mask, which can be formed of or include silicon oxide, silicon nitride, a metal-containing oxide (e.g., titanium oxide), or a metal-containing nitride (e.g., titanium nitride). Alternatively, the mask layer 28 has a composite structure including multiple sub-layers, which can be formed of the materials described above. The mask layer 28 can be formed using plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like.

[0021] A plurality of mandrels 30 is formed over the mask layer 28. In the process flow 200 as shown, the corresponding process is shown as process 202. According to some embodiments, the mandrels 30 are formed as a plurality of parallel strips, for example, as shown in the top view as shown in Figure 4A Figure 4B The mandrels 30 can be formed of or include amorphous silicon, amorphous carbon, tin oxide, or the like. According to some embodiments, the width Wl of the mandrels 30 is in a range between about 5 nm to about 20 nm. The spacing SI between adjacent mandrels 30 can be about 2.5 times to about 4 times the width Wl. According to some embodiments, the height HI of the mandrels 30 can be in a range between about 10 nm to about 40 nm, and can be in a range between about 25 nm to about 40 nm. The formation of the mandrels 30 can include depositing a blanket layer (which can be a planar layer having a uniform thickness), and then performing an etching process to pattern the blanket layer and form the mandrels 30.

[0022] Referring to Figure 4B , the spacers 32 are formed. In the process flow 200 as shown, the corresponding process is shown as process 204. According to some embodiments, the spacers 32 are formed as a plurality of parallel strips, for example, as shown in the top view as shown in Figure 4A ​In the illustrated process flow 200, the corresponding process is shown as process 204. According to some embodiments, the spacers 32 are formed of or include a metal-containing material such as a metal oxide or a metal nitride (e.g., titanium oxide, titanium nitride, etc.). The width W2 of the spacers 32 can be in a range of about 5 nm to about 20 nm. The height H2 of the spacers 32 is equal to or slightly less than (e.g., between about 80% to 100%) the height H1 of the mandrels 30. The height H2 can be in a range of about 20 nm to about 40 nm, and can be in a range of about 25 nm to about 40 nm. The height H2 is further greater than the width W2 of the spacers 32, and can be about 1.5 times or 2 times greater than the width W2. The formation process of the spacers 32 can include performing a conformal deposition process to form a conformal spacer layer including vertical portions on the mandrel 30 sidewalls, a top horizontal portion on the mandrel 30 top, and a bottom horizontal portion between the vertical portions. An anisotropic etch process is then performed to remove the top and bottom horizontal portions and leave the vertical portions (which are the spacers 32). According to some embodiments, the anisotropic etch process is performed using an etch gas such as Cl2, HBr, CH4, etc., or a combination thereof. A carrier gas such as N2, argon, etc., can also be added to the etch gas. There is a space 34 between the spacers 32 formed on adjacent mandrels 30, which can have a spacing S2 in a range of about 0.5W1 to about 1.5W2.

[0023] Figure 5A , Figure 21 , Figure 7A , Figure 5B , Figure 5A , Figure 5A , Figure 5B , Figure 5B , Figure 5A , Figure 6A and Figure 6B shows the formation of first vias and metal lines in the dielectric layer 26 according to some embodiments. The corresponding process can also be referred to as a first patterning process in a dual patterning process. Figure 7A shows the formation of the protective layer 36. In as Figure 7BIn the illustrated process flow 200, the corresponding process is shown as process 206. According to some embodiments, the protective layer 36 is formed of a material that is not etched during the subsequent etching of the dielectric layer 26. Furthermore, the protective layer 36 is formed of a material different from both the mandrel 30 and the spacer 32, such that the mandrel 30 and the spacer 32 are not damaged during patterning of the protective layer 36. According to some embodiments, the protective layer 36 may (or may not) be formed of a material selected from the same group of candidate materials used to form the spacer 32. According to some embodiments, the protective layer 36 is formed of or contains titanium oxide, titanium nitride, silicon oxide, etc. The formation of the protective layer 36 includes depositing a blanket layer, and then performing an etching process to pattern and remove unwanted portions of the protective layer 36. The etching process can be performed using gases including O2, CO2, NH3, etc. The photolithography process for patterning can be performed using, for example, extreme ultraviolet (EUV) light with a wavelength of 193 nm.

[0024] refer to Figure 7C This can form a three-layer etch mask 38. In, for example... Figure 8 In the illustrated process flow 200, the corresponding process is shown as process 208. The etching mask 38 may include a bottom layer (sometimes also called the lower layer) 38BL, an intermediate layer 38ML above the bottom layer 38BL, and a top layer (sometimes also called the upper layer) 38TL above the intermediate layer 38ML. According to some embodiments, the bottom layer 38BL and the top layer 38TL are formed of a photoresist, wherein the bottom layer 38BL is cross-linked. The intermediate layer 38ML may be formed of an inorganic material, which may be a nitride (e.g., silicon nitride), an oxide oxynitride (e.g., silicon oxynitride), an oxide (e.g., silicon oxide), etc. The intermediate layer 38ML has high etch selectivity relative to the top layer 38TL and the bottom layer 38BL, therefore the top layer 38TL can be used as an etching mask for patterning the intermediate layer 38ML, and the intermediate layer 38ML can be used as an etching mask for patterning the bottom layer 38BL. The top layer 38TL is patterned to form an opening 40, which defines a via opening in the low-k dielectric layer 26. The patterning process can be performed using, for example, EUV light with a wavelength of 193 nm.

[0025] Figure 6A It shows Figure 21 Top view of the structure shown. Figure 6B The cross-sectional view shown is taken from Figure 6A Reference section AA in the diagram. For example... Figure 6A As shown, an etching mask 38 is formed over the entire illustrated area of ​​wafer 10, and an opening 40 is formed in the etching mask 38. The opening 40 extends through spaces 34, where each space 34 is located between two adjacent spacers 32.

[0026] Next, the patterned top layer 38TL is used as an etch mask to etch the middle layer 38ML Figure 6B ), so that the openings 40 extend into the middle layer 38ML. After etching through the middle layer 38ML, the bottom layer 38BL is further patterned, during which the middle layer 38ML serves as an etch mask. During patterning of the bottom layer 38BL, the top layer 38TL is consumed. The middle layer 38ML can be partially or completely consumed during patterning of the bottom layer 38BL. Upon patterning of the bottom layer 38BL, the openings 40 extend downward, exposing the mandrel 30 and spacers 32. The resulting structure is shown in Figure 6B . Depending on the size of the openings 40 and the severity of overlay shifts, the protective layer 36 can or can not be exposed.

[0027] The etching process continues to etch the hard mask 28 so as to form via openings 42 in the hard mask 28. In the process flow 200 shown in Figure 6B , the corresponding process is shown as process 210. The dielectric layer 26 is then etched so that the via openings 42 extend into (and possibly through) the low-k dielectric layer 26. According to some embodiments, the etching of the dielectric layer 26 is performed using an etching gas selected from the group consisting of C4F6, C4F8, C5F8, CF4, CHF3, CH2F2, NF3, N2, O2, Ar, He, and combinations thereof. According to some embodiments, the via openings 42 extend to the bottom of the dielectric layer 26 and expose the etch stop layer 24. Next, the etch stop layer 24 is removed in an etching process, which can be a dry etching process or a wet etching process. The conductive features 22A are thereby exposed to the via openings 40. It should be understood that the protective layer 36 has the function of protecting undesired portions of the dielectric layer 26 from etching. For example, if there is an overlay shift, and the openings 40 are shifted to the left and overlap the space 34 between the second and third spacers 32 (counting from the left), then without the formation of the protective layer 36, it can be that the portion of the dielectric layer 26 under the space 34 is undesirably etched. Thus, when an overlay shift occurs, the protective layer 36 protects the undesired portion of the dielectric layer 26 from being etched.

[0028] According to alternative embodiments, the formation of the via openings 42 is stopped when the bottom of the via openings 42 is at an intermediate level between the top and bottom surfaces of the dielectric layer 26, rather than forming via openings 42 that extend to the conductive features 22A, where the dashed line 43 illustrates the intermediate level. According to these embodiments, upon subsequent formation of trenches, the via openings 42 will extend downward, the process of which is shown in Figure 6A .

[0029] Figure 7A A top view of the structure shown in Figure 6A is shown.Figure 7A The cross-sectional view shown is taken from the reference cross-section A-A in Figure 6B For ease of differentiation, the width of the openings 42 (measured in the Y direction) is shown as slightly less than the width of the corresponding openings 40, although the width of the openings 42 can actually be equal to the width of the corresponding openings 40. As Figure 21 shown, according to some embodiments, the spacers 32 define the size of the openings 42 in the X direction, while the openings 40 in the etch mask 38 define the size of the openings 42 in the Y direction. After forming the openings 42, the bottom layer 38BL Figure 7C ) is removed, for example, using a process gas containing CO2, NH3, O2, or a combination thereof.

[0030] Figure 7C , Figure 7A , Figure 7B , Figure 5A , Figure 5A and Figure 5A shows a process for forming a first plurality of trenches. Referring to Figure 7B , a second etch mask 46, which can be three layers, is formed, including a bottom layer 46BL, a middle layer 46ML over the bottom layer 46BL, and a top layer 46TL over the middle layer 46ML. In the process flow 200 shown in Figure 7A , the corresponding process is shown as process 212. The materials of the bottom layer 46BL, the middle layer 46ML, and the top layer 46TL can be similar to the materials of the bottom layer 38BL, the middle layer 38ML, and the top layer 38TL, respectively. The top layer 46TL is patterned to form openings 48 for defining one or more trenches in the low-k dielectric layer 26. The photolithography process to pattern the top layer 46TL can be performed using, for example, EUV light having a wavelength of 193 nm.

[0031] Figure 7A is a top view of the structure shown in Figure 7B . The cross-sectional view shown in Figure 7B is taken from the reference cross-section A-A in Figure 8 . As shown, the previously formed via openings 42 are directly below the openings 48. There can be some openings 48 with a single opening 42 below each opening 48. There can also be some other openings 48 with multiple via openings 42 below each opening 48, as shown in Figure 9 Figure 21

[0032] Next, the middle layer 46ML is etched using the patterned top layer 46TL as an etch mask Figure 21 ​​), so that the openings 48 extend into the middle layer 46ML. After etching through the middle layer 46ML, the bottom layer 46BL is patterned, during which the middle layer 46ML serves as an etch mask. During patterning of the bottom layer 46BL, the top layer 46TL is consumed. The middle layer 46ML can be partially or completely consumed during patterning of the bottom layer 46BL. Upon patterning of the bottom layer 46BL, the openings 48 extend downward, exposing the underlying mandrel 30 and spacers 32. Depending on the size of the openings 48 and the severity of the overlay misregistration, the protective layer 36 can or can not be exposed. The resulting structure is shown in Figure 10 It is understood that the protective layer 36 can protect undesired portions of the dielectric layer 26 from being patterned. For example, if there is overlay misregistration, and the openings 48 are shifted to the left and overlap the space 34 between the second and third spacers 32 as shown, then without the protective layer 36 being formed, it can be undesirable to etch portions of the dielectric layer 26 under the space 34. Thus, the protective layer 36 protects undesired portions of the dielectric layer 26 from being etched when the trenches are formed.

[0033] The etching process continues to etch the hard mask 28, where the etched portions are not shown in Figures 11-18 and Figure 11 but can be achieved by Figure 10 Next, the dielectric layer 26 is etched so as to form trenches 50-1 and 50-2 in the hard mask 28, which are referred to individually and collectively as trenches 50. In the process flow 200 as shown in Figure 21 , the corresponding process is shown as process 214. According to some embodiments, the etching of the dielectric layer 26 is performed using an etching gas selected from C4F6, C4F8, C5F8, CF4, CHF3, CH2F2, NF3, N2, O2, Ar, He, and combinations thereof. The trench 50-1 is connected with the via 42, as shown in Figure 12 , the via opening 42 has extended to the conductive feature 22A. According to alternative embodiments, when the process shown in Figure 21 is completed, the bottom of the via opening 42 extends to the conductive feature 22A with a virtual line 43 Figure 13 The trench 52-2 can be connected with another via opening 42 above the via opening 42, as shown in Figure 21 The trenches 50-1 and 50-2 extend to an intermediate level between the top surface and the bottom surface of the dielectric layer 26. According to some embodiments, when the process shown in Figure 4A is completed, the via opening 42 has extended to the conductive feature 22A. According to alternative embodiments, when the process shown in Figure 4B is completed, the bottom of the via opening 42 extends to the conductive feature 22A with a virtual line 43 Figure 14The via opening 42 extends downward during the same etching process used to form trench 50, and stops at the top surface of etch stop layer 24. One or more etching processes can then be performed to etch through etch stop layer 24 and expose conductive feature 22A.

[0034] Figure 21 It shows Figure 14 The top view of the structure shown. Figures 15-17 The cross-sectional view shown is taken from Figure 15 Reference section AA in the diagram. For example... Figure 21 As shown, according to some embodiments, spacer 32 defines the dimensions of trenches 50-1 and 50-2 in the X direction, while opening 48 in the etching mask 46 defines the dimensions of trenches 50-1 and 50-2 in the Y direction. After forming trenches 50-1 and 50-2, the bottom layer 46BL is removed, for example, using a process gas containing CO2, NH3, O2, or a combination thereof. The resulting structure is as follows. Figure 6B As shown.

[0035] Figure 15 The formation of conductive material 54 is shown to fill the via opening 42 and trench 50. In such a way... Figure 15 In the illustrated process flow 200, the corresponding process is shown as process 216. According to some embodiments, a metallic material (e.g., cobalt, tungsten, or combinations thereof) is filled in. This metallic material can be formed using a barrier-free process, wherein no barrier portions are formed, and the metallic material is in physical contact with the conductive feature 22A and the dielectric layer 26. According to alternative embodiments, the conductive material may include the metallic material on the barrier portions and diffusion barrier portions. The barrier portions may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc. The metallic material may be formed of copper or contain copper.

[0036] In subsequent processes, planarization processes such as chemical mechanical polishing (CMP) or mechanical polishing can be performed to remove excess portions of the conductive material 54 and protective layer 36, thereby exposing the mandrel 30. The mandrel 30 and / or spacer 32 can serve as CMP stop layers. Figure 16 In the process flow 200 shown, the corresponding process is illustrated as process 218. The resulting structure is as follows: Figure 21 As shown.

[0037] Figure 7C A second patterning process for forming vias and metal lines is shown. These processes are similar to those shown in the previous figures, except that the vias and metal lines are not formed through the space between the spacers 32, but rather by removing the mandrel 30 to create new space, and the vias and metal lines are formed through the newly created space.

[0038] refer to Figure 14 Remove the mandrel 30 during the etching process. Figure 14 In such Figure 17 In the process flow 200 shown, the corresponding process is illustrated as process 220. Therefore, openings 58 are formed between adjacent spacers 32, thereby exposing the underlying hard mask layer 28. According to some embodiments, all mandrels 30 on wafer 10 are removed. According to an alternative embodiment, some portions of the mandrels 30 are removed, while some portions of the mandrels 30 are not removed. Next, as... Figure 18 As shown, a protective layer 60 is formed and fills some portions of the opening 58. In... Figure 21 In the illustrated process flow 200, the corresponding process is shown as process 222. The protective layer 60 may be formed of or comprise a material similar to that of the protective layer 36, and may be selected from the same group of candidate materials as the group of candidate materials for the protective layer 36. Furthermore, the protective layer 60 may be formed of or comprise a material different from that of the spacers 32 (and mandrel 30, if present) and the hard mask 28, so that the spacers 32 (and mandrel 30) are not damaged during patterning of the protective layer 60. According to some embodiments, the protective layer 60 may (or may not) be formed of or comprise these materials, such as titanium oxide, titanium nitride, silicon oxide, etc. The formation of the protective layer 60 includes depositing a blanket layer, and then performing an etching process to pattern and remove unwanted portions of the protective layer 60. The etching process may be performed using gases including O2, CO2, NH3, etc. The photolithography process for patterning may be performed using, for example, EUV light with a wavelength of 193 nm.

[0039] refer to Figure 19A A third etch mask 62, which can be three layers, is formed. The etch mask 62 may include a bottom layer (sometimes also called the lower layer) 62BL, an intermediate layer 62ML above the bottom layer 62BL, and a top layer (sometimes also called the upper layer) 62TL above the intermediate layer 62ML. In such cases... Figure 21 In the process flow 200 shown, the corresponding process is shown as process 224. The material and structure of the etching mask 62 can be similar to the material and structure of the etching mask 38. Figure 19B The top layer 62TL is patterned to form an opening 64, which defines a via opening in the low-k dielectric layer 26. The photolithography process for patterning can be performed using, for example, EUV light with a wavelength of 193 nm. The top view shape of the opening 64 can be similar to... Figure 19A The top view shape of the opening 40 shown may be rectangular, and this will not be discussed in detail here.

[0040] Next, the middle layer 62ML and the bottom layer 62BL are patterned such that the openings 64 extend into and through the middle layer 62ML and the bottom layer 62BL. Thereby, the spacers 32 are exposed. Depending on the size of the openings 64 and the severity of the overlay misregistration, the protective layers 36 and 60 can or can not be exposed.

[0041] The etching process continues to etch the hard mask 28 so as to form via openings 66 in the hard mask 28, as shown in Figure 20 . In the process flow 200, as shown in Figure 20 , the corresponding process is shown as process 226. The dielectric layer 26 is then etched such that the via openings 66 extend into the dielectric layer 26. According to some embodiments, the etching of the dielectric layer 26 is performed using an etching gas selected from the group consisting of C4F6, C4F8, C5F8, CF4, CHF3, CH2F2, NF3, N2, O2, Ar, He, and combinations thereof. According to some embodiments, the via openings 66 extend to the bottom of the dielectric layer 26 and expose the etch stop layer 24. Next, the etch stop layer 24 is removed in an etching process, which can be a dry etching process or a wet etching process. The conductive features 22B are thereby exposed to the via openings 66. The resulting structure is shown in Figure 2 . During the etching process, the protective layers 36 and 60 can protect undesired portions of the dielectric layer 26 from being patterned if a severe overlay misregistration occurs.

[0042] According to an alternative embodiment, the formation of the via openings 66 is stopped when the bottom of the via openings 66 is at an intermediate level between the top surface and the bottom surface of the dielectric layer 26, rather than forming via openings 66 that extend all the way to the conductive features 22B, where the dashed line 67 illustrates the intermediate level.

[0043] ​ A process of forming a second plurality of trenches is shown. Referring to ​ , a fourth etching mask 70, which can be three layers, is formed. The etching mask 70 can include a bottom layer 70BL, a middle layer 70ML above the bottom layer 70BL, and a top layer 70TL above the middle layer 70ML. In the process flow 200, as shown in ​ , the corresponding process is shown as process 228. The materials of the bottom layer 70BL, the middle layer 70ML, and the top layer 70TL can be similar to the materials of the bottom layer 62BL, the middle layer 62ML, and the top layer 62TL, respectively. The top layer 70TL is patterned to form openings 72 that are used to define the pattern of the trench(es) in the low-k dielectric layer 26. The photolithography process that performs the patterning can be performed using, for example, EUV light having a wavelength of 193 nm. The relationship of the openings 72 and the corresponding via opening(s) 66 is similar to ​As shown, this relationship can be achieved.

[0044] Next, the patterned top layer 70TL was used as an etching mask to etch the middle layer 70ML. ​ This allows the opening 72 to extend into the intermediate layer 70ML. Next, the intermediate layer 70ML and the bottom layer 70BL are patterned such that the opening 72 extends into and through these layers, exposing the spacer 32. Depending on the size of the opening 72, the severity of overlay misalignment, and the location of the opening 72, the protective layers 36 and 60 may or may not be exposed. Exposing the protective layers 36 and 60 protects unwanted portions of the dielectric layer 26 from patterning.

[0045] Etching continues with etching the hard mask 28, where ​ The etched portion is not shown. Next, as... ​ As shown, the dielectric layer 26 is etched to form trenches 74-1, 74-2, and 74-3 in the hard mask 28, which are individually and collectively referred to as trench 74. In... ​ In the process flow 200 shown, the corresponding process is illustrated as process 230. According to some embodiments, etching of the dielectric layer 26 is performed using a process gas similar to that used in the preceding etching process. Trench 74-1 connects to via opening 66, similar to... ​ As shown. Trench 74-2 and 74-3 may be above and connected to other via openings 66 that are not in the plane shown. Trench 74-1, 74-2, and 74-3 extend to an intermediate level between the top and bottom surfaces of the dielectric layer 26. According to some embodiments, due to ​ As shown in the process diagram, via opening 66 extends to conductive feature 22A. The bottom of via opening 66 extends to the middle level marked by dashed line 67. ​ In an alternative embodiment, when trench 74 is formed, via opening 66 extends downward and stops at the top surface of etch stop layer 24. One or more etching processes can then be performed to etch through etch stop layer 24 and expose conductive feature 22B. After forming trenches 74-1, 74-2, and 74-3, the remaining bottom layer 70BL is removed, for example, using a process gas comprising CO2, NH3, O2, or a combination thereof. The resulting structure is as follows: ​ As shown.

[0046] ​ The formation of conductive material 78 filling the via opening 66 and trench 74 is shown. In such... ​In the illustrated process flow 200, the corresponding process is shown as process 232. According to some embodiments, a metallic material, such as cobalt, tungsten, or a combination thereof, is deposited. The deposition can be performed using a barrier-free process, wherein no barriers are formed, and the metallic material contacts the conductive feature 22A and the dielectric layer 26. According to an alternative embodiment, the conductive material may include the metallic material on the barriers and diffusion barriers. The barriers may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc. The metallic material may be formed of copper or contain copper.

[0047] In subsequent processes, planarization processes such as CMP or mechanical polishing are performed to remove excess conductive material 78 above the dielectric layer 26. Planarization processes may be performed until spacers 32, protective layers 36 and 60, and the hard mask layer 28 are removed, exposing the dielectric layer 26. The resulting structure is as follows: ​ As shown. Vias 80A and 80B (each individually and collectively referred to as via 80) and metal lines 82A, 82B, 82C, 82D and 82E (each individually and collectively referred to as metal line 82) are formed. In... ​ In the process flow 200 shown, the corresponding process is shown as process 234. ​ It shows ​ Reference section BB in the diagram.

[0048] ​ The formation of the upper layer is shown, which includes an etch stop layer 84, a dielectric layer 86, vias 88, and metal lines 90. The formation process can be similar to that of vias 80A and 80B and metal lines 82A, 82B, 82C, 82D, and 82E, and the details of the formation process will not be repeated herein. The materials and formation processes of the etch stop layer 84, dielectric layer 86, vias 88, and metal lines 90 can be similar to those of the corresponding etch stop layer 24, dielectric layer 26, vias 80, and metal lines 82, respectively.

[0049] like ​ As shown, vias 80A and 80B are formed using a double patterning process. Therefore, although vias 80A and 80B are closely positioned relative to each other, the pattern is unaffected by optical proximity effects. Similarly, metal lines 82C and 82D (as well as metal lines 82A and 82B) are formed in another double patterning process. Therefore, although metal lines 82A and 82B are closely positioned relative to each other, and metal lines 82C and 82D are closely positioned relative to each other, the pattern is unaffected by optical proximity effects. It can be understood that the spacing between some adjacent vias (and the spacing between adjacent metal lines) can be determined by the width W2 of the spacer 32 (…). ​ This is used to define the boundaries. Therefore, very fine lines / vias can be formed.

[0050] Embodiments of the present disclosure have some advantageous features. The spacers formed on the side wall of the mandrel serve as part of the etch mask that defines the first via and metal line. Since the spacers can be formed with higher height without the need to increase their lateral dimension, the spacers can serve as an effective etch mask in the process for defining the pattern of the via and metal line. For comparison, if the etch mask is formed by deposition and patterning (instead of using the spacers), in order to have a small line width of the etch mask, the thickness of the etch mask needs to be reduced, which can cause the etch to go through the etch mask during the formation of the via opening, thus, the etch mask can lose its function as an etch mask. In addition, the space occupied by the mandrel can also be used to form the second via and metal line. The first via and the second via and the first metal line and the second metal line are effectively formed in a dual patterning process. Since the lateral dimension of the spacers can be formed small, the via / metal line formed by the dual patterning process can be close to each other and can have a small lateral dimension.

[0051] According to some embodiments of the present disclosure, a method includes: forming a first mandrel and a second mandrel over a dielectric layer; forming a first spacer and a second spacer on the first mandrel and the second mandrel, respectively, wherein the first spacer and the second spacer are adjacent to each other and have a first space therebetween; etching the dielectric layer to form an opening in the dielectric layer, wherein the opening overlaps the first space, and wherein the first spacer and the second spacer serve as part of an etch mask in the etching; filling a conductive material into the opening; and performing a planarization process on the conductive material. In one embodiment, the opening penetrates the dielectric layer, a conductive feature underneath the dielectric layer is exposed to the opening, and wherein a remaining portion of the conductive material filling the opening forms a conductive via extending into the dielectric layer. In one embodiment, the opening stops at an intermediate level between a top surface and a bottom surface of the dielectric layer, and wherein a remaining portion of the conductive material forms a conductive line at an upper portion of the dielectric layer. In one embodiment, forming the first spacer and the second spacer includes: depositing a spacer layer on the first mandrel and the second mandrel; and performing an anisotropic etching process on the spacer layer, wherein a remaining portion of the spacer layer forms the first spacer and the second spacer. In one embodiment, the method further includes forming an additional etch mask on the first mandrel and the second mandrel and the first spacer and the second spacer, wherein the additional etch mask includes an additional opening, wherein a portion of the additional opening is directly above a portion of the first spacer. In one embodiment, the method further includes forming a third spacer on the first mandrel, wherein the first spacer and the third spacer are on opposite sides of the first mandrel, and wherein the method further includes: removing the first mandrel to form a second space between the first spacer and the third spacer; etching the dielectric layer to form an additional opening in the dielectric layer and directly below the second space, wherein the first spacer and the third spacer serve as part of an additional etch mask; and filling the additional opening with an additional conductive material. In one embodiment, the first spacer has a width and a height that is greater than the width. In one embodiment, the planarization process is performed until the first spacer and the second spacer are removed. In one embodiment, the method further includes forming a hard mask over the dielectric layer, wherein the first mandrel and the second mandrel and the first spacer and the second spacer are formed over the hard mask.In one embodiment, the method further includes forming a protective layer covering a portion of the first mandrel and the first spacer, wherein the protective layer acts as an additional portion of the etch mask when etching the dielectric layer to form the opening.

[0052] According to some embodiments of the disclosure, a method includes: forming a mandrel over a dielectric layer; forming a first spacer on a sidewall of the mandrel, wherein the first spacer includes a first sidewall and a second sidewall opposite to each other, wherein the second sidewall contacts the mandrel; etching a first portion of the dielectric layer to form a first opening in the dielectric layer, wherein the first opening has a third sidewall vertically aligned with the first sidewall; filling the first opening with a first conductive material; etching a second portion of the dielectric layer to form a second opening in the dielectric layer, wherein the second opening has a fourth sidewall vertically aligned with the second sidewall, and wherein the first opening and the second opening are located on opposite sides of the mandrel; and filling the second opening with a second conductive material. In one embodiment, the method further includes performing a planarization process to remove the first spacer, wherein a remaining portion of each of the first conductive material and the second conductive material forms a via or a metal line. In one embodiment, the method further includes forming a second spacer adjacent to the first spacer, having a space between the first spacer and the second spacer, and wherein the first opening is directly below the space. In one embodiment, the first opening has a fifth sidewall opposite to the third sidewall, and wherein the fifth sidewall is vertically aligned with a sixth sidewall of the second spacer. In one embodiment, the method further includes removing the mandrel, wherein the second portion of the dielectric layer is etched through a space left by the mandrel. In one embodiment, forming the first spacer includes: depositing a spacer layer on the mandrel; and performing an anisotropic etching process on the spacer layer, wherein a remaining portion of the spacer layer forms the first spacer.

[0053] According to some embodiments of the present disclosure, a method includes forming a hard mask over a low-k dielectric layer; forming a plurality of mandrels over the hard mask; forming a plurality of spacers on sidewalls of the plurality of mandrels, wherein first, second, and third spaces separate adjacent spacers of the plurality of spacers, wherein portions of the hard mask are exposed to the first, second, and third spaces; forming a protective layer filled into the first spaces; patterning the protective layer to remove the protective layer from the second and third spaces; forming a patterned etch mask over the protective layer; in a first etch process, etching through first portions of the hard mask and first portions of the low-k dielectric layer directly below the second spaces to form first openings in the low-k dielectric layer, wherein the protective layer and the patterned etch mask are used in combination as an etch mask; and in a second etch process, etching through second portions of the hard mask and second portions of the low-k dielectric layer directly below the third spaces to form second openings in the low-k dielectric layer. In one embodiment, the method further includes filling a first conductive material into the first openings. In one embodiment, the method further includes filling a second conductive material into the second openings, wherein the first and second conductive materials are filled in separate fill processes. In one embodiment, the method further includes performing a planarization process to remove portions of the first conductive material above the low-k dielectric layer, wherein in the planarization process, the plurality of mandrels, the plurality of spacers, and the hard mask are removed.

[0054] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

[0055] Example 1. A method of forming a semiconductor structure, comprising:

[0056] forming a first mandrel and a second mandrel over a dielectric layer;

[0057] forming a first spacer and a second spacer on the first mandrel and the second mandrel, respectively, wherein the first and second spacers are adjacent to each other and have a first space between the first and second spacers;

[0058] etching the dielectric layer to form an opening in the dielectric layer, wherein the opening overlaps the first space, and wherein the first spacer and the second spacer function as part of an etch mask in the etching;

[0059] filling the opening with a conductive material; and

[0060] performing a planarization process on the conductive material.

[0061] Example 2. The method of example 1, wherein the opening penetrates the dielectric layer, a conductive feature underneath the dielectric layer is exposed to the opening, and wherein a remaining portion of the conductive material filling the opening forms a conductive via extending into the dielectric layer.

[0062] Example 3. The method of example 1, wherein the opening stops at an intermediate level between a top surface and a bottom surface of the dielectric layer, and wherein a remaining portion of the conductive material forms a conductive line at an upper portion of the dielectric layer.

[0063] Example 4. The method of example 1, wherein forming the first spacer and the second spacer comprises:

[0064] depositing a spacer layer on the first mandrel and the second mandrel; and

[0065] performing an anisotropic etching process on the spacer layer, wherein a remaining portion of the spacer layer forms the first spacer and the second spacer.

[0066] Example 5. The method of example 1, further comprising forming an additional etch mask on the first mandrel and the second mandrel and the first spacer and the second spacer, wherein the additional etch mask comprises an additional opening, wherein a portion of the additional opening is directly above a portion of the first spacer.

[0067] Example 6. The method of example 1, further comprising forming a third spacer on the first mandrel, wherein the first spacer and the third spacer are on opposite sides of the first mandrel, and wherein the method further comprises:

[0068] removing the first mandrel to form a second space between the first spacer and the third spacer;

[0069] etching the dielectric layer to form an additional opening in the dielectric layer and directly underneath the second space, wherein the first spacer and the third spacer function as part of an additional etch mask; and

[0070] filling the additional openings with an additional conductive material.

[0071] Example 7. The method of example 1, wherein the first spacer has a width, and a height greater than the width.

[0072] Example 8. The method of example 1, wherein the planarization process is performed until the first spacer and the second spacer are removed.

[0073] Example 9. The method of example 1, further comprising forming a hard mask over the dielectric layer, wherein the first mandrel and the second mandrel and the first spacer and the second spacer are formed over the hard mask.

[0074] Example 10. The method of example 1, further comprising forming a protective layer covering a portion of the first mandrel and the first spacer, wherein the protective layer acts as an additional portion of the etch mask when etching the dielectric layer to form the opening.

[0075] Example 11. A method of forming a semiconductor structure, comprising:

[0076] forming a mandrel over a dielectric layer;

[0077] forming a first spacer on a sidewall of the mandrel, wherein the first spacer includes a first sidewall and a second sidewall opposite each other, wherein the second sidewall contacts the mandrel;

[0078] etching a first portion of the dielectric layer to form a first opening in the dielectric layer, wherein the first opening has a third sidewall vertically aligned with the first sidewall;

[0079] filling the first opening with a first conductive material;

[0080] etching a second portion of the dielectric layer to form a second opening in the dielectric layer, wherein the second opening has a fourth sidewall vertically aligned with the second sidewall, and wherein the first opening and the second opening are on opposite sides of the mandrel; and

[0081] filling the second opening with a second conductive material.

[0082] Example 12. The method of example 11, further comprising performing a planarization process to remove the first spacer, wherein a remaining portion of each of the first conductive material and the second conductive material forms a via or a metal line.

[0083] Example 13. The method of example 11, further comprising forming a second spacer adjacent to the first spacer, having a space between the first spacer and the second spacer, and wherein the first opening is directly below the space.

[0084] Example 14. The method of example 13, wherein the first opening has a fifth sidewall opposite the third sidewall, and wherein the fifth sidewall is in perpendicular alignment with a sixth sidewall of the second spacer.

[0085] Example 15. The method of example 11, further comprising removing the mandrel, wherein a second portion of the dielectric layer is etched through a space left by the mandrel.

[0086] Example 16. The method of example 11, wherein forming the first spacer comprises:

[0087] depositing a spacer layer on the mandrel; and

[0088] performing an anisotropic etching process on the spacer layer, wherein a remaining portion of the spacer layer forms the first spacer.

[0089] Example 17. A method of forming a semiconductor structure, comprising:

[0090] forming a hard mask over a low-k dielectric layer;

[0091] forming a plurality of mandrels over the hard mask;

[0092] forming a plurality of spacers on sidewalls of the plurality of mandrels, wherein a first space, a second space, and a third space separate adjacent spacers of the plurality of spacers, wherein portions of the hard mask are exposed to the first space, the second space, and the third space;

[0093] forming a protective layer filled into the first space;

[0094] patterning the protective layer to remove the protective layer from the second space and the third space;

[0095] forming a patterned etch mask over the protective layer;

[0096] in a first etching process, etching through a first portion of the hard mask and a first portion of the low-k dielectric layer directly below the second space to form a first opening in the low-k dielectric layer, wherein the protective layer and the patterned etch mask are used in combination as an etch mask; and

[0097] In a second etching process, etching through a second portion of the hard mask and a second portion of the low-k dielectric layer directly below the third space to form a second opening in the low-k dielectric layer.

[0098] Example 18. The method of example 17, further comprising filling a first conductive material into the first opening.

[0099] Example 19. The method of example 18, further comprising filling a second conductive material into the second opening, wherein the first conductive material and the second conductive material are filled in separate fill processes.

[0100] Example 20. The method of example 18, further comprising performing a planarization process to remove portions of the first conductive material above the low-k dielectric layer, wherein in the planarization process, the plurality of mandrels, the plurality of spacers, and the hard mask are removed.

Claims

1. A method for forming a semiconductor structure, comprising: A first mandrel and a second mandrel are formed on the dielectric layer; A first spacer and a second spacer are formed on the first mandrel and the second mandrel, respectively, wherein the first spacer and the second spacer are adjacent to each other and there is a first space between the first spacer and the second spacer; A protective layer is formed covering a portion of the first mandrel and the first spacer; The first spacer, the second spacer, and the protective layer are used together as an etching mask to etch the dielectric layer to form an opening in the dielectric layer, wherein the opening overlaps with the first space; Fill the opening with conductive material; and A planarization process is performed on the conductive material.

2. The method according to claim 1, wherein, The opening penetrates the dielectric layer, exposing conductive features beneath the dielectric layer to the opening, and wherein the remaining portion of the conductive material filling the opening forms a conductive via extending into the dielectric layer.

3. The method according to claim 1, wherein, The opening stops at a mid-level between the top and bottom surfaces of the dielectric layer, and the remaining portion of the conductive material forms a conductive line on the upper part of the dielectric layer.

4. The method according to claim 1, wherein, The formation of the first spacer and the second spacer includes: Deposit spacer layers on the first mandrel and the second mandrel; and An anisotropic etching process is performed on the spacer layer, wherein the remaining portion of the spacer layer forms the first spacer and the second spacer.

5. The method of claim 1, further comprising forming an additional etching mask on the first mandrel and the second mandrel, and on the first spacer and the second spacer, wherein, The additional etch mask includes additional openings, a portion of which is located directly above a portion of the first spacer.

6. The method of claim 1, further comprising forming a third spacer on the first mandrel, wherein, The first spacer and the third spacer are located on opposite sides of the first mandrel, and the method further includes: Remove the first mandrel to form a second space between the first spacer and the third spacer; Etching the dielectric layer to form an additional opening in the dielectric layer and directly below the second space, wherein the first spacer and the third spacer serve as part of the additional etching mask; and The additional opening is filled with additional conductive material.

7. The method according to claim 1, wherein, The first spacer has a width and a height greater than the width.

8. The method according to claim 1, wherein, The planarization process is performed until the first spacer and the second spacer are removed.

9. The method of claim 1, further comprising forming a hard mask on the dielectric layer, wherein the first mandrel and the second mandrel, as well as the first spacer and the second spacer, are formed on the hard mask.

10. A method for forming a semiconductor structure, comprising: A mandrel is formed on top of the dielectric layer; A first spacer is formed on the sidewall of the mandrel, wherein the first spacer includes a first sidewall and a second sidewall opposite to each other, wherein the second sidewall contacts the mandrel; A protective layer is formed covering a portion of the mandrel and the first spacer; The first spacer and the protective layer are used together as an etching mask to etch a first portion of the dielectric layer to form a first opening in the dielectric layer, wherein the first opening has a third sidewall that is perpendicularly aligned with the first sidewall. The first opening is filled with a first conductive material; Etching a second portion of the dielectric layer to form a second opening in the dielectric layer, wherein the second opening has a fourth sidewall perpendicularly aligned with the second sidewall, and wherein the first opening and the second opening are located on opposite sides of the first spacer; and The second opening is filled with a second conductive material.

11. The method of claim 10, further comprising performing a planarization process to remove the first spacer, wherein, The remaining portion of each of the first conductive material and the second conductive material forms a via or metal wire.

12. The method of claim 10, further comprising forming a second spacer adjacent to the first spacer, having a space between the first spacer and the second spacer, and wherein, The first opening is located directly below the space.

13. The method according to claim 12, wherein, The first opening has a fifth sidewall opposite to the third sidewall, and wherein the fifth sidewall is perpendicularly aligned with the sixth sidewall of the second spacer.

14. The method of claim 10, further comprising removing the mandrel, wherein, The second portion of the dielectric layer was etched through the space left by the mandrel.

15. The method according to claim 10, wherein, The first spacer includes: Depositing a spacer layer on the mandrel; and An anisotropic etching process is performed on the spacer layer, wherein the remaining portion of the spacer layer forms the first spacer.

16. A method for forming a semiconductor structure, comprising: A hard mask is formed on top of a low-k dielectric layer; Multiple mandrels are formed on the hard mask; Multiple spacers are formed on the sidewalls of the plurality of mandrels, wherein a first space, a second space, and a third space separate adjacent spacers among the plurality of spacers, wherein some portions of the hard mask are exposed to the first space, the second space, and the third space; A protective layer is formed to fill the first space; The protective layer is patterned to remove it from the second space and the third space; A patterned etching mask is formed on the protective layer; In the first etching process, the protective layer and the patterned etching mask are used in combination as an etching mask to etch a first portion of the hard mask and a first portion of the low-k dielectric layer directly beneath the second space, to form a first opening in the low-k dielectric layer; and In the second etching process, the second portion of the hard mask and the second portion of the low-k dielectric layer, which are directly below the third space, are etched to form a second opening in the low-k dielectric layer.

17. The method of claim 16, further comprising filling the first conductive material into the first opening.

18. The method of claim 17, further comprising filling the second conductive material into the second opening, wherein, The first conductive material and the second conductive material are filled in separate filling processes.

19. The method of claim 17, further comprising performing a planarization process to remove a portion of the first conductive material above the low-k dielectric layer, wherein, In the planarization process, the plurality of mandrels, the plurality of spacers, and the hard mask are removed.

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