A method of manufacturing a semiconductor device

Abstract

The present application relates to the technical field of semiconductor, and especially relates to a manufacturing method of semiconductor device, which comprises the following steps: forming an outer electrode and an inner electrode on a wafer, wherein the outer electrode is arranged correspondingly to the inner electrode; and forming an air medium between the outer electrode and the inner electrode. The method forms the inner electrode, the air medium and the outer electrode on the wafer, wherein the air medium is formed between the outer electrode and the inner electrode. The air medium is essentially air. The semiconductor formed by the structure uses air as the medium, can greatly reduce the transmission loss, uses the transmission of radio frequency signals, and has the characteristics of cost saving and high performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] In the development of semiconductor technology, chips have become smaller while becoming more functional. One technological approach involves stacking multiple devices in three dimensions to form a compact structure. To achieve this structure, through-hole technology is often used, including through silicon vias (TSVs) and through glass vias (TGVs).

[0003] In the field of radio frequency (RF), communication between RF chips on different layers requires the fabrication of vias using via technology, followed by the use of special transmission lines embedded within these vias for inter-chip communication. However, the vias often employ materials such as silicon oxide or organic compounds as the dielectric, leading to significant communication losses. Summary of the Invention

[0004] This application provides a method for manufacturing a semiconductor device, which solves the technical problem of high communication loss in chips in the prior art, and achieves the technical effect of optimizing the structure of vias in semiconductors and greatly reducing the communication loss of semiconductors.

[0005] In a first aspect, embodiments of the present invention provide a method for fabricating a semiconductor device, comprising:

[0006] An external electrode and an internal electrode are formed on a wafer, wherein the external electrode and the internal electrode are respectively disposed.

[0007] An air medium is formed between the outer electrode and the inner electrode.

[0008] Preferably, forming the external and internal electrodes on the wafer includes:

[0009] An annular blind via is formed on the wafer;

[0010] The wafer region within the annular blind hole is used as the inner electrode, and the wafer region outside the annular blind hole is used as the outer electrode.

[0011] Preferably, forming the external and internal electrodes on the wafer includes:

[0012] An annular blind via is formed on the wafer;

[0013] After forming an insulating layer on the inner wall of the annular blind hole, a metal layer is formed on the inner ring sidewall of the annular blind hole to form the inner electrode, and the metal layer is formed on the outer ring sidewall of the annular blind hole to form the outer electrode.

[0014] Preferably, after forming the outer electrode and the inner electrode, the method further includes:

[0015] The insulating layer is formed on the outer wall of the inner electrode and the outer wall of the outer electrode.

[0016] Preferably, forming the external and internal electrodes on the wafer includes:

[0017] Annular blind vias and hollow blind vias are formed on the wafer;

[0018] After forming an insulating layer on the inner wall of the hollow blind hole and the inner wall of the annular blind hole, a metal layer is filled into the hollow blind hole to form the inner electrode, and the metal layer is filled into the annular blind hole to form the outer electrode.

[0019] Preferably, forming an air medium between the outer electrode and the inner electrode includes:

[0020] When there is a connecting wafer region between the inner electrode and the outer electrode, the connecting wafer region is etched to form an etched region; after filling the etched region with a sacrificial layer, the wafer is polished to form a polished wafer; after bonding the polished wafer to another wafer, the sacrificial layer is released to form the air medium.

[0021] When there is no connecting wafer region between the inner electrode and the outer electrode, the sacrificial layer is filled into the region between the inner electrode and the outer electrode, and the wafer is polished to form a polished wafer; after the polished wafer is bonded to another wafer, the sacrificial layer is released to form the air medium.

[0022] Preferably, the material of the sacrificial layer includes organic materials or phosphosilicate glass.

[0023] Preferably, before forming the air medium, it further includes:

[0024] Wires are arranged on the inner electrode and the outer electrode respectively.

[0025] Preferably, the external electrode includes an intermittent external electrode or a non-intermittent external electrode.

[0026] Preferably, the wafer includes: a silicon wafer, a glass wafer, or a silicon carbide wafer.

[0027] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0028] In this embodiment of the invention, an inner electrode, an air dielectric, and an outer electrode are formed on a wafer, wherein the outer electrode surrounds the inner electrode, and the air dielectric is formed between the outer electrode and the inner electrode. The air dielectric is essentially air. The semiconductor forming this structure utilizes air as a dielectric, which significantly reduces transmission loss. For radio frequency signal transmission, it also offers cost savings and superior performance. Attached Figure Description

[0029] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0030] Figure 1 A schematic flowchart of the semiconductor fabrication method in an embodiment of the present invention is shown;

[0031] Figure 2a A top view of the semiconductor according to embodiment one of the present invention is shown;

[0032] Figure 2b A cross-sectional view of the semiconductor in embodiment one of the present invention is shown;

[0033] Figure 3 A schematic diagram of a semiconductor fabrication method according to Scheme 1 of the present invention is shown;

[0034] Figure 4a A top view of the semiconductor in embodiment two of the present invention is shown;

[0035] Figure 4b A cross-sectional view of the semiconductor in embodiment two of the present invention is shown;

[0036] Figure 5 A schematic diagram of a semiconductor fabrication method according to Scheme 2 of the present invention is shown;

[0037] Figure 6a A top view of the semiconductor in embodiment three of the present invention is shown;

[0038] Figure 6b A cross-sectional view of the semiconductor in embodiment three of the present invention is shown;

[0039] Figure 7 A schematic diagram of a semiconductor fabrication method according to embodiment three of the present invention is shown;

[0040] Figure 8 A top view of the unclosed shape of the outer electrode of the semiconductor in an embodiment of the present invention is shown;

[0041] Figure 9 A top view of the discontinuous external electrode of the semiconductor in an embodiment of the present invention is shown;

[0042] Figure 10 A top view of a semiconductor according to an embodiment of the present invention is shown;

[0043] Figure 11 A top view of the wiring of a semiconductor in an embodiment of the present invention is shown. Detailed Implementation

[0044] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0045] Example 1

[0046] The first embodiment of the present invention provides a method for fabricating a semiconductor device, such as... Figure 1 As shown, it includes:

[0047] S101, an external electrode and an internal electrode are formed on the wafer, wherein the external electrode and the internal electrode are configured to correspond to each other;

[0048] S102 forms an air medium between the outer electrode and the inner electrode.

[0049] Specifically, an inner electrode, an air dielectric, and an outer electrode are formed on the wafer, wherein the outer electrode is positioned corresponding to the inner electrode, and the air dielectric is formed between the outer electrode and the inner electrode. The air dielectric is essentially air. The semiconductor forming this structure uses air as the dielectric, and according to the calculation of formula (1), it can be concluded that this semiconductor can greatly reduce transmission loss.

[0050]

[0051] Where Z is the characteristic impedance, d is the inner diameter, D is the outer diameter, μ is the permeability of the medium, ω is the angular frequency, σ is the conductor conductivity, f is the frequency, and ε is the dielectric constant. r Let ε be the relative permittivity of the medium, c0 be the propagation speed of electromagnetic waves in vacuum (approximately 3 × 10⁸), and tanδ be the tangential loss of the medium. Compared to common insulating materials such as SiO₂ and SU-8, air has a smaller ε. r And tanδ. Therefore, in this embodiment, the semiconductor uses air as the transmission medium, which greatly reduces the transmission loss of the semiconductor.

[0052] It should also be noted that the wafers used in this embodiment include, but are not limited to, silicon wafers, glass wafers, or silicon carbide wafers. The external electrode corresponds to the internal electrode, and the specific corresponding structure can be that the external electrode surrounds the internal electrode, or the external electrode is located near the internal electrode; no specific limitation is made here. The composition of the external electrode, internal electrode, and air medium can form a coaxial structure where the center point of the external electrode, the center point of the internal electrode, and the center point of the air medium are on the same axis; that is, the air medium, external electrode, and internal electrode form a coaxial structure with the center line of the internal electrode as the axis; or it can form a non-coaxial structure, which is not limited here.

[0053] Below, in conjunction with Figure 1 The specific implementation steps of the semiconductor fabrication method provided in this embodiment will be described in detail below:

[0054] The overall process of semiconductor fabrication is as follows: External and internal electrodes are formed on a wafer, with the external and internal electrodes corresponding to each other. After the external and internal electrodes are formed, it is necessary to determine whether there is a connecting wafer region between them. If a connecting wafer region exists, it is etched to form an etched region. The wafer region between the external and internal electrodes is then etched to form the etched region. After etching, a sacrificial layer is filled into the etched region. The sacrificial layer material includes, but is not limited to, organic materials or phosphosilicate glass. Both sides of the wafer are then polished to expose the internal and external electrodes, forming a polished wafer. Chemical mechanical polishing (CMP) is preferred as the polishing technique. The polished wafer is bonded to another wafer to electrically connect the internal and external electrodes. Finally, the sacrificial layer is released, forming an air dielectric.

[0055] When there is no connecting wafer region between the inner electrode and the outer electrode, a sacrificial layer is filled into the region between the inner electrode and the outer electrode, and the wafer is polished to form a polished wafer; after bonding the polished wafer to another wafer, the sacrificial layer is released to form an air medium.

[0056] After the inner and outer electrodes are formed but before the air dielectric is formed, wires can be laid on the inner and outer electrodes separately. Specifically, this involves wiring the inner and outer electrodes before polishing the wafer, or wiring the inner and outer electrodes of the polished wafer separately before bonding it to another wafer. In reality, the specific wiring operation for the inner and outer electrodes is determined based on actual requirements.

[0057] The entire production process will be described in detail.

[0058] Option 1

[0059] like Figure 2a and Figure 2b As shown, annular blind vias are first formed on the wafer. The wafer region within the annular blind via is then used as the inner electrode, and the wafer region outside the annular blind via is used as the outer electrode.

[0060] The specific implementation steps are as follows: Figure 3 As shown, a) annular blind vias are etched on the wafer. Figure 3 The blank areas of the wafer are annular blind vias. b. The sacrificial layer is filled into the annular blind vias. Figure 3 The dotted area in step 1 is the sacrificial layer. c. Polish both sides of the wafer to form a polished wafer. d. Bond the polished wafer to another wafer to electrically connect the inner and outer electrodes of the polished wafer. e. Release the sacrificial layer to form an air medium; the blank area in step e is the air medium.

[0061] Option 1 uses silicon wafers doped with other elements, giving them low resistivity so they can be directly used as electrodes. Both internal and external electrodes are silicon, and air is used as the transmission medium. This optimizes the structure of vias in the semiconductor, significantly reducing losses in semiconductor communication.

[0062] Option 2

[0063] like Figure 4a and Figure 4b As shown, annular blind vias are first formed on the wafer; then, an insulating layer (not shown in Figure 4) is formed on the inner wall of the annular blind via. A metal layer is then formed on the inner ring sidewall of the annular blind via to form the inner electrode, and a metal layer is formed on the outer ring sidewall of the annular blind via to form the outer electrode. After forming the outer and inner electrodes, insulating layers are formed on the outer walls of both the inner and outer electrodes.

[0064] The specific implementation steps are as follows: Figure 5 As shown, a) annular blind vias are etched on the wafer. Figure 5 The blank areas of the wafer are annular blind vias. b. An insulating layer is formed on the inner wall of the annular blind via. Figure 5 The obliquely lined area represents the insulating layer. The insulating layer may be made of materials including, but not limited to, silicon dioxide and silicon nitride. c. After forming the insulating layer on the inner wall of the annular blind hole, a metal layer is formed on the inner ring sidewall of the annular blind hole to form the inner electrode, and a metal layer is formed on the outer ring sidewall of the annular blind hole to form the outer electrode. The metal layer is a metallic conductor, such as gold, silver, or copper. d. After forming the outer and inner electrodes, insulating layers are formed on the outer walls of both the inner and outer electrodes. e. The sacrificial layer is filled into the annular blind hole. Figure 5The dotted area in the diagram is the sacrificial layer. f. Polish both sides of the wafer to form a polished wafer. g. Bond the polished wafer to another wafer to electrically connect the inner and outer electrodes of the polished wafer. h. Release the sacrificial layer to form an air medium; the blank area in h is the air medium.

[0065] In Scheme 2, both the inner and outer electrodes are made of partially filled metal, with air as the transmission medium. This optimizes the structure of the vias in the semiconductor and greatly reduces the loss in semiconductor communication.

[0066] It should also be noted that, in the scheme of this embodiment, the insulating layer provided on the outside of the inner electrode and the outer electrode is provided according to actual needs. That is, the insulating layer may or may not be provided, or it may be provided on the outside of the inner electrode and not on the outside of the outer electrode.

[0067] Option 3

[0068] like Figure 6a and Figure 6b As shown, annular blind vias and hollow blind vias are formed on the wafer. After forming insulating layers on the inner walls of the hollow blind vias and the annular blind vias, metal layers are filled into the hollow blind vias to form inner electrodes, and metal layers are filled into the annular blind vias to form outer electrodes.

[0069] The specific implementation steps are as follows: Figure 7 As shown, a) forming annular blind vias and hollow blind vias on the wafer. Figure 7 The central blank area of ​​the wafer is a hollow blind via, and the blank area surrounding the central blank area is a ring-shaped blind via. An insulating layer is formed on the inner wall of both the hollow blind via and the ring-shaped blind via. Figure 7 The obliquely lined area represents the insulating layer. The insulating layer may be made of materials including, but not limited to, silicon dioxide and silicon nitride. c. After forming the insulating layer on the inner wall of the hollow blind via, a metal layer is filled into the hollow blind via to form the inner electrode; after forming the insulating layer on the inner wall of the annular blind via, a metal layer is filled into the annular blind via to form the outer electrode. The metal layer is a metallic conductor, such as gold, silver, or copper. d. After the outer and inner electrodes are formed, the wafer region between the outer and inner electrodes is etched to form the etched region. Figure 7 The blank area in d is the etching area. e. Fill the etching area with the sacrificial layer. Figure 7 The dotted area in the diagram is the sacrificial layer. f. Polish both sides of the wafer to form a polished wafer. g. Bond the polished wafer to another wafer to electrically connect the inner and outer electrodes of the polished wafer. h. Release the sacrificial layer to form an air medium; the blank area in h is the air medium.

[0070] In Scheme 3, both the inner and outer electrodes are made of solid filled metal, with air as the transmission medium. This optimizes the structure of the through-hole in the semiconductor and greatly reduces the loss in semiconductor communication.

[0071] Option 4

[0072] In this embodiment, the outer electrode is arranged correspondingly to the inner electrode. In schemes one through three described above, the outer electrode surrounds the inner electrode. In scheme four, the outer electrode is not closed and is arranged correspondingly to the inner electrode. Figure 8 As shown, the central black and white grid area is the inner electrode, the blank area is the air medium, and the ring-shaped black and white grid area is the outer electrode. From Figure 8 As can be seen, the outer electrode does not completely surround or enclose the inner electrode, so the outer electrode is considered to be an open shape.

[0073] Option 5

[0074] The external electrodes in this embodiment include discontinuous or continuous external electrodes. The external electrodes in schemes one to three are continuous and uninterrupted; the external electrode in scheme four is continuous and not enclosed; and the external electrode in scheme five is discontinuous and not enclosed. Figure 9 As shown, a central blind via and multiple sub-blind vias are formed on the wafer, wherein the multiple sub-blind vias are located near the central blind via. After forming an insulating layer on the inner wall of the central blind via and the inner walls of the multiple sub-blind vias, a metal layer is filled into the central blind via to form an inner electrode, and a metal layer is filled into the multiple sub-blind vias to form an outer electrode. Figure 9 In the diagram, the areas marked with well symbols represent the inner and outer electrodes, respectively, while the blank areas represent the air medium.

[0075] It should also be noted that the shapes of the inner and outer electrodes of the semiconductor fabricated by the method of this embodiment are not specifically limited. As shown in Figure 10, the rectangle with black and white grids in the middle is the inner electrode, the irregular ring with black and white grids is the outer electrode, and the blank area between the inner and outer electrodes is the air medium.

[0076] Before forming the air dielectric, wires are arranged on the inner and outer electrodes of the wafer. For example, the wafer in Scheme 3 is wired as follows: Figure 11 As shown, the black and white grid area in the middle is the inner electrode, the circular black and white grid area is the outer electrode, the blank area is the air medium, and the vertical line area is the wire.

[0077] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0078] In this embodiment, an inner electrode, an air dielectric, and an outer electrode are formed on the wafer, wherein the outer electrode surrounds the inner electrode, and the air dielectric is formed between the outer electrode and the inner electrode. The air dielectric is essentially air. The semiconductor with this structure utilizes air as a dielectric, which significantly reduces transmission loss. For radio frequency signal transmission, it also offers cost savings and superior performance.

[0079] Those skilled in the art will understand that although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0080] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: An outer electrode and an inner electrode are formed on a wafer, wherein the outer electrode is disposed correspondingly to the inner electrode; the outer electrode surrounds the inner electrode; An air medium is formed between the outer electrode and the inner electrode, comprising: When there is a connecting wafer region between the inner electrode and the outer electrode, the connecting wafer region is etched to form an etched region; after filling the etched region with a sacrificial layer, the wafer is polished to form a polished wafer; after bonding the polished wafer to another wafer, the sacrificial layer is released to form the air medium. When there is no connecting wafer region between the inner electrode and the outer electrode, the sacrificial layer is filled into the region between the inner electrode and the outer electrode, and the wafer is polished to form a polished wafer; after bonding the polished wafer to another wafer, the sacrificial layer is released to form the air medium; wherein, the air medium serves as a radio frequency signal transmission medium; Before forming the air medium, the method further includes: arranging wires on the inner electrode and the outer electrode respectively.

2. The manufacturing method as described in claim 1, characterized in that, The process of forming external and internal electrodes on the wafer includes: An annular blind via is formed on the wafer; The wafer region within the annular blind hole is used as the inner electrode, and the wafer region outside the annular blind hole is used as the outer electrode.

3. The manufacturing method as described in claim 1, characterized in that, The process of forming external and internal electrodes on the wafer includes: An annular blind via is formed on the wafer; After forming an insulating layer on the inner wall of the annular blind hole, a metal layer is formed on the inner annular sidewall of the annular blind hole to form the inner electrode, and the metal layer is formed on the outer annular sidewall of the annular blind hole to form the outer electrode.

4. The manufacturing method as described in claim 3, characterized in that, After forming the outer electrode and the inner electrode, the process further includes: The insulating layer is formed on the outer wall of the inner electrode and the outer wall of the outer electrode.

5. The manufacturing method as described in claim 1, characterized in that, The process of forming external and internal electrodes on the wafer includes: Annular blind vias and hollow blind vias are formed on the wafer; After forming an insulating layer on the inner wall of the hollow blind hole and the inner wall of the annular blind hole, a metal layer is filled into the hollow blind hole to form the inner electrode, and the metal layer is filled into the annular blind hole to form the outer electrode.

6. The manufacturing method as described in claim 1, characterized in that, The sacrificial layer is made of organic materials or phosphosilicate glass.

7. The manufacturing method as described in claim 1, characterized in that, The external electrode includes an intermittent external electrode or an uninterrupted external electrode.

8. The manufacturing method as described in claim 1, characterized in that, The wafer includes: silicon wafer, glass wafer or silicon carbide wafer.

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