Test Structure and Method for Self-Heating Effect of FinFET

Abstract

The present invention discloses a test structure for the self-heating effect of a FinFET. A FinFET with a self-heating effect is formed on a fin body. The test structure includes a Zener diode, which is composed of a first embedded epitaxial layer heavily doped with a first conduction type formed on the fin body and a second embedded epitaxial layer heavily doped with a second conduction type. A well of the first conduction type is formed at the bottom of the first embedded epitaxial layer. The self-heating effect of the FinFET will heat the area of the fin body covered by the FinFET and the area adjacent to the FinFET. The Zener diode is arranged on the area of the fin body adjacent to the FinFET. By utilizing the characteristic that the breakdown voltage of the Zener diode changes with temperature, the self-heating effect is measured by measuring the breakdown voltage of the Zener diode. The present invention also discloses a test method for the self-heating effect of a FinFET. The present invention can achieve accurate testing of the self-heating effect of the FinFET, and will not have an adverse impact on the conduction of the FinFET, and is also convenient for process integration.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a test structure for the self-heating effect (SHE) of a fin field effect transistor (FinFET). The present invention also relates to a test method for the self-heating effect of a FinFET. Background Art

[0002] As Figure 1 shown, it is a schematic structural diagram of the heat dissipation path of an existing planar MOSFET; a shallow trench isolation 102 is formed on a semiconductor substrate 101, and the shallow trench isolation 102 isolates an active region on the semiconductor substrate 101. The planar MOSFET is formed on the active region. Figure 1 shows the gate structure 103 of the planar MOSFET. The channel region 104 is formed on the surface of the active region covered by the gate structure 103. The gate structure 103 generally includes a stacked gate dielectric layer such as a gate oxide layer and a polysilicon gate. Source regions and drain regions are formed in the active regions on both sides of the gate structure 103. When the planar MOSFET is turned on, the channel region 104 is inverted and a channel current connecting the source region and the drain region is formed. The heat generated by the channel current will dissipate along the arrow line shown by the mark 105. This heat dissipation path is large and short, and the heat generated by the channel current can usually be dissipated in time. Therefore, the planar MOSFET is not likely to generate the self-heating effect.

[0003] As Figure 2 shown, it is a schematic structural diagram of the heat dissipation path of an existing FinFET; a fin body 201 is formed on a semiconductor substrate 202 by patterning and etching the semiconductor substrate 202. A shallow trench isolation 203 is formed at the bottom of the spaced regions of the fin body 201. The shallow trench isolation 203 only covers the bottom part of the fin body 201, and the top part of the fin body 201 is used to form the FinFET. The gate structure 204 will cover both the top surface and the side surfaces of the top part of the fin body 201 at the same time. Therefore, the gate structure 204 will deplete the channel region formed by the top part of the fin body 201 from the top surface and the two side surfaces at the same time. The channel region is shown by the dashed box 205. When the FinFET is operating, channel currents will be formed on both the top surface and the two side surfaces of the fin body 201. Therefore, a large amount of heat will be generated in the fin body 201. The heat generated in the fin body 201 needs to be dissipated through the arrow line shown by the mark 206. It can be seen that the width of the heat dissipation path is narrow and the depth is deep. Coupled with the fact that the heat generated by the channel current is concentrated and large, the heat in the fin body 201 is not easily dissipated. As a result, the temperature of the fin body 201 rises, thus generating the self-heating effect.

[0004] If the self-heating effect of the FinFET is severe, it will have an adverse impact on the performance of the device. Therefore, it is necessary to test the self-heating effect of the FinFET. There are various test structures for the self-heating effect of FinFETs in the prior art. For example, Figure 3 Shown is a top view of the first prior art test structure for the self-heating effect of a FinFET; Figure 3 shows that multiple fin bodies 301 are formed on a semiconductor substrate, and the fin bodies 301 are arranged in parallel. Multiple first FinFETs with self-heating effects are provided on each fin body 301. The first FinFETs on different fin bodies 301 are aligned, and the gate structures 302 of the aligned first FinFETs are connected into an integral structure. The first prior art test structure consists of a second FinFET as a sensor, and the gate structure 304 of the second FinFET covers the fin body 301 adjacent to the first FinFET. Figure 3 In it, the second FinFETs on each fin body 301 are also aligned, and the gate structures 304 are connected to form an integral structure. A dummy gate structure 303 is also provided between the gate structures 302 and 304. The first prior art test structure requires a second FinFET specifically designed to be different from the first FinFET, which will inevitably increase the difficulty of process integration and the process cost will increase; at the same time, the channel current of the second FinFET itself will also generate heat, which will have an adverse impact on the performance of the first FinFET.

[0005] For example, Figure 4 Shown is a top view of the second prior art test structure for the self-heating effect of a FinFET; Figure 4 shows that multiple fin bodies 401 are formed on a semiconductor substrate, and the fin bodies 401 are arranged in parallel. Multiple FinFETs with self-heating effects are provided on each fin body 401. The FinFETs on different fin bodies 401 are aligned, and the gate structures 403 of the aligned FinFETs are connected into an integral structure. The second prior art test structure adopts a Kelvin four-wire detection (4T Kelvin sensing) circuit, Figure 4 and the four test terminals shown in it are marked with 403a, 403b, 403c, and 403d respectively. The second prior art test structure detects the resistance of the gate structure 403 through the Kelvin four-wire detection circuit, and obtains the magnitude of the self-heating effect of the FinFET through the detected resistance.

[0006] Generally, the gate structure of a FinFET is composed of a gate dielectric and a metal gate stacked; 4T Kelvin is a currently popular method for characterizing SHE, but it directly measures the gate of the FinFET and has low sensitivity because heat needs to penetrate the gate dielectric with a very small thermal conductivity into the metal gate.

[0007] Currently, there are other structures to detect the self-heating effect. For example, using a PN junction for detection, the breakdown voltage of the PN junction increases with the increase in temperature, and the higher breakdown voltage will have an adverse effect on the device. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a test structure for the self-heating effect of a FinFET, which can accurately test the self-heating effect of the FinFET, and will not have an adverse effect on the conduction of the FinFET, and is also convenient for process integration. For this purpose, the present invention also provides a test method for the self-heating effect of a FinFET.

[0009] To solve the above technical problem, in the test structure for the self-heating effect of a FinFET provided by the present invention, a FinFET with a self-heating effect is formed on the fin body.

[0010] The test structure includes a Zener diode, which is composed of a first embedded epitaxial layer doped with a first conductivity type and heavily doped and a second embedded epitaxial layer doped with a second conductivity type and heavily doped formed on the fin body. A well of the first conductivity type is formed in the fin body at the bottom of the first embedded epitaxial layer, and the second embedded epitaxial layer is formed on the top of the first embedded epitaxial layer.

[0011] The self-heating effect of the FinFET will heat the area of the fin body covered by the FinFET and the area adjacent to the FinFET. The Zener diode is arranged on the area of the fin body adjacent to the FinFET. By using the characteristic that the breakdown voltage of the Zener diode changes with temperature, the area of the fin body adjacent to the FinFET is measured by measuring the breakdown voltage of the Zener diode to realize the test of the self-heating effect of the FinFET; the higher the doping concentration of the first embedded epitaxial layer and the second embedded epitaxial layer, the lower the breakdown voltage of the Zener diode, and the smaller the influence on the conduction of the adjacent FinFET.

[0012] A further improvement is that the fin body is formed by patterning and etching a semiconductor substrate, and multiple fin bodies are formed on the semiconductor substrate.

[0013] A further improvement is that multiple FinFETs are integrated on the semiconductor substrate, and on each fin body, the Zener diode is located between the formation regions of two corresponding FinFETs.

[0014] A further improvement is that after the formation regions of the two FinFETs, a plurality of dummy gate structures are formed. The dummy gate structures cover the top surface and the side surfaces of the fin bodies, and the formation region of the Zener diode is defined by self-alignment through two adjacent dummy gate structures.

[0015] A further improvement is that a plurality of the fin bodies are arranged in parallel, the FinFETs formed on each of the fin bodies are aligned, and the Zener diodes formed on each of the fin bodies are also aligned.

[0016] A further improvement is that the aligned FinFETs formed on the plurality of fin bodies arranged in parallel form a parallel structure, and the aligned Zener diodes also form a parallel structure.

[0017] A further improvement is that the semiconductor substrate includes a silicon substrate.

[0018] A further improvement is that the FinFET includes an N-type FinFET and a P-type FinFET.

[0019] A further improvement is that in the formation region of the N-type FinFET, a P-type well is formed on the fin body, an embedded SiP epitaxial layer is formed on the fin bodies on both sides of the gate structure of the N-type FinFET, and N-type heavily doped source and drain regions are formed in the embedded SiP epitaxial layer.

[0020] A further improvement is that in the formation region of the P-type FinFET, a P-type well is formed on the fin body, an embedded SiGe epitaxial layer is formed on the fin bodies on both sides of the gate structure of the P-type FinFET, and P-type heavily doped source and drain regions are formed in the embedded SiGe epitaxial layer.

[0021] A further improvement is that the first conduction type is N-type, the second conduction type is P-type, the first embedded epitaxial layer is an embedded SiP epitaxial layer, and the second embedded epitaxial layer is an embedded SiGe epitaxial layer.

[0022] A further improvement is that the first conduction type is P-type, the second conduction type is N-type, the first embedded epitaxial layer is an embedded SiGe epitaxial layer, and the second embedded epitaxial layer is an embedded SiP epitaxial layer.

[0023] To solve the above technical problems, the test method for the self-heating effect of the FinFET provided by the present invention includes the following steps:

[0024] Step 1, forming the test structure.

[0025] Step 2, testing and forming a first curve in which the breakdown voltage of the Zener diode forming the test structure varies with temperature.

[0026] Step 3: Turn on the FinFET. The self-heating effect of the FinFET heats the fin body and raises its temperature.

[0027] Step 4: Test the breakdown voltage of the Zener diode and obtain the temperature of the region of the fin body adjacent to the FinFET according to the first curve.

[0028] A further improvement is that in Step 1, the first wire type is N-type, the second conduction type is P-type, the first embedded epitaxial layer is an embedded SiP epitaxial layer, and the second embedded epitaxial layer is an embedded SiGe epitaxial layer.

[0029] A further improvement is that in Step 1, the first wire type is P-type, the second conduction type is N-type, the first embedded epitaxial layer is an embedded SiGe epitaxial layer, and the second embedded epitaxial layer is an embedded SiP epitaxial layer.

[0030] In the present invention, by providing a Zener diode adjacent to the FinFET as a test structure, and utilizing the characteristic that the breakdown voltage of the Zener diode decreases with the increase of temperature, when the FinFET is turned on, the breakdown voltage of the Zener diode is measured to obtain the temperature of the fin body in the adjacent region of the FinFET, so as to accurately test the self-heating effect of the FinFET.

[0031] Since the breakdown voltage of the Zener diode is very small, it basically has no adverse effect on the conduction of the FinFET during the test. By increasing the doping concentration of the first embedded epitaxial layer and the second embedded epitaxial layer of the Zener diode, the adverse effect on the conduction of the FinFET during the test can be further reduced.

[0032] In addition, the Zener diode of the present invention is formed by stacking a heavily doped first embedded epitaxial layer and a second embedded epitaxial layer. The first embedded epitaxial layer and the second embedded epitaxial layer can be integrated with the embedded epitaxial layers used in the FinFET, such as the embedded SiP epitaxial layer of the N-type FinFET and the embedded SiGe epitaxial layer of the P-type FinFET. Therefore, the present invention is convenient for process integration and has a low process cost. Description of the Drawings

[0033] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments:

[0034] Figure 1 is a schematic structural diagram of the heat dissipation path of an existing planar MOSFET;

[0035] Figure 2 is a schematic structural diagram of the heat dissipation path of an existing FinFET;

[0036] Figure 3 is a top view of a test structure for the self-heating effect of the first existing FinFET;

[0037] Figure 4 is a top view of a test structure for the self-heating effect of the second existing FinFET;

[0038] Figure 5 is a top view of a test structure for the self-heating effect of the FinFET according to an embodiment of the present invention;

[0039] Figure 6 is Figure 5 a cross-sectional view of the test structure in Detailed implementation manners

[0040] As Figure 5 shown, it is a top view of a test structure 504 for the self-heating effect of the FinFET according to an embodiment of the present invention; as Figure 6 shown, it is Figure 5 a cross-sectional view of the test structure 504 in

[0041] In the test structure 504 for the self-heating effect of the FinFET, a FinFET with a self-heating effect is formed on a fin body 501. The test structure 504 includes a Zener diode 505, and the Zener diode 505 is composed of a first embedded epitaxial layer 603 with a heavily doped first conductivity type formed on the fin body 501 and a second embedded epitaxial layer 604 with a heavily doped second conductivity type. A first conductivity type well 607 is formed in the fin body 501 at the bottom of the first embedded epitaxial layer 603, and the second embedded epitaxial layer 604 is formed on the top of the first embedded epitaxial layer 603.

[0042] The self-heating effect of the FinFET will heat the area of the fin body 501 covered by the FinFET and the area adjacent to the FinFET. The Zener diode 505 is disposed on the area adjacent to the FinFET of the fin body 501. By utilizing the characteristic that the breakdown voltage of the Zener diode 505 varies with temperature, the area adjacent to the FinFET of the fin body 501 is measured by measuring the breakdown voltage of the Zener diode 505 to implement the test of the self-heating effect of the FinFET; the higher the doping concentrations of the first embedded epitaxial layer 603 and the second embedded epitaxial layer 604, the lower the breakdown voltage of the Zener diode 505, and the smaller the influence on the conduction of the adjacent FinFET.

[0043] In an embodiment of the present invention, the fin body 501 is formed by patterning and etching a semiconductor substrate 601, and a plurality of the fin bodies 501 are formed on the semiconductor substrate 601.

[0044] The semiconductor substrate 601 includes a silicon substrate.

[0045] As Figure 6 shown, a shallow trench isolation 602 is formed in the spaced region of the fin body 501.

[0046] A plurality of the FinFETs are integrated on the semiconductor substrate 601. On each of the fin bodies 501, the Zener diode 505 is located between the formation regions of two corresponding FinFETs.

[0047] After the formation regions of two FinFETs, a plurality of dummy gate structures 503 are further formed. The dummy gate structures 503 cover the top surface and side surfaces of the fin body 501, and the formation region of the Zener diode 505 is defined by self-alignment through two adjacent dummy gate structures 503.

[0048] The plurality of fin bodies 501 are arranged in parallel. The FinFETs formed on each of the fin bodies 501 are aligned, and the Zener diodes 505 formed on each of the fin bodies 501 are also aligned.

[0049] The aligned FinFETs formed on the plurality of fin bodies 501 arranged in parallel form a parallel structure, and the aligned Zener diodes 505 also form a parallel structure. Figure 5 In, the gate structures 502 of the aligned FinFETs are connected to form an integral structure.

[0050] The FinFET includes an N-type FinFET and a P-type FinFET.

[0051] In the formation region of the N-type FinFET, a P-type well is formed on the fin body 501, an embedded SiP epitaxial layer is formed on the fin body 501 on both sides of the gate structure of the N-type FinFET, and N-type heavily doped source and drain regions are formed in the embedded SiP epitaxial layer.

[0052] In the formation region of the P-type FinFET, a P-type well is formed on the fin body 501, an embedded SiGe epitaxial layer is formed on the fin body 501 on both sides of the gate structure of the P-type FinFET, and P-type heavily doped source and drain regions are formed in the embedded SiGe epitaxial layer.

[0053] In an embodiment of the present invention, the first wire type is N-type, the second conductive type is P-type, the first embedded epitaxial layer 603 is an embedded SiP epitaxial layer, and the second embedded epitaxial layer 604 is an embedded SiGe epitaxial layer. In other embodiments, it can also be: the first wire type is P-type, the second conductive type is N-type, the first embedded epitaxial layer 603 is an embedded SiGe epitaxial layer, and the second embedded epitaxial layer 604 is an embedded SiP epitaxial layer.

[0054] Figure 5 It also shows an interlayer film 605 and a metal layer 606. The metal layer 606 is the zeroth metal layer, usually formed of tungsten metal. The second embedded epitaxial layer 604 is led out through the tungsten metal on the top.

[0055] In an embodiment of the present invention, the Zener diode 505 adjacent to the FinFET is set as the test structure 504. By using the characteristic that the breakdown voltage of the Zener diode 505 decreases with the increase of temperature, when the FinFET is turned on, the breakdown voltage of the Zener diode 505 is measured to obtain the temperature of the fin body 501 in the adjacent area of the FinFET, so as to accurately test the self-heating effect of the FinFET.

[0056] Since the breakdown voltage of the Zener diode 505 is very small, it basically has no adverse effect on the conduction of the FinFET during the test. By increasing the doping concentration of the first embedded epitaxial layer 603 and the second embedded epitaxial layer 604 of the Zener diode 505, the adverse effect on the conduction of the FinFET during the test can be further reduced.

[0057] In addition, the Zener diode 505 in the embodiment of the present invention is formed by stacking the heavily doped first embedded epitaxial layer 603 and the second embedded epitaxial layer 604. The first embedded epitaxial layer 603 and the second embedded epitaxial layer 604 can be integrated with the embedded epitaxial layers used in the FinFET, such as the embedded SiP epitaxial layer of the N-type FinFET and the embedded SiGe epitaxial layer of the P-type FinFET, so the embodiment of the present invention is convenient for process integration and has a low process cost.

[0058] The test method for the self-heating effect of the FinFET in the embodiment of the present invention includes the following steps:

[0059] Step 1: Form the test structure 504.

[0060] In the method of the embodiment of the present invention, the first wire type is N-type, the second conductive type is P-type, the first embedded epitaxial layer 603 is an embedded SiP epitaxial layer, and the second embedded epitaxial layer 604 is an embedded SiGe epitaxial layer. Or, the first wire type is P-type, the second conductive type is N-type, the first embedded epitaxial layer 603 is an embedded SiGe epitaxial layer, and the second embedded epitaxial layer 604 is an embedded SiP epitaxial layer.

[0061] It can be seen that both the first embedded epitaxial layer 603 and the second embedded epitaxial layer 604 in the method of the embodiment of the present invention are compatible with the existing process and are convenient for manufacturing.

[0062] Step 2: Form a first curve showing that the breakdown voltage of the Zener diode 505 forming the test structure 504 changes with temperature through testing.

[0063] Step 3: Turn on the FinFET, and the self-heating effect of the FinFET heats the fin body 501 and raises the temperature of the fin body 501.

[0064] Step 4: Test the breakdown voltage of the Zener diode 505 and obtain the temperature of the region of the fin body 501 near the FinFET according to the first curve.

[0065] Those skilled in the art should understand that the breakdown of the Zener diode 505 is mainly band-to-band breakdown. After the temperature rises, the bandgap (Eg) of the semiconductor material will decrease, and the band-to-band tunneling breakdown current will increase, so the breakdown voltage will decrease; that is, the breakdown voltage will decrease as the temperature rises. Since the lower the breakdown voltage, the more adverse effects on the FinFET can be reduced. The breakdown voltage of the Zener diode 505 also decreases as the temperature rises, which is obviously more conducive to improving the measurement accuracy.

[0066] For an ordinary PN junction, such as the PN junction formed by the contact between the embedded epitaxial layer and the well region with different conductive types, the breakdown voltage of the PN junction will increase as the temperature rises. Therefore, when the temperature increases, the measured breakdown voltage will also increase, and the influence on the FinFET will also increase, which is not conducive to improving the measurement accuracy. In the embodiment of the present invention, the test structure is specifically selected to be realized by a Zener diode, which can eliminate the defects brought about when the breakdown voltage of the device also increases as the temperature rises, so as to achieve better technical effects.

[0067] The present invention has been described in detail through specific embodiments above, but these do not constitute limitations to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many deformations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A test structure for the self-heating effect of a FinFET, characterized in that: a FinFET with a self-heating effect is formed on the fin body; the test structure includes a Zener diode, which is composed of a first embedded epitaxial layer heavily doped with a first conductivity type formed on the fin body and a second embedded epitaxial layer heavily doped with a second conductivity type. A well of the first conductivity type is formed in the fin body at the bottom of the first embedded epitaxial layer, and the second embedded epitaxial layer is formed on top of the first embedded epitaxial layer; the self-heating effect of the FinFET heats the area of the fin body covered by the FinFET and the area adjacent to the FinFET. The Zener diode is arranged on the area of the fin body adjacent to the FinFET. By using the characteristic that the breakdown voltage of the Zener diode changes with temperature, the area of the fin body adjacent to the FinFET is measured by measuring the breakdown voltage of the Zener diode to realize the test of the self-heating effect of the FinFET; the higher the doping concentrations of the first embedded epitaxial layer and the second embedded epitaxial layer, the lower the breakdown voltage of the Zener diode and the smaller the influence on the conduction of the adjacent FinFET.

2. The test structure for the self-heating effect of a FinFET according to claim 1, characterized in that: the fin body is formed by patterning and etching a semiconductor substrate, and multiple fin bodies are formed on the semiconductor substrate.

3. The test structure for the self-heating effect of a FinFET according to claim 2, characterized in that: multiple FinFETs are integrated on the semiconductor substrate. On each fin body, the Zener diode is located between the formation regions of two corresponding FinFETs.

4. The test structure for the self-heating effect of a FinFET according to claim 3, characterized in that: after the formation regions of two FinFETs, multiple dummy gate structures are further formed. The dummy gate structures cover the top surface and the side surfaces of the fin body, and the formation region of the Zener diode is self-aligned and defined by two adjacent dummy gate structures.

5. The test structure for the self-heating effect of a FinFET according to claim 4, characterized in that: multiple fin bodies are arranged in parallel, the FinFETs formed on each fin body are aligned, and the Zener diodes formed on each fin body are also aligned.

6. The test structure for the self-heating effect of a FinFET according to claim 5, characterized in that: the aligned FinFETs formed on multiple fin bodies arranged in parallel form a parallel structure, and the aligned Zener diodes also form a parallel structure.

7. The test structure for the self-heating effect of a FinFET according to claim 2, characterized in that: the semiconductor substrate includes a silicon substrate.

8. The test structure for the self-heating effect of a FinFET according to claim 1, characterized in that: the FinFET includes an N-type FinFET and a P-type FinFET.

9. The test structure for the self-heating effect of the FinFET as described in claim 8, characterized in that: In the formation region of the N-type FinFET, a P-type well is formed on the fin body, an embedded SiP epitaxial layer is formed on the fin bodies on both sides of the gate structure of the N-type FinFET, and N-type heavily doped source and drain regions are formed in the embedded SiP epitaxial layer.

10. The test structure for the self-heating effect of the FinFET as described in claim 8, characterized in that: In the formation region of the P-type FinFET, a P-type well is formed on the fin body, an embedded SiGe epitaxial layer is formed on the fin bodies on both sides of the gate structure of the P-type FinFET, and P-type heavily doped source and drain regions are formed in the embedded SiGe epitaxial layer.

11. The test structure for the self-heating effect of the FinFET as described in claim 1, characterized in that: The first wire type is N-type, the second conduction type is P-type, the first embedded epitaxial layer is an embedded SiP epitaxial layer, and the second embedded epitaxial layer is an embedded SiGe epitaxial layer.

12. The test structure for the self-heating effect of the FinFET as described in claim 1, characterized in that: The first wire type is P-type, the second conduction type is N-type, the first embedded epitaxial layer is an embedded SiGe epitaxial layer, and the second embedded epitaxial layer is an embedded SiP epitaxial layer.

13. A test method using the test structure for the self-heating effect of the FinFET as described in claim 1, characterized in that, it includes the following steps: Step 1, forming the test structure; Step 2, testing to form a first curve in which the breakdown voltage of the Zener diode forming the test structure varies with temperature; Step 3, turning on the FinFET, and the self-heating effect of the FinFET heats the fin body and raises the temperature of the fin body; Step 4, testing the breakdown voltage of the Zener diode and obtaining the temperature of the region of the fin body adjacent to the FinFET according to the first curve.

14. The test structure for the self-heating effect of the FinFET as described in claim 13, characterized in that: In step 1, the first wire type is N-type, the second conduction type is P-type, the first embedded epitaxial layer is an embedded SiP epitaxial layer, and the second embedded epitaxial layer is an embedded SiGe epitaxial layer; During the formation process, the first embedded epitaxial layer and the embedded SiP epitaxial layer of the source and drain regions of the N-type FinFET are grown simultaneously; The second embedded epitaxial layer and the embedded SiGe epitaxial layer of the source and drain regions of the P-type FinFET are grown simultaneously.

15. The test structure for the self-heating effect of the FinFET as described in claim 13, characterized in that: In step 1, the first wire type is P-type, the second conduction type is N-type, the first embedded epitaxial layer is an embedded SiGe epitaxial layer, and the second embedded epitaxial layer is an embedded SiP epitaxial layer; During the formation process, the first embedded epitaxial layer and the embedded SiGe epitaxial layers of the source and drain regions of the P-type FinFET are grown simultaneously. The second embedded epitaxial layer and the embedded SiP epitaxial layers of the source and drain regions of the N-type FinFET are grown simultaneously.

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