Semiconductor Device with Backside Power Rail and Method of Forming the Same

Abstract

The present disclosure relates to a semiconductor device having a back power rail and a method of forming the same. A method of manufacturing a semiconductor device includes: forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching source / drain (S / D) regions of the fin structure to form S / D recesses. The fin structure includes alternatingly stacked first and second semiconductor layers. The method further includes depositing an insulating dielectric layer in the S / D recesses, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing epitaxial S / D features in the S / D recesses. A bottom of the insulating dielectric layer is interposed between the epitaxial S / D features and the substrate.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices having a backside power rail and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous one. In the course of IC development, the functional density (i.e., the number of interconnected devices per chip area) has generally increased while the geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and decreasing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs.

[0003] In recent years, to improve gate control by enhancing gate-channel coupling, reduce off-state current, and reduce short-channel effects (SCEs), multi-gate devices have been introduced. One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The name FinFET is derived from the fin-like structure that extends from the substrate on which it is formed and is used to form the FET channel. Another multi-gate device that has been introduced to address performance challenges associated with FinFETs is the gate-all-around (GAA) transistor. The name GAA transistor is derived from the gate structure that can extend around the channel region, thereby providing control of the channel on four sides. The GAA transistor is compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and its structure allows it to be scaled up massively while maintaining gate control and mitigating SCEs.

[0004] Conventionally, multi-gate devices (e.g., FinFETs and GAA transistors) are constructed in a stacked manner, with transistors at the lowest level and interconnects (vias and wires) on top of the transistors to provide connections to the transistors. Power rails (e.g., metal lines for voltage sources and ground planes) are also located above the transistors and can be part of the interconnects. As integrated circuits continue to scale down, the power rails are also continuously scaled down. This inevitably leads to an increase in the voltage drop across the power rails and an increase in the power consumption of the integrated circuit. Thus, although existing methods in semiconductor manufacturing have been generally adequate for their intended purposes, they are not entirely satisfactory in all respects. An area of interest is how to form power rails and vias on the backside of an IC with reduced resistance and reduced coupling capacitance. Summary of the Invention

[0005] According to an embodiment of the present disclosure, a method of forming a semiconductor structure is provided, including: forming a sacrificial feature in a top portion of a substrate; forming a fin over the sacrificial feature; recessing the fin in a source / drain (S / D) region to form an S / D trench exposing the sacrificial feature; forming an S / D epitaxial feature in the S / D trench; removing a bottom portion of the substrate to expose the sacrificial feature from a back side of the substrate; and replacing the sacrificial feature with a conductive feature.

[0006] According to another embodiment of the present disclosure, a method of forming a semiconductor structure is provided, including: providing a structure having a front side and a back side, the structure including a substrate located at the back side of the structure and a fin located at the front side of the structure, wherein the substrate includes a sacrificial feature located under the fin, and wherein the fin includes a plurality of sacrificial layers and a plurality of channel layers arranged alternately; recessing the fin from the front side of the structure to expose the sacrificial feature in a source / drain (S / D) region; forming an S / D epitaxial feature over the sacrificial feature; thinning the structure from the back side of the structure until the sacrificial feature is exposed; etching the sacrificial feature from the back side of the structure to form a trench exposing the S / D epitaxial feature; depositing a conductive feature in the trench; and forming a metal wiring layer at the back side of the structure, wherein the metal wiring layer is electrically coupled to the S / D epitaxial feature through the conductive feature.

[0007] According to yet another embodiment of the present disclosure, a semiconductor structure is provided, including: a first source / drain (S / D) epitaxial feature and a second S / D epitaxial feature; one or more channel structures connecting the first S / D epitaxial feature and the second S / D epitaxial feature; a gate structure engaging the one or more channel structures, wherein the first S / D epitaxial feature and the second S / D epitaxial feature, the one or more channel structures and the gate structure are located at a front side of the semiconductor structure; a metal wiring layer located at a back side of the semiconductor structure; and a conductive feature connecting the metal wiring layer and the first S / D epitaxial feature, wherein the conductive feature extends to a position directly under the one or more channel structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, according to standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1A and Figure 1B FIG. shows a flowchart of an exemplary method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0010] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A and Figure 23A illustrate a perspective view of a semiconductor device constructed according to the method in Figure 1A and Figure 1B according to some embodiments of the present disclosure.

[0011] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B and Figure 23B illustrate a cross-sectional view perpendicular to the longitudinal direction of the channel structure of the semiconductor device in a corresponding perspective view during the manufacturing process of the method in Figure 1A and Figure 1B according to some embodiments of the present disclosure.

[0012] Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C, Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C , Figure 22C and Figure 23C show cross-sectional views along the longitudinal direction of the channel structure of a semiconductor device in corresponding perspective views during a manufacturing process of a method in accordance with Figure 1A and Figure 1B in accordance with some embodiments of the present disclosure.

[0013] Figure 24 , Figure 25 and Figure 26 show cross-sectional views along the longitudinal direction of the channel structure of a semiconductor device during a manufacturing process of a method in accordance with Figure 1A and Figure 1B in accordance with some alternative embodiments of the present disclosure.

[0014] Figure 27 shows a cross-sectional view perpendicular to the longitudinal direction of the channel structure of a semiconductor device during a manufacturing process of a method in accordance with Figure 1A and Figure 1B in accordance with yet another alternative embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed. Further, in the present disclosure below, forming another feature on a feature, a feature being connected to another feature, and / or being coupled to another feature may include embodiments in which these features are formed in direct contact, and may also include embodiments in which additional features are formed between these features such that these features are not in direct contact. Further, spatially relative terms (e.g., "lower", "upper", "horizontal", "vertical", "above", "over", "below", "beneath", "on", "under", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downward", "upward", etc.)) are used for ease of understanding the relationship of one feature to another feature of the present disclosure. Spatially relative terms are intended to cover different orientations of devices including the features. Still further, when a number or a range of numbers is described by "about", "approximate", etc., the term is intended to include numbers within a reasonable range including the described number, e.g., within + / - 10% of the described number or other values understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0017] The present disclosure generally relates to semiconductor fabrication of multi-gate transistors in semiconductor devices. As used herein, a semiconductor device refers to, for example, one or more transistors, integrated circuits, semiconductor chips (e.g., memory chips, logic chips on semiconductor dies), semiconductor chip stacks, semiconductor packages, semiconductor wafers, etc. The term "multi-gate transistor" refers to a transistor having (one or more) gate materials disposed on multiple sides of the channel structure of the transistor, such as a fin field-effect transistor (FinFET). In some examples, when (one or more) gate materials are disposed on at least four sides of the channel structure of the multi-gate transistor, the multi-gate transistor is referred to as a gate-all-around (GAA) transistor. The term "channel structure" is used herein to designate any material portion having nano-scale or even micro-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term designates elongated material portions having circular and substantially circular cross-sections, as well as bundle-shaped or bar-shaped material portions, such as those including cylindrical or substantially rectangular cross-sections. In some examples, the channel structure is referred to as a "nanowire", "nanosheet", etc., and the channel structure as used herein includes channel structures of various geometries (e.g., cylindrical, bar-shaped) and various sizes.

[0018] As the semiconductor industry moves further towards sub-10 nanometer (nm) technology process nodes in pursuit of higher device density, higher performance, and lower cost, the power rails in an IC need to be further improved to provide the required performance boost and reduce power consumption. The purpose of the present disclosure is to design power rails (or power wirings) on the backside (or back face) of a structure including transistors (e.g., GAA transistors and / or FinFET transistors), and an interconnect structure (which may also include power rails) on the front side (or front face) of the structure. This increases the number of metal tracks available in the structure for direct connection to source / drain (S / D) contacts and vias. This also increases the gate density, providing a greater degree of device integration compared to existing structures without backside power rails. The backside power rails can have a wider dimension than the first-level metal (M0) tracks on the front face of the structure, which advantageously reduces the resistance of the power rails. According to some embodiments, sacrificial (dummy) contact vias are formed on the backside of the wafer before forming the channel structure on the front face, and the sacrificial contact vias are replaced with conductive contact vias at a later processing stage (e.g., during the backside processing of the wafer). By forming the backside sacrificial contact vias, a large contact area can be retained between the S / D epitaxial features and the backside power rails, effectively reducing the contact resistance and improving device performance. Additionally, the embodiments disclosed herein provide significantly improved overlay control.

[0019] Details of the structure and manufacturing method of the present disclosure are described below with reference to the accompanying drawings, which illustrate the process of manufacturing a GAA transistor according to some embodiments. GAA transistors are promising candidates for taking CMOS to the next stage of the roadmap due to their better gate control capabilities, lower leakage currents, and full FinFET device layout compatibility. For simplicity, the present disclosure uses GAA transistors as an example. Those of ordinary skill in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures (e.g., FinFET devices) to achieve the same purpose and / or realize the same advantages of the embodiments introduced herein.

[0020] Figure 1A and Figure 1B A flowchart of a method 100 for manufacturing a semiconductor device according to various embodiments of the present disclosure is shown. The present invention contemplates additional processing. Additional operations may be provided before, during, and after method 100, and for additional embodiments of method 100, some of the described operations may be moved, replaced, or eliminated. Details are described below with reference to Figures 2A to 27 are described Figure 1A and Figure 1B , Figures 2A to 27Shows various top views and cross-sectional views of a semiconductor device (or device) 200 in various manufacturing steps according to method 100 in accordance with some embodiments. In some embodiments, device 200 is part of an IC chip, a system-on-chip (SoC), and includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate field-effect transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, memory devices, other suitable components, or combinations thereof. For a clearer understanding of the inventive concept of the present disclosure, Figures 2A to 27 is simplified. Additional features may be added to device 200, and some of the features described below may be replaced, modified, or eliminated in other embodiments of device 200.

[0021] In operation 102, method 100 ( Figure 1A ) provides device 200 having a substrate 202, as Figures 2A - 2C shown. Figure 2A A perspective view of device 200 is shown, and Figure 2B and Figure 2C respectively show cross-sectional views of portions of device 200 along Figure 2A lines A-A and B-B in Figures 3A to 27 . Specifically, line A-A is taken along the longitudinal direction (direction "Y" or Y-direction) of the gate structure to be formed, and line B-B is taken along the longitudinal direction (direction "X" or X-direction) of the semiconductor fin to be formed. The A-A line and B-B line in Figures 3A to 27 are similarly configured. In some embodiments, substrate 202 is a silicon-on-insulator (SOI) substrate, which may include a base semiconductor layer 204, a buried insulating layer 206, and an overlying semiconductor layer 208. Both the base semiconductor layer 204 and the overlying semiconductor layer 208 may include bulk single-crystalline silicon. In some embodiments, the buried insulating layer 206 is a buried oxide layer. Alternatively, the base semiconductor layer 204 and the overlying semiconductor layer 208 may include the same or different semiconductor compositions such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, InP, or combinations thereof.

[0022] In operation 104, method 100 ( Figure 1A ) forms a sacrificial (dummy) contact via feature 210 embedded in the overlying semiconductor layer 208, as Figures 3A - 3CAs shown. The sacrificial contact via feature 210 reserves space for the S / D contact via to be formed and its thickness is selected based on device performance considerations. In some embodiments, the sacrificial contact via feature 210 has a thickness ranging from about 10 nm to about 200 nm. The formation of the sacrificial contact via feature 210 may include a patterning process to form an opening in the overlying semiconductor layer 208 and then deposit a dielectric material in the opening. In some embodiments, the overlying semiconductor layer 208 is patterned using any suitable method such as a lithography process, which may include: forming a resist layer (not shown) on the device 200; exposing the resist layer through a lithography exposure process; performing a post-exposure bake process; developing the resist layer to form a patterned resist layer that exposes a portion of the overlying semiconductor layer 208; etching the overlying semiconductor layer 208 to form an opening that exposes the buried insulating layer 206; and finally removing the patterned resist layer. The lithography process may alternatively be replaced by other suitable techniques such as electron beam writing, ion beam writing, maskless patterning, or molecular printing. The dielectric material of the sacrificial contact via feature 210 can be deposited in the opening by: chemical vapor deposition (CVD), including low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD); physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. A planarization operation, such as a chemical mechanical polishing (CMP) process, may also be performed to remove the excess dielectric material to expose the top surface of the overlying semiconductor layer 208. The dielectric material is selected such that there is a high etch selectivity between the overlying semiconductor layer 208 and the sacrificial contact via feature 210. In some embodiments, the overlying semiconductor layer 208 includes silicon (Si), and the sacrificial contact via feature 210 includes SiN, SiC, SiOCN, SiOC, other silicon-derived materials, or metal oxides (e.g., Al2O3). In some embodiments, the length L0 of the sacrificial contact via feature 210 along the Y direction is in the range of about 40 nm to about 240 nm. In some embodiments, the width W0 of the sacrificial contact via feature 210 along the X direction is in the range of about 40 nm to about 120 nm.

[0023] In operation 106, method 100 ( Figure 1A ) forms an epitaxial stack 212 over the substrate 202, as Figures 4A - 4C shown. The epitaxial stack 212 includes an epitaxial layer 214 of a first composition interposed by an epitaxial layer 216 of a second composition. The first composition and the second composition may be different. In one embodiment, the epitaxial layer 214 is a SiGe layer and the epitaxial layer 216 is a Si layer. However, other embodiments may include providing layers of a first composition and a second composition having different oxidation rates and / or etch selectivities. Note that in Figures 4A - 4CFour (4) layers of each of the epitaxial layers 214 and 216 are shown, which are for illustrative purposes only and are not intended to limit what is specifically recited in the claims. It will be understood that any number of epitaxial layers may be formed in the epitaxial stack 212; the number of layers depends on the desired number of channel structures of the device 200. In some embodiments, the number of epitaxial layers 214 or epitaxial layers 216 is between 2 and 10, such as 3 or 5.

[0024] For example, the epitaxial growth of the epitaxial stack 212 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layer (e.g., epitaxial layer 216) includes the same material as the overlying semiconductor layer 208, such as Si. In some embodiments, either of the epitaxial layers 214 and 216 may include a material different from the overlying semiconductor layer 208. In further embodiments, either of the epitaxial layers 214 and 216 may include other materials, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. As discussed, the materials of the epitaxial layers 214 and 216 can be selected based on providing different oxidation and etching selectivity properties. As described above, in at least some examples, the epitaxial layer 214 includes an epitaxially grown SiGe layer with a Ge molar ratio in the range of about 10 - 55%, and the epitaxial layer 216 includes an epitaxially grown Si layer. In a further example, the bottommost epitaxial layer 214 may include a different Ge molar ratio from the other upper epitaxial layers 214. For example, the bottommost epitaxial layer 214 may include an epitaxially grown Si 1-x Ge x layer (e.g., x is about 10 - 15%), and the other upper epitaxial layers 214 may include an epitaxially grown Si 1-y Ge y layer (y > x, e.g., y is about 25 - 55%). In various embodiments, the epitaxial layers 214 and 216 are substantially free of dopants (i.e., having an extrinsic dopant concentration from about 0 cm -3 to about 1x10 17 cm -3 ), where, for example, no intentional doping is performed during the epitaxial growth process. In yet some alternative embodiments, the bottommost epitaxial layer 216 may have a higher impurity concentration than the other upper epitaxial layers 216, such as due to the formation of a bottom n-well and / or p-well.

[0025] In some embodiments, the epitaxial layer 214 has a thickness ranging from about 3 nm to about 6 nm. In further embodiments, the epitaxial layer 214 in the epitaxial stack 212 may be substantially uniform in thickness. In still some alternative embodiments, the bottommost epitaxial layer 214 may be thicker than the other upper epitaxial layers 214, for example, about 20% to about 50% thicker. In some embodiments, the epitaxial layer 216 has a thickness ranging from about 4 nm to about 12 nm. In further embodiments, the epitaxial layer 216 in the epitaxial stack 212 is substantially uniform in thickness. As described in more detail below, the epitaxial layer 216 serves as the channel structure of the subsequently formed multi-gate device, and the thickness is selected based on device performance considerations. The epitaxial layer 214 is used to reserve a pitch (or called a gap) between adjacent channel structures for the subsequently formed multi-gate device, and the thickness is also selected based on device performance considerations. Therefore, the epitaxial layer 214 is also referred to as the sacrificial layer 214, and the epitaxial layer 216 is also referred to as the channel layer 216 or the channel structure 216.

[0026] In addition, at operation 106, a mask layer 218 is formed over the epitaxial stack 212. In some embodiments, the mask layer 218 includes a first mask layer 218A and a second mask layer 218B. The first mask layer 218A is a pad oxide layer made of silicon oxide that can be formed by a thermal oxidation process. The second mask layer 218B is made of silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), including low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0027] At operation 108, the method 100 ( Figure 1A ) patterns the epitaxial stack 212 to form semiconductor fins 220 (also referred to as fins 220), as Figures 5A - 5CAs shown. In various embodiments, each fin 220 includes a top portion of the interleaved epitaxial layers 214 and 216 and a bottom portion formed by patterning the overlying semiconductor layer 208. The mask layer 218 is patterned into a mask pattern by using patterning operations including photolithography and etching. In some embodiments, operation 108 uses a suitable process including a double patterning or multiple patterning process to pattern the epitaxial stack 212. Generally, a double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing patterns to be created with a smaller pitch, for example, than would otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned material layer using a self-alignment process. The material layer is then removed, and the remaining spacers or mandrels can subsequently be used to pattern the epitaxial stack 212 in an etching process (e.g., dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes) through the openings defined in the patterned mask layer 218. An etchant is selected such that the buried insulating layer 206 and the sacrificial contact via features 210 remain substantially intact. Thus, the stacked epitaxial layers 214 and 216 and the overlying semiconductor layer 208 are patterned into fins 220 having trenches 222 therebetween.

[0028] Still referring to Figures 5A - 5C , each fin 220 projects upward in the Z direction above the buried insulating layer 206 and extends longitudinally in the X direction. In Figures 5A - 5CIn [the figure], two (2) fins 220 are spaced apart along the Y direction. However, the number of fins is not limited to two and can be as small as one or more than two. In some embodiments, one or more dummy fin structures (not shown) are formed on both sides of the fins 220 to improve pattern fidelity in the patterning operation. In some embodiments, the fin width W1 of the upper portion of the fins 220 along the Y direction is in the range of about 6 nm to about 40 nm. In some embodiments, the fin distance S1 between the opposing sidewalls of two adjacent fins 220 along the Y direction is in the range of about 36 nm to about 150 nm or even greater. In some embodiments, the fin pitch P1 (P1 = W1 + S1) of two adjacent fins 220 along the Y direction is in the range of about 40 nm to about 200 nm or even higher. In some embodiments, the height H1 of the fins 220 along the Z direction (measured from the exposed top surface of the buried insulating layer 206) is in the range of about 100 nm to about 200 nm. In some embodiments, the length L0 of the sacrificial contact via feature 210 along the Y direction is greater than the fin distance S1 but less than the sum of the fin pitch P1 and the fin width W1 (i.e., S1 < L0 < P1 + W1), for example, in one example, equal to one fin pitch P1 (e.g., L0 = P1), such that along the Y direction, each side end of the sacrificial contact via feature 210 is covered by one of the fins 220, while the central portion of the sacrificial contact via feature 210 is exposed in the trench 222. In some other embodiments, the length L0 of the sacrificial contact via feature 210 can be greater than the sum of the fin pitch P1 and the fin width W1 (i.e., L0 > P1 + W1), for example, in one example, equal to twice or multiple times the fin pitch P1 (e.g., L0 = n * P1, n = 2, 3,...), such that along the Y direction, each side end of the sacrificial contact via feature 210 protrudes from the fins 220 (as Figure 5B shown by the dashed rectangular box 210' in [the figure]). In other words, the two sidewalls of each fin 220 can be connected on the top surface of the sacrificial contact via feature 210. By comparison, referring to Figure 5C , in various embodiments, the width W0 of the sacrificial contact via feature 210 in the X direction is less than the length of the fins 220.

[0029] In operation 110, method 100 ( Figure 1A ) deposits a dielectric material in the trench 222 between adjacent fins 220 to form an isolation feature 224, as Figures 6A - 6CAs shown. The isolation feature 224 may include one or more dielectric layers. Suitable dielectric materials for the isolation feature 224 may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique including thermal growth, CVD, HDP-CVD, PVD, ALD, and / or spin coating techniques. Then, a planarization operation such as a CMP process is performed such that the upper surface of the topmost semiconductor layer 216 is exposed from the isolation feature 224. The isolation feature 224 is then recessed to form a shallow trench isolation (STI) feature (and thus also denoted as STI feature 224). Any suitable etching technique may be used to recess the isolation feature 224, including dry etching, wet etching, RIE, and / or other etching methods, and in an exemplary embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the isolation feature 224 without etching the fins 220. In some embodiments, the mask layer 218 is removed by a CMP process performed prior to recessing the isolation feature 224. In some embodiments, the mask layer 218 is removed by an etchant used to recess the isolation feature 224. In the illustrated embodiment, the STI feature 224 remains covering the sacrificial contact via feature 210. For example, in the illustrated embodiment, the top surface of the STI feature 224 may be between the top and bottom surfaces of the bottommost epitaxial layer 216. Alternatively, according to some other embodiments, the top surface of the STI feature 224 may be between the top and bottom surfaces of the bottommost epitaxial layer 214.

[0030] At operation 112, method 100 ( Figure 1A ) forms a sacrificial (dummy) gate structure 226, as Figures 7A - 7CAs shown. The sacrificial gate structure 226 is formed over a portion of the fin 220 that will become the channel region. The sacrificial gate structure 226 defines the channel region of the GAA transistor to be formed. Each sacrificial gate structure 226 includes a sacrificial gate dielectric layer 228 and a sacrificial gate electrode layer 230. The sacrificial gate structure 226 is formed by first depositing the sacrificial gate dielectric layer 228 with a uniform thickness over the fin 220. Then, the sacrificial gate electrode layer 230 is deposited over the sacrificial gate dielectric layer 228 and over the fin 220. The sacrificial gate electrode layer 230 includes silicon such as polysilicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer 228 is in the range of about 1 nm to about 5 nm. In some embodiments, the thickness of the sacrificial gate electrode layer 230 is in the range of about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer 230 undergoes a planarization operation. The sacrificial gate dielectric layer 228 and the sacrificial gate electrode layer 230 can be deposited using CVD (including LPCVD and PECVD, PVD, ALD, or other suitable processes). Subsequently, a mask layer 232 is formed over the sacrificial gate electrode layer. The mask layer 232 can include a liner oxide layer 232A and a silicon nitride mask layer 232B. Subsequently, a patterning operation is performed on the mask layer 232, and the sacrificial gate dielectric and electrode layers are patterned into the sacrificial gate structures 226. By patterning the sacrificial gate structures 226, the fins 220 are partially exposed on opposite sides of the sacrificial gate structures 226, thereby defining the S / D regions. In this via, the source and drain can be used interchangeably and their structures are substantially the same.

[0031] In the illustrated embodiment, two (2) sacrificial gate structures 226 are formed, but the number of sacrificial gate structures 226 is not limited to one, two, or more sacrificial gate structures, and these sacrificial gate structures are arranged along the X direction. In some embodiments, the gate width W2 of the upper portion of the sacrificial gate structure 226 along the X direction is in the range of about 20 nm to about 100 nm. In some embodiments, the gate distance S2 between the opposing sidewalls of two adjacent sacrificial gate structures 226 along the X direction is in the range of about 20 nm to about 150 nm. In some embodiments, the gate pitch P2 (P2 = W2 + S2) of two adjacent sacrificial gate structures 226 along the X direction is in the range from about 40 nm to about 250 nm. In some embodiments, the width W0 of the sacrificial contact via feature 210 in the X direction is greater than the gate distance S2, but less than the sum of the gate pitch P2 and the gate width W2 (i.e., S2 < W0 < P2 + W2), for example, in one example, it is equal to one gate pitch P2 (e.g., W0 = P2), such that along the X direction, each side end of the sacrificial contact via feature 210 is located directly below one of the sacrificial gate structures 226. In some other embodiments, the width W0 of the sacrificial contact via feature 210 may be greater than the sum of the gate pitch P2 and the gate width W2 (i.e., W0 > P2 + W2), for example, in one example, it is equal to twice or more times the gate pitch P2 (e.g., W0 = n*P2, n = 2, 3, …), such that along the X direction, each side end of the sacrificial contact via feature 210 protrudes from the sacrificial gate structure 226 (as Figure 7C shown by the dashed rectangular box 210” in

[0032] . In other words, the two sidewalls of each sacrificial gate structure 226 may be located directly above the top surface of the sacrificial contact via feature 210.

[0032] In operation 114, method 100 ( Figure 1A ) forms gate spacers 234 on the sidewalls of the sacrificial gate structures 226, as Figures 8A - 8CAs shown. The gate spacer 234 may also cover the sidewalls of the fins 220, and for this portion of the gate spacer, these sidewalls are referred to as fin spacers 234'. The gate spacer 234 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon carbon oxide, SiOCN film, and / or combinations thereof. In some embodiments, the gate spacer 234 includes multiple layers, such as a main spacer wall, a liner layer, etc. For example, the gate spacer 234 may be formed by conformally depositing a dielectric material layer with a uniform thickness over the sacrificial gate structure 226 using a process such as a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable processes. In the illustrated embodiment, after depositing the dielectric material layer, a re-etching (e.g., anisotropically) process is performed to remove the dielectric material layer from the horizontal surfaces and expose the top surface of the sacrificial gate structure 226 and the top surfaces of the fins 220 adjacent to but not covered by the sacrificial gate structure 226 (e.g., the S / D regions). The dielectric material layer may remain on the sidewalls of the sacrificial gate structure 226 as the gate spacer 234 (and / or on the sidewalls of the fins 220 as the fin spacer 234'). In some embodiments, the re-etch process may include a wet etching process, a dry etching process, a multi-step etching process, and / or combinations thereof. According to some embodiments, the gate spacer 234 may have a thickness between about 5 nm and about 20 nm.

[0033] Still referring to Figures 8A - 8C , at operation 116, method 100 ( Figure 1A ) depresses portions of the fins 220 to form S / D trenches (recesses) 236 in the S / D regions. The stacked epitaxial layers 214 and 216 are etched downward at the S / D regions. In many embodiments, operation 116 forms the S / D trenches 236 by a suitable etching process (e.g., a dry etching process, a wet etching process, or an RIE process). The etching process of operation 116 may implement a dry etching process using an etchant including a bromine-containing gas (e.g., HBr and / or CHBR3), a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), other suitable gases, or combinations thereof. The etchant is selected such that the overlying semiconductor layer 208, the sacrificial contact via features 210, and the STI features 224 remain substantially intact and are exposed in the S / D trenches 236.

[0034] At operation 118, method 100 ( Figure 1A ) laterally etches the ends of the epitaxial layer 214, thereby forming a cavity 238, as Figures 9A - 9CAs shown. In some embodiments, the amount of etching of the epitaxial layer 214 ranges from about 1 nm to about 4 nm. The epitaxial layer 214 can be selectively etched by using a wet etchant (such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution). Alternatively, operation 118 can first selectively oxidize the side ends of the epitaxial layer 214 exposed in the S / D trenches 236 to increase the etching selectivity between the epitaxial layers 214 and 216. In some examples, the oxidation process can be performed by exposing the device 200 to a wet oxidation process, a dry oxidation process, or a combination thereof. Additionally, as described above, during the formation of the bottommost epitaxial layer 214, it can include a different Ge molar ratio (e.g., smaller) than other upper epitaxial layers 214, and the selective etching process can be tuned to have a higher etching rate for the upper epitaxial layer 214, thereby restricting the cavity 238 from forming as a recessed side end adjacent to the upper epitaxial layer 214 rather than the bottommost end, as shown in the illustrated embodiment.

[0035] In operation 120, method 100 ( Figure 1A ) forms an internal spacer 240 on the recessed side ends of the upper epitaxial layer 214, as Figures 10A - 10C shown. By way of example, operation 120 can include depositing a layer of internal spacer material uniformly in the S / D trenches 236. Specifically, the layer of internal spacer material is deposited on the recessed side ends of the upper epitaxial layer 214 exposed in the cavity 238, and on the sidewalls of the bottommost epitaxial layer 214 and the epitaxial layer 216 exposed in the S / D recesses 236. The layer of internal spacer material can include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon carbonitride oxide, and / or other suitable dielectric materials. In some embodiments, the layer of internal spacer material is deposited as a conformal layer with a substantially uniform thickness on different surfaces. The layer of internal spacer material can be formed by ALD or any other suitable method. By conformally forming the layer of internal spacer material, the volume of the cavity 238 is reduced or completely filled. After depositing the layer of internal spacer material, an etching operation is performed to partially remove the layer of internal spacer material from the S / D trenches 236. Specifically, the layer of internal spacer material is removed from the sidewalls of the bottommost epitaxial layer 214 and the epitaxial layer 216. By this etching, due to the small volume of the cavity, the layer of internal spacer material remains substantially within the cavity 238. Generally, plasma dry etching etches layers in wide and flat regions faster than layers in concave (e.g., holes, trenches, and / or slits) portions. Therefore, the layer of internal spacer material can remain inside the cavity 238. The remaining portion of the layer of internal spacer material within the cavity 238 provides isolation between the metal gate structure to be formed and the S / D epitaxial features to be formed, and this isolation is referred to as the internal spacer 240.

[0036] At operation 122, method 100( Figure 1A ) removes the bottommost epitaxial layer 214, as Figures 11A - 11C shown. In some embodiments, the bottommost epitaxial layer 214 is removed from the S / D trench 236 in a selective etching process, while the epitaxial layer 216, the inner spacer 240, the overlying semiconductor layer 208, and the sacrificial contact via feature 210 remain substantially intact. The selective etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0037] At operation 124, method 100( Figure 1B ) forms a self-aligned contact (SAC) layer 242 beneath the bottommost epitaxial layer 216 and fills the space formed by removing the bottommost epitaxial layer 214 in operation 122, as Figures 12A - 12C shown. The SAC layer 242 can include silicon oxide (SiO2), aluminum oxide (Al2O3), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or silicon carbon oxynitride (SiCON). According to some embodiments, the SAC layer 242 can include the same or a different dielectric material composition as the inner spacer 240. Generally, the compositions of the SAC layer 242 and the sacrificial contact via feature 210 are selected such that there is a high etch selectivity between them. As will be discussed further in detail below, the SAC layer 242 serves as an etch stop layer during an etching process for later removing the sacrificial contact via feature 210. In some embodiments, the SAC layer 242 is first deposited in the S / D trench 236 using CVD, PVD, ALD, or other suitable processes to fill the space beneath the bottommost epitaxial layer 216 and above the sidewalls of the S / D trench 236. Subsequently, a etch-back process is performed to remove portions of the SAC layer 242 from the sidewalls of the S / D trench 236, while other portions of the SAC layer 242 beneath the bottommost epitaxial layer 216 remain. Any suitable etching technique can be used to partially remove the SAC layer 242 from the S / D trench 236, including dry etching, wet etching, RIE, and / or other etching methods, and in an exemplary embodiment, anisotropic dry etching is used.

[0038] At operation 126, method 100( Figure 1B ) forms S / D epitaxial features 244 in the S / D trench 236, as Figures 13A - 13CAs shown. In some embodiments, the S / D epitaxial feature 244 includes epitaxially grown semiconductor material, such as epitaxially grown silicon, germanium, or silicon germanium. The S / D epitaxial feature 244 can be formed by any epitaxial process including chemical vapor deposition (CVD) techniques (e.g., vapor phase epitaxy and / or ultra-high vacuum CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The S / D epitaxial feature 244 can be doped with n-type dopants and / or p-type dopants. In some embodiments, for an n-type transistor, the S / D epitaxial feature 244 includes silicon and can be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., to form a Si:C S / D epitaxial feature, a Si:P S / D epitaxial feature, or a Si:C:P S / D epitaxial feature). In some embodiments, for a p-type transistor, the S / D epitaxial feature 244 includes silicon germanium or germanium and can be doped with boron, other p-type dopants, or combinations thereof (e.g., to form a Si:Ge:B S / D epitaxial feature). The S / D epitaxial feature 244 can include multiple epitaxial semiconductor layers having different doping density levels. In some embodiments, an annealing process (e.g., rapid thermal annealing (RTA) and / or laser annealing) is performed to activate the dopants in the S / D epitaxial feature 244.

[0039] At operation 128, method 100 ( Figure 1B ) forms a contact etch stop layer (CESL) 246 over the S / D epitaxial feature 244 and forms an interlayer dielectric (ILD) layer 248 over the CESL layer 246, as Figures 14A - 14C shown. The CESL layer 246 can include silicon nitride, silicon oxynitride, silicon nitride containing oxygen (O) or carbon (C) elements, and / or other materials; and can be formed by CVD, PVD (physical vapor deposition), ALD, or other suitable methods. The ILD layer 248 can include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 248 can be formed by PECVD or FCVD (flowable CVD) or other suitable methods. In some embodiments, forming the ILD layer 248 further includes performing a CMP process to planarize the top surface of the device 200, thereby removing the mask layer 232 over the top portion of the sacrificial gate structure 226.

[0040] Still referring to Figures 14A - 14C , at operation 130, method 100 ( Figure 1B)Replace the sacrificial gate structure 226 with a metal gate structure 250. For example, operation 130 may first remove the sacrificial gate structure 226 to form a gate trench in an etching process (e.g., plasma dry etching and / or wet etching). The gate trench exposes the epitaxial layers 214 and 216 in the channel region. Operation 130 then releases the channel structure from the channel region. In the illustrated embodiment, the channel structure is the epitaxial layer 216 in the form of a nanosheet. In this embodiment, the epitaxial layer 216 comprises silicon, and the epitaxial layer 214 comprises silicon germanium. The epitaxial layer 214 may be selectively removed. In some embodiments, the selective removal process includes oxidizing the epitaxial layer 214 using a suitable oxidant such as ozone. Thereafter, the oxidized epitaxial layer 214 may be selectively removed from the gate trench. To further implement this embodiment, operation 130 includes a dry etching process for selectively removing the epitaxial layer 214, for example, by applying HCl gas at a temperature of about 500 °C to about 700 °C, or by applying a gas mixture of CF4, SF6, and CHF3. For simplicity and clarity, after the channel structure is released, the epitaxial layer 216 is denoted as the channel structure 216. Subsequently, operation 130 forms a metal gate structure 250 in the gate trench, surrounding each channel structure 216 in the channel region. The inner spacer 240 separates the metal gate structure 250 from the S / D epitaxial features 244.

[0041] The metal gate structure 250 includes a gate dielectric layer 252 surrounding each channel structure 216 in the channel region and a gate electrode layer 254 formed on the gate dielectric layer 252. In some embodiments, the gate dielectric layer 252 includes one or more dielectric materials, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium dioxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 252 includes an interface layer formed between the channel structure and the high-k dielectric material. The gate dielectric layer 252 can be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 252 is formed using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer of uniform thickness is formed around each channel layer. The gate electrode layer 254 is formed on the gate dielectric layer 252 to surround each channel structure 216. The gate electrode layer 254 includes one or more conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 256 can be formed by CVD, ALD, electroplating, or other suitable methods. In certain embodiments of the present disclosure, one or more work function adjustment layers are inserted between the gate dielectric layer and the gate electrode layer. The work function adjustment layer is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multi-layer composed of two or more of these materials. For n-channel FETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for p-channel FETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer. The work function adjustment layer can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Additionally, the work function adjustment layer can be formed separately for n-type transistors and p-type transistors that can use different metal layers.

[0042] In operation 132, method 100( Figure 1B ) forms one or more interconnect layers 260, where contacts, vias, and wires are embedded in a dielectric layer, as Figures 15A - 15CAs shown. One or more interconnect layers 260 connect the gates, source and drain electrodes of various transistors and other circuits in device 200 to partially or fully form an integrated circuit. In some embodiments, operation 132 includes performing one or more middle-of-line (MEOL) and back-end-of-line (BEOL) processes. This can include: forming metal contact plugs (e.g., Figure 24 the metal contact plug 288 in

[0043] ) to source / drain features, additional etch stop layers (e.g., etch stop layer 262) and ILD layer formation (e.g., ILD layer 264), forming gate contact vias (e.g., gate contact via 266) and source / drain contact vias (not shown), forming an inter-metal dielectric (IMD) layer (e.g., IMD layer 268), metal lines (e.g., metal line 270), contact pads (not shown), etc. Device 200 may also include a passivation layer (e.g., passivation layer 272) and / or other layers built on the front side of device 200. These layers and one or more interconnect layers are collectively denoted by reference numeral 260. Figure 1B ) attaches the front side of device 200 to a carrier 274, as Figures 16A - 16C shown. In some embodiments, carrier 370 may be a silicon wafer. Operation 134 may use any suitable attachment process, such as direct bonding, hybrid bonding, using an adhesive, or other bonding methods. In the illustrated embodiment, an adhesive layer 276 is formed on the front side of device 200, and carrier 370 is adjacent to the front side of device 200. Operation 134 may also include alignment, annealing, and / or other processes. Attachment of carrier 274 allows device 200 to be flipped upside down. This enables access to device 200 from the back side of device 200 for further processing. Note that in Figures 17A - 17C , device 200 is flipped upside down.

[0044] In operation 136, method 100 ( Figure 1B ) thins device 200 from the back side of device 200 until the buried insulating layer 206 is exposed from the back side of device 200, as Figures 18A - 18C shown. The thinning process may include a mechanical grinding process and / or a chemical thinning process. A large amount of the substrate semiconductor layer 204 may first be removed from the substrate 202 during the mechanical grinding process. Thereafter, the chemical thinning process may apply an etch chemical to the back side of the substrate 202 to completely remove the substrate semiconductor layer 204 to expose the buried insulating layer 206.

[0045] In operation 138, method 100 ( Figure 1B ) further thins device 200 from the back side of device 200 until the sacrificial contact via features 210 are exposed from the back side of device 200, as Figures 19A - 19CAs shown. Similar to operation 136, the thinning process can include a mechanical grinding process and / or a chemical thinning process. A large amount of the buried insulating layer 206 can be first removed from the substrate 202 during the mechanical grinding process. Subsequently, the chemical thinning process can apply an etching chemical to the back surface of the substrate 202 to completely remove the buried insulating layer 206 to expose the buried insulating layer 206, the overlying semiconductor layer 208, and the STI features 224.

[0046] In operation 140, method 100 ( Figure 1B ) selectively etches the sacrificial contact via features 210 to form trenches 280 over the back surface of the S / D epitaxial features 244, as Figures 20A - 20C shown. The trenches 280 expose the surfaces of the overlying semiconductor layer 208, the STI features 224, the SAC layer 242, and the S / D epitaxial features 244 from the back surface. In some embodiments, operation 140 applies an etching process that is tuned to be selective to the materials in the sacrificial contact via features 210 (e.g., silicon-derived materials or metal oxides), and has no (or minimal) etching on the overlying semiconductor layer 208, the STI features 224, the SAC layer 242, and the S / D epitaxial features 244. In the illustrated embodiment, the exposed surfaces of the SAC layer 242 and the S / D epitaxial features 244 are substantially horizontal. In an alternative embodiment, the etching process also etches the S / D epitaxial features 244 to recess the exposed surface below the level of the exposed surface of the SAC layer 242. In yet another alternative embodiment, the etching process also etches the SAC layer 242 to recess its exposed surface below the level of the exposed surface of the S / D epitaxial features 244 such that the S / D epitaxial features 244 protrude from the SAC layer 242. Operation 108 can apply more than one etching process. For example, operation 108 can apply a first etching process to selectively remove the sacrificial contact via features 210, and then apply a second etching process to selectively recess the S / D epitaxial features 244 to a desired level or selectively recess the SAC layer 242 to a desired level, where the first etching process and the second etching process use different etching parameters, such as using different etchants. The (one or more) etching processes can be dry etching, wet etching, reactive ion etching, or other etching methods.

[0047] In operation 142, method 100 ( Figure 1B ) forms backside conductive contact vias 282 in the trenches 280 formed by removing the sacrificial contact via features 210, as Figures 21A - 21CAs shown. The backside conductive contact via 282 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, electroplating, or other suitable processes. In the illustrated embodiment, the backside conductive contact via 282 directly contacts the S / D epitaxial feature 244. Alternatively, in one embodiment, operation 142 optionally forms a silicide feature (not shown) between the S / D epitaxial feature 244 and the backside conductive contact via 282 to further reduce the contact resistance. In a further embodiment, operation 142 first deposits one or more metals into the trench 280, performs an annealing process on the device 200 to react the one or more metals with the S / D epitaxial feature 244 to produce a silicide feature, and removes the unreacted portions of the one or more metals, leaving the silicide feature in the trench 280. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals), and the one or more metals may be deposited using CVD, PVD, ALD, or other suitable methods. The silicide feature may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), a combination thereof, or other suitable compounds.

[0048] In operation 144, method 100 ( Figure 1B ) forms one or more backside interconnect layers 284, with backside power rails embedded in a dielectric layer on the backside of the device 200. According to an embodiment, the resulting structure is shown in Figures 22A - 22C . The backside power rails are electrically connected to the backside conductive contact vias 282. In one embodiment, the backside power rails may be formed using a damascene process, a dual damascene process, a metal patterning process, or other suitable processes. The backside power rails may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be deposited by CVD, PVD, ALD, electroplating, or other suitable processes. Although Figures 22A - 22CAlthough not shown, the backside power rails may include contacts, vias, wires, and / or other conductive features. Having backside power rails beneficially increases the number of metal tracks available in device 200 for direct connection to source / drain contacts and vias (including backside conductive contact vias 282). The backside power rails may have a wider dimension than the first-level metal (M0) tracks on the front side of device 200, which is beneficial for reducing the backside power rail resistance. By forming sacrificial contact via features before forming the active regions (e.g., fins), a relatively large contact area can be retained between the S / D epitaxial features and the power rails, thus effectively further reducing the contact resistance and improving device performance. Additionally, the relatively large contact area provides better overlay control between the vias and the contact structures. Note that although the resulting structure as shown in Figures 22A - 22C does not show other S / D contacts (or contact plugs) on the front side of device 200, in various other embodiments, such metal features (e.g., Figure 24 the metal contact plug 288 shown in

[0049] Now referring to Figures 23A - 23C , Figures 23A - 23C shows an alternative embodiment of the structure resulting after operation 144. Some of the processes and materials used to form semiconductor device 200 may be similar to those previously described in connection with Figures 1A - 22CThe processes and materials described or the same as them are not repeated here. One difference is that the overlying semiconductor layer 208 adjacent to the backside conductive contact via 282 is replaced with a dielectric layer 286. By replacing the semiconductor material in the overlying semiconductor layer 208 with a dielectric material, the isolation between the S / D epitaxial features 244 and the backside interconnect layer 284 is improved, which in turn suppresses the backside leakage current and improves the TDDB (time-dependent dielectric breakdown) performance of the IC. In some embodiments, the dielectric material in the dielectric layer 286 includes silicon oxide (SiO2), aluminum oxide (Al2O3), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or silicon carbon oxynitride (SiCON). In further embodiments, the dielectric layer 286 and the SAC layer 242 may include the same material composition in one example or different material compositions in another example. In various embodiments, forming the dielectric layer 286 may include removing the overlying semiconductor layer 208 in a selective etching process after operation 138 of exposing the overlying semiconductor layer 208 in a backside thinning process to form a trench, and then depositing a dielectric material in the trench by ALD, PVD, CVD, or other suitable processes. Subsequently, method 100 proceeds to operation 140, i.e., removing the sacrificial contact via feature 210 after forming the dielectric layer 286.

[0050] Now refer to Figure 25 。 Figure 25 FIG. shows a cross-sectional view along line B-B of yet another alternative embodiment of the structure resulting after operation 144. Some of the processes and materials used to form the semiconductor device 200 may be similar to or the same as those previously described in connection with Figures 1A - 22C The processes and materials described or the same as them are not repeated here. One difference is that the S / D epitaxial features 244 protrude from the SAC layer 242 and extend (embed) into the backside conductive contact via 282. As discussed above in connection with operation 140, the protruding portion of the S / D epitaxial feature can be formed by recessing the SAC layer 242 in one or more etching processes during or after forming the trench 280 ( Figures 20A - 20C ). The (one or more) etching processes can be dry etching, wet etching, reactive ion etching, or other etching methods.

[0051] Now refer to Figure 26 。 Figure 26 FIG. shows a cross-sectional view along line B-B of yet another alternative embodiment of the structure resulting after operation 144. Some of the processes and materials used to form the semiconductor device 200 may be similar to or the same as those previously described in connection with Figures 1A - 22CThe processes and materials described or the same as them are not repeated here. One difference is that the S / D epitaxial feature 244 is recessed below the SAC layer 242 such that the backside conductive contact via 282 protrudes into the SAC layer 242. As discussed above in connection with operation 140, the protruding portion of the backside conductive contact via 282 can be formed by recessing the S / D epitaxial feature 244 in one or more etching processes during or after the formation of the trench 280 ( Figures 20A - 20C ). The (one or more) etching processes can be dry etching, wet etching, reactive ion etching, or other etching methods.

[0052] Now refer to Figure 27 . Figure 27 FIG. shows a cross-sectional view along line A-A of yet another alternative embodiment of the structure resulting after operation 144. Some of the processes and materials used to form the semiconductor device 200 can be similar to or the same as those previously described in connection with Figures 1A - 22C . The processes and materials described or the same as them are not repeated here. One difference is that the bottom surface of the S / D epitaxial feature 244 is fully connected to the backside conductive contact via 282, rather than partially on the backside conductive contact via 282 and partially on the overlying semiconductor layer 208 ( Figure 22B ) or the dielectric layer 286 ( Figure 23B ). As discussed above in connection with operation 108, the length L0 of the sacrificial contact via feature 210 along the Y direction (and thus the length of the backside conductive contact via 282) can be greater than the sum of the fin pitch P1 and the fin width W1 (as shown by the dashed rectangular box 210' in Figure 5B ), for example, in one example equal to twice or more than twice the fin pitch P1 (e.g., L0 = n*P1, n = 2, 3,...), such that the two sidewalls of each fin 220 (and thus the S / D epitaxial feature 244) can be connected to the top surface of the sacrificial contact via feature 210 (and thus the backside conductive contact via 282).

[0053] In operation 146, the method 100 ( Figure 1B ) performs further manufacturing processes on the device 200. For example, it can form one or more interconnect layers on the backside of the device 200, form a passivation layer on the backside of the device 200, perform other BEOL processes, and remove the carrier 274.

[0054] Although not intended to be limiting, embodiments of the present via provide one or more of the following advantages. For example, embodiments of the present invention form a sacrificial (dummy) contact via feature on the backside of the wafer before forming a channel structure on the front side. This advantageously preserves a relatively large contact area to form a conductive contact via between the source / drain epitaxial feature and the backside power rail, which reduces contact resistance and improves device performance. Additionally, embodiments of the present disclosure form a backside wiring layer, such as a backside power rail, to increase the number of metal tracks available in the integrated circuit and increase the gate density to enable greater device integration. Embodiments of the present disclosure can be easily integrated into existing semiconductor manufacturing processes.

[0055] In one exemplary aspect, the present disclosure relates to a method. The method includes: forming a sacrificial feature in a top portion of a substrate; forming a fin over the sacrificial feature; recessing the fin in a source / drain (S / D) region to form an S / D trench exposing the sacrificial feature; forming an S / D epitaxial feature in the S / D trench; removing a bottom portion of the substrate to expose the sacrificial feature from the backside of the substrate; and replacing the sacrificial feature with a conductive feature. In some embodiments, replacing the sacrificial feature with the conductive feature includes: removing the sacrificial feature in a selective etch process to form a trench exposing the S / D epitaxial feature, and depositing the conductive feature in the trench. In some embodiments, the trench also exposes a top portion of the substrate, and wherein replacing the sacrificial feature with the conductive feature further includes: removing the top portion of the substrate from the trench before removing the sacrificial feature, and depositing a dielectric layer adjacent to the sacrificial feature. In some embodiments, the conductive feature is in physical contact with the S / D epitaxial feature. In some embodiments, the substrate includes a buried insulating layer, and wherein forming the sacrificial feature includes: patterning a top portion of the substrate to form an opening exposing the buried insulating layer, and depositing the sacrificial feature in the opening to cover the buried insulating layer. In some embodiments, removing the bottom portion of the substrate includes removing the buried insulating layer. In some embodiments, the top portion of the substrate includes an overlying semiconductor layer, and wherein the fin has a first sidewall directly above the overlying semiconductor layer and a second sidewall directly above the sacrificial feature. In some embodiments, the fin has a first sidewall and a second sidewall, both of which are directly above the sacrificial feature. In some embodiments, the method further includes: removing a bottom portion of the fin; and forming an etch stop layer stacked between the fin and the sacrificial feature, and the conductive feature is in physical contact with the etch stop layer.

[0056] In another exemplary aspect, the present disclosure relates to a method. The method includes: providing a structure having a front side and a back side, the structure including a substrate located on the back side of the structure and fins located on the front side of the structure, wherein the substrate includes sacrificial features located under the fins, and wherein the fins include a plurality of sacrificial layers and a plurality of channel layers arranged alternately; recessing the fins from the front side of the structure to expose the sacrificial features in source / drain (S / D) regions; forming S / D epitaxial features over the sacrificial features; thinning the structure from the back side of the structure until the sacrificial features are exposed; etching the sacrificial features from the back side of the structure to form trenches exposing the S / D epitaxial features; depositing conductive features in the trenches; and forming a metal wiring layer on the back side of the structure, wherein the metal wiring layer is electrically coupled to the S / D epitaxial features through the conductive features. In some embodiments, the substrate includes a semiconductor layer surrounding the sacrificial features, and wherein thinning the structure also exposes the semiconductor layer. In some embodiments, the method further includes: depositing isolation features on the front side of the structure, the isolation features covering the sacrificial features and bottom portions of sidewalls of the fins, wherein the trenches also expose the isolation features. In some embodiments, a top surface of the isolation features is higher than a top surface of the bottommost sacrificial layer. In some embodiments, the method further includes: removing the bottommost sacrificial layer from the fins to form an opening between the fins and the sacrificial features; and depositing a dielectric layer in the opening. In some embodiments, the trenches also expose the dielectric layer. In some embodiments, the method further includes: recessing the dielectric layer from the back side of the structure such that a portion of the S / D epitaxial features protrudes from the recessed dielectric layer.

[0057] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a first source / drain (S / D) epitaxial feature and a second S / D epitaxial feature; one or more channel structures connecting the first S / D epitaxial feature and the second S / D epitaxial feature; a gate structure engaging the one or more channel structures, wherein the first S / D epitaxial feature, the second S / D epitaxial feature, the one or more channel structures, and the gate structure are located on a front side of the semiconductor structure; a metal wiring layer located on a back side of the semiconductor structure; and a conductive feature connecting the metal wiring layer and the first S / D epitaxial feature, wherein the conductive feature extends to a position directly below the one or more channel structures. In some embodiments, a bottom surface of the first S / D epitaxial feature partially contacts the conductive feature. In some embodiments, a portion of the first S / D epitaxial feature is embedded in the conductive feature. In some embodiments, the conductive feature is a first conductive feature, and further includes: in some embodiments, a second conductive feature is in physical contact with the second S / D epitaxial feature.

[0058] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations therein without departing from the spirit and scope of the present disclosure.

[0059] Example 1 is a method of forming a semiconductor structure, including: forming a sacrificial feature in a top portion of a substrate; forming a fin over the sacrificial feature; recessing the fin in a source / drain (S / D) region to form an S / D trench exposing the sacrificial feature; removing a bottom portion of the substrate to expose the sacrificial feature from a back side of the substrate; and replacing the sacrificial feature with a conductive feature.

[0060] Example 2 is the method of Example 1, wherein replacing the sacrificial feature with the conductive feature includes: removing the sacrificial feature in a selective etching process to form a trench exposing the S / D epitaxial feature, and depositing the conductive feature in the trench.

[0061] Example 3 is the method described in Example 2, wherein the trench also exposes a top portion of the substrate, and wherein replacing the sacrificial feature with the conductive feature further comprises: removing the top portion of the substrate from the trench before removing the sacrificial feature, and depositing a dielectric layer adjacent to the sacrificial feature.

[0062] Example 4 is the method described in Example 1, wherein the conductive feature is in physical contact with the S / D epitaxial feature.

[0063] Example 5 is the method described in Example 1, wherein the substrate comprises a buried insulating layer, and wherein forming the sacrificial feature comprises: patterning a top portion of the substrate to form an opening exposing the buried insulating layer, and depositing the sacrificial feature in the opening to cover the buried insulating layer.

[0064] Example 6 is the method described in Example 5, wherein removing the bottom portion of the substrate comprises: removing the buried insulating layer.

[0065] Example 7 is the method described in Example 1, wherein the top portion of the substrate comprises an overlying semiconductor layer, and wherein the fin has a first sidewall directly above the overlying semiconductor layer and a second sidewall directly above the sacrificial feature.

[0066] Example 8 is the method described in Example 1, wherein the fin has a first sidewall and a second sidewall, both directly above the sacrificial feature.

[0067] Example 9 is the method described in Example 1, further comprising: removing a bottom portion of the fin; and forming an etch stop layer stacked between the fin and the sacrificial feature, wherein the conductive feature is in physical contact with the etch stop layer.

[0068] Example 10 is a method of forming a semiconductor structure, comprising: providing a structure having a front side and a back side, the structure comprising a substrate located on the back side of the structure and a fin located on the front side of the structure, wherein the substrate comprises a sacrificial feature located under the fin, and wherein the fin comprises a plurality of sacrificial layers and a plurality of channel layers arranged alternately; recessing the fin from the front side of the structure to expose the sacrificial feature in a source / drain (S / D) region; forming an S / D epitaxial feature over the sacrificial feature; thinning the structure from the back side of the structure until the sacrificial feature is exposed; etching the sacrificial feature from the back side of the structure to form a trench exposing the S / D epitaxial feature; depositing a conductive feature in the trench; and forming a metal wiring layer on the back side of the structure, wherein the metal wiring layer is electrically coupled to the S / D epitaxial feature through the conductive feature.

[0069] Example 11 is the method described in Example 10, wherein the substrate includes a semiconductor layer surrounding the sacrificial feature, and wherein thinning the structure also exposes the semiconductor layer.

[0070] Example 12 is the method described in Example 10, further comprising: depositing an isolation feature on a front side of the structure, the isolation feature covering the sacrificial feature and a bottom portion of sidewalls of the fin, wherein the trench also exposes the isolation feature.

[0071] Example 13 is the method described in Example 12, wherein a top surface of the isolation feature is higher than a top surface of a bottommost sacrificial layer.

[0072] Example 14 is the method described in Example 10, further comprising: removing a bottommost sacrificial layer from the fin to form an opening between the fin and the sacrificial feature; and depositing a dielectric layer in the opening.

[0073] Example 15 is the method described in Example 14, wherein the trench also exposes the dielectric layer.

[0074] Example 16 is the method described in Example 14, further comprising: recessing the dielectric layer from a back side of the structure such that a portion of the S / D epitaxial feature protrudes from the recessed dielectric layer.

[0075] Example 17 is a semiconductor structure, comprising: a first source / drain (S / D) epitaxial feature and a second S / D epitaxial feature; one or more channel structures connecting the first S / D epitaxial feature and the second S / D epitaxial feature; a gate structure engaging the one or more channel structures, wherein the first S / D epitaxial feature, the second S / D epitaxial feature, the one or more channel structures, and the gate structure are located on a front side of the semiconductor structure; a metal wiring layer located on a back side of the semiconductor structure; and a conductive feature connecting the metal wiring layer and the first S / D epitaxial feature, wherein the conductive feature extends to a position directly below the one or more channel structures.

[0076] Example 18 is the semiconductor structure described in Example 17, wherein a bottom surface portion of the first S / D epitaxial feature is in partial contact with the conductive feature.

[0077] Example 19 is the semiconductor structure described in Example 17, wherein a portion of the first S / D epitaxial feature is embedded in the conductive feature.

[0078] Example 20 is the semiconductor structure described in Example 17, wherein the conductive feature is a first conductive feature, further comprising: a second conductive feature located on a front side of the semiconductor structure, wherein the second conductive feature is in physical contact with the second S / D epitaxial feature.

Claims

1. A method of forming a semiconductor structure, comprising: forming a sacrificial feature in a top portion of a substrate; forming a fin over the sacrificial feature; recessing the fin in a source / drain (S / D) region to form an S / D trench exposing the sacrificial feature; forming an S / D epitaxial feature in the S / D trench; removing a bottom portion of the substrate to expose the sacrificial feature from a back side of the substrate; and replacing the sacrificial feature with a conductive feature.

2. The method according to claim 1, wherein Replacing the sacrificial feature with the conductive feature comprises: removing the sacrificial feature in a selective etching process to form a trench exposing the S / D epitaxial feature, and depositing the conductive feature in the trench.

3. The method according to claim 2, wherein The trench also exposes a top portion of the substrate, and wherein replacing the sacrificial feature with the conductive feature further comprises: removing the top portion of the substrate from the trench before removing the sacrificial feature, and depositing a dielectric layer adjacent to the sacrificial feature.

4. The method according to claim 1, wherein The conductive feature is in physical contact with the S / D epitaxial feature.

5. The method according to claim 1, wherein The substrate includes a buried insulating layer, and wherein forming the sacrificial feature comprises: patterning a top portion of the substrate to form an opening exposing the buried insulating layer, and depositing the sacrificial feature in the opening to cover the buried insulating layer.

6. The method according to claim 5, wherein Removing the bottom portion of the substrate includes removing the buried insulating layer.

7. The method according to claim 1, wherein The top portion of the substrate includes an overlying semiconductor layer, and wherein the fin has a first sidewall directly above the overlying semiconductor layer and a second sidewall directly above the sacrificial feature.

8. The method according to claim 1, wherein, The fin has a first sidewall and a second sidewall, both of which are directly above the sacrificial feature.

9. The method according to claim 1, further comprising: removing a bottom portion of the fin; and forming an etch stop layer stacked between the fin and the sacrificial feature, wherein the conductive feature is in physical contact with the etch stop layer.

10. A method of forming a semiconductor structure, comprising: providing a structure having a front side and a back side, the structure including a substrate on the back side of the structure and a fin on the front side of the structure, wherein the substrate includes a sacrificial feature under the fin, and wherein the fin includes a plurality of sacrificial layers and a plurality of channel layers arranged alternately; recessing the fin from the front side of the structure to expose the sacrificial feature in a source / drain (S / D) region; forming an S / D epitaxial feature over the sacrificial feature; thinning the structure from the back side of the structure until the sacrificial feature is exposed; etching the sacrificial feature from the back side of the structure to form a trench exposing the S / D epitaxial feature; depositing a conductive feature in the trench; and forming a metal wiring layer on the back side of the structure, wherein the metal wiring layer is electrically coupled to the S / D epitaxial feature through the conductive feature.

11. The method according to claim 10, wherein, The substrate includes a semiconductor layer surrounding the sacrificial feature, and wherein thinning the structure also exposes the semiconductor layer.

12. The method according to claim 10, further comprising: Deposit isolation features on the front side of the structure, the isolation features covering the sacrificial features and the bottom portions of the sidewalls of the fins. Wherein, the trench also exposes the isolation features.

13. The method according to claim 12, wherein, The top surface of the isolation features is higher than the top surface of the bottommost sacrificial layer.

14. The method according to claim 10, further comprising: Removing the bottommost sacrificial layer from the fins, thereby forming an opening between the fins and the sacrificial features; And Depositing a dielectric layer in the opening.

15. The method according to claim 14, wherein, The trench also exposes the dielectric layer.

16. The method according to claim 14, further comprising: Recessing the dielectric layer from the back side of the structure such that a portion of the S / D epitaxial features protrudes from the recessed dielectric layer.

17. A semiconductor structure, comprising: A first source / drain (S / D) epitaxial feature and a second S / D epitaxial feature; One or more channel structures connecting the first S / D epitaxial feature and the second S / D epitaxial feature; A gate structure engaging the one or more channel structures, wherein the first S / D epitaxial feature, the second S / D epitaxial feature, the one or more channel structures, and the gate structure are located on the front side of the semiconductor structure; A metal wiring layer located on the back side of the semiconductor structure; and A conductive feature connecting the metal wiring layer and the first S / D epitaxial feature, wherein the conductive feature extends to a position directly below the one or more channel structures; and A self-aligned contact (SAC) layer located below the one or more channel structures, the SAC layer being configured to be recessed during an etching process to cause the first S / D epitaxial feature and the second S / D epitaxial feature to protrude from the SAC layer.

18. The semiconductor structure according to claim 17, wherein, The bottom surface portion of the first S / D epitaxial feature partially contacts the conductive feature.

19. The semiconductor structure according to claim 17, wherein, A portion of the first S / D epitaxial feature is embedded in the conductive feature.

20. The semiconductor structure according to claim 17, wherein, The conductive feature is a first conductive feature, further comprising: A second conductive feature located on the front side of the semiconductor structure, wherein the second conductive feature is in physical contact with the second S / D epitaxial feature.

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