A semiconductor device and a control method thereof

Abstract

The present invention relates to the technical field of electronic circuits, and specifically discloses a semiconductor device and a control method therefor. The semiconductor device includes an HIVC drive logic circuit, an upper bridge arm drive signal output circuit, and a lower bridge arm drive signal output circuit. Both the upper bridge arm drive signal output circuit and the lower bridge arm drive signal output circuit are electrically connected to the HIVC drive logic circuit. The HIVC drive logic circuit includes a PWM signal buffer circuit, an upper bridge arm drive circuit, a lower bridge arm drive circuit, and a fault logic control circuit. The PWM signal buffer circuit, the lower bridge arm drive circuit, and the fault logic control circuit are all electrically connected to the upper bridge arm drive circuit. The present invention adopts a double-pulse trigger circuit to solve the problem that the RS flip-flop cannot record the signal sent by the single pulse GEN due to the long time for VS to recover from the negative, resulting in unstable operation of the HVIC, and effectively improves the usage efficiency and stability of the HVIC.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a semiconductor device and a control method thereof. Background Art

[0002] An Intelligent Power Module (IPM) is a power drive type semiconductor product that combines power electronics and integrated circuit HVIC technologies. Inside, power switch devices and high-voltage drive device circuits are integrated together, and fault detection circuits such as overvoltage, overcurrent, and overheating are built in. It is widely used in systems such as frequency converters, welding machines, and servo drives. It is internally divided into an upper bridge arm, a lower bridge arm, a logic circuit, a protection circuit, etc., and drive control and protection feedback are realized through the logic chip of the integrated circuit. When the intelligent power module is working, on the one hand, it receives the control signal of the MCU to drive the subsequent circuit to work, and on the other hand, it sends the state detection signal of the system back to the MCU for processing to detect the working dynamics of the IPM in real time, such as sudden overcurrent, overvoltage, and overheating, and can make protection actions in time.

[0003] HVIC, that is, a high-voltage integrated drive IC, is a high-voltage-resistant IC that directly drives the gates of power MOSFETs and IGBTs using the input signal of a single-chip microcomputer and can replace common pulse transformers and optocouplers. In the HIVC integrated circuit control system, for the upper bridge to instantaneously turn on and off the high-voltage DMOS, generally, the rising edge and falling edge of the upper bridge HIN signal are respectively used to generate pulses to control its turn-on and turn-off, and an RS signal flip-flop is used to record this instantaneous control signal to make the control signal HO of the upper bridge synchronized with HIN. VB is a voltage formed by a voltage pump and has limited energy. Generally, it does not have the ability to continuously pass current to the ground through the conducting DMOS. The reason why the continuous high and low signals of HIN cannot be used to control the conduction of DMOS is that when VS is 600V - 650V, the level of VB is 615V - 675V. If a continuous current loop is generated between VB and the ground, VB will rapidly decrease and enter the low-voltage protection area, making the HVIC unable to work properly. The introduction of the PLUSE GEN (pulse generator) circuit is very necessary. In HVIC, the more commonly used PLUSE GEN (pulse generator) is a single-pulse NESHOT circuit (generating one pulse). For the case where VS will be pulled to a lower level, the time for VS to recover from the negative is relatively long. If there is only one pluse signal, the pulse width is generally in the order of hundreds of nanoseconds, and the signal may be submerged, resulting in the RS flip-flop being unable to detect the signal and the HIVC being unable to work. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a semiconductor device and its control method in view of the above-mentioned defects of the prior art. By adopting a dual-pulse trigger circuit, it solves the problem that the RS flip-flop cannot record the signal sent by the single pulse GEN due to the long time for VS to recover from the negative, and the problem of unstable operation of the HVIC, effectively improving the usage efficiency and stability of the HVIC.

[0005] To solve the above technical problem, the technical solution of the present invention is as follows:

[0006] A semiconductor device includes an HIVC drive logic circuit, an upper-bridge-arm drive signal output circuit, and a lower-bridge-arm drive signal output circuit. Both the upper-bridge-arm drive signal output circuit and the lower-bridge-arm drive signal output circuit are electrically connected to the HIVC drive logic circuit. The HIVC drive logic circuit includes a PWM signal buffer circuit, an upper-bridge-arm drive circuit, a lower-bridge-arm drive circuit, and a fault logic control circuit. The PWM signal buffer circuit, the lower-bridge-arm drive circuit, and the fault logic control circuit are all electrically connected to the upper-bridge-arm drive circuit.

[0007] Preferably, the PWM signal buffer circuit includes a plurality of Schmidt triggers, a plurality of filter circuits, and a plurality of potential displacement circuits. The filter circuits are electrically connected to the Schmidt triggers and the potential displacement circuits respectively.

[0008] Preferably, the upper-bridge-arm drive circuit includes a plurality of dead-time interlock circuits, a delay circuit, a pulse generation circuit, a drive conduction circuit, a filter rectification circuit, and a latch circuit. The dead-time interlock circuits are electrically connected to the delay circuit and the pulse generation circuit respectively. The drive conduction circuit is electrically connected to the pulse generation circuit and the filter rectification circuit respectively. The latch circuit is electrically connected to the filter rectification circuit.

[0009] Preferably, the lower-bridge-arm drive circuit includes a comparator, MOSFET MOS5, and MOSFET MOS6. The comparator is electrically connected to the delay circuit, the pulse generation circuit, MOSFET MOS5, and MOSFET MOS6 respectively.

[0010] Preferably, the semiconductor device further includes an enable drive circuit, a power supply undervoltage protection circuit, and a fault output circuit. The enable drive circuit and the power supply undervoltage protection circuit are both electrically connected to the filter circuit and the fault logic control circuit respectively. The fault output circuit is electrically connected to the Schmidt trigger and the filter circuit respectively.

[0011] Preferably, the drive conduction circuit includes MOSFET MOS1 and MOSFET MOS2. The filter rectification circuit includes a DV / DT filter and a UV filter. The latch circuit includes a latch, a NOR logic gate, MOSFET MOS3, and MOSFET MOS4. Both MOSFET MOS1 and MOSFET MOS2 are electrically connected to the pulse generation circuit, the DV / DT filter, and the UV filter respectively. The latch is electrically connected to the DV / DT filter, the UV filter, and the NOR logic gate respectively. Both MOSFET MOS3 and MOSFET MOS4 are electrically connected to the NOR logic gate.

[0012] Preferably, the pulse generation circuit includes a first pulse generation circuit and a second pulse generation circuit. The first pulse generation circuit receives the HIN input signal. The delay circuit is electrically connected to the first pulse generation circuit and the second pulse generation circuit respectively. The second pulse generation circuit is electrically connected to the drive conduction circuit.

[0013] To solve the above technical problems, the present invention also provides a semiconductor device control method. A drive high-level signal is input at the HIN signal input terminal, filtered by a Schmitt circuit, and then the level conversion circuit outputs a HIN pulse signal. The rising edge and falling edge of the HIN pulse signal are respectively used to drive MOSFET MOS1 and MOSFET MOS2 through signal processing. The voltage rise and fall formed by the voltage pump are used to achieve high and low voltage separation. The conduction signals and turn-off signals of MOSFET MOS1 and MOSFET MOS2 are directly sent to the RS flip-flop for temporary storage and the pulse signals are respectively output to MOSFET MOS3 and MOSFET MOS4, thereby realizing the synchronization of the HO drive signal and the HIN drive signal.

[0014] Preferably, when the HIN pulse signal input is at a high level, the rising edge signal of HIN is detected by the double-pulse generation circuit. A pulse signal will be output at the HINA terminal of the double-pulse generation circuit, and MOSFET MOS1 is turned on once. After a preset delay time, a second pulse signal is output. At this time, the S terminal of the RS flip-flop is low-level effective, and the Q terminal of the RS flip-flop outputs a high level. At this time, the HINB terminal of the pulse generation circuit is at a low level, and MOSFET MOS2 is in the cut-off state. When the double-pulse generation circuit detects that the HIN pulse signal is a falling edge signal, a pulse signal will be output at the HINB terminal, and MOSFET MOS2 is turned on. The R terminal of the flip-flop is at a low level, and the Q terminal of the flip-flop is at a high level. At this time, the HINA terminal is at a low level, and MOSFET MOS1 is in the cut-off state.

[0015] With the above technical solution, a semiconductor device provided by the present invention has the following beneficial effects: A dual-pulse trigger circuit is adopted, that is, by setting that both the upper-bridge-arm drive signal output circuit and the lower-bridge-arm drive signal output circuit are electrically connected to the HIVC drive logic circuit. The HIVC drive logic circuit includes a PWM signal buffer circuit, an upper-bridge-arm drive circuit, a lower-bridge-arm drive circuit, and a fault logic control circuit. The PWM signal buffer circuit, the lower-bridge-arm drive circuit, and the fault logic control circuit are all electrically connected to the upper-bridge-arm drive circuit, which solves the problem that the RS flip-flop cannot record the signal sent by the single pulse GEN due to the long time for VS to recover from the negative, resulting in unstable operation of the HVIC. A drive high-level signal is input at the HIN signal input terminal, filtered by a Schmitt circuit, and then the level conversion circuit outputs a HIN pulse signal. The HIN pulse signal is processed to output rising and falling edges to drive MOSFET MOS1 and MOSFET MOS2 respectively. The voltage rise and fall formed by the voltage pump realize high-voltage and low-voltage separation. The conduction signals and turn-off signals of MOSFET MOS1 and MOSFET MOS2 are directly sent to the RS flip-flop for temporary storage and output pulse signals to MOSFET MOS3 and MOSFET MOS4 respectively, thereby realizing the synchronization of the HO drive signal and the HIN drive signal, effectively improving the usage efficiency and stability of the HVIC. Description of the Drawings

[0016] Figure 1 It is the internal structure topology diagram of the semiconductor device in the present invention;

[0017] Figure 2 It is the internal structure topology diagram of the HIVC drive logic circuit in the present invention;

[0018] Figure 3 It is the internal structure topology diagram of the high-voltage side circuit in the present invention;

[0019] Figure 4 It is the circuit structure diagram of Embodiment 1 of the present invention;

[0020] Figure 5 It is the pulse signal control timing diagram of Embodiment 1 of the present invention. Detailed Embodiments

[0021] The following further describes the detailed embodiments of the present invention with reference to the drawings. It should be noted here that the description of these embodiments is for helping to understand the present invention, but does not constitute a limitation to the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0022] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present invention.

[0023] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0024] As Figures 1-4 shown, the semiconductor device includes an HIVC drive logic circuit 10, an upper bridge arm drive signal output circuit, and a lower bridge arm drive signal output circuit. Both the upper bridge arm drive signal output circuit and the lower bridge arm drive signal output circuit are electrically connected to the HIVC drive logic circuit 10. The HIVC drive logic circuit 10 includes a PWM signal buffer circuit 11, an upper bridge arm drive circuit 12, a lower bridge arm drive circuit 13, and a fault logic control circuit. The PWM signal buffer circuit 11, the lower bridge arm drive circuit 13, and the fault logic control circuit are all electrically connected to the upper bridge arm drive circuit 12. They achieve protection functions such as driving and under-voltage through logical relationships among them. The HIVC drive logic circuit 10 is used to receive and feedback the PWM input control signal of the peripheral main control board MCU, drive the upper bridge arm drive circuit 12 and the lower bridge arm drive circuit 13, so that components such as the switching transistors Q1, Q2, Q3, Q4, Q5, and Q6 in the drive signal output circuit 56 work to achieve the purpose of motor drive. At the same time, a control voltage under-voltage protection circuit (UV), an over-temperature protection circuit (OT), an over-current protection circuit (OC), and a short-circuit protection circuit (SC) are provided inside the HIVC drive logic circuit 10. When a fault occurs during the operation of the module, it can achieve upper and lower bridge interlocking and cut off the power signal to avoid burning out the product and ensure the stability and reliability of the product.

[0025] It can be understood that the PWM signal buffer circuit 11 is a buffer circuit for the PWM signals of the upper and lower bridge arms. After receiving the MCU signal from the peripheral circuit, it is processed by filtering and amplification and then output to the corresponding switch tube drive circuit. The upper bridge arm drive circuit 12 includes a bootstrap circuit, an undervoltage protection circuit, a UPU drive circuit, a UPV drive circuit, and a UPW drive circuit. Different from the existing solutions, it integrates the bootstrap circuit into the HVIC. Compared with the external bootstrap circuit solution, it can be more reliable and is convenient for high-integration design of the module. After receiving the signal from the circuit 11, the lower bridge arm drive circuit 13 directly drives the switch tubes Q4, Q5, and Q6 after the signal is processed by filtering and amplification. The protection circuit 14 is a working protection circuit for the upper and lower bridge arms, responsible for monitoring the working states of the switch tubes Q1, Q2, Q3, Q4, Q5, and Q6. When a fault occurs and the ITRIP terminal detects an abnormal signal, the signal is fed back to the MCU, and an action is immediately taken to cut off the signal, and the signal at the FAULT terminal changes from a high level to a low level state to achieve the function of protecting the module. The drive enable circuit 15 is active high and is responsible for enabling and disabling the module execution function. When it monitors that the working states of the switch tubes Q1, Q2, Q3, Q4, Q5, and Q6 are in a fault state, it will remain in a low level state and cut off the power supply to protect the entire module circuit. When the fault disappears and the RCIN recovery time inside it reaches the designed value, it then returns to a high level state, the module is powered on, and enters the working preparation state. The fault logic output circuit 16 is an intelligent power module fault detection and output circuit. When the system detects abnormal signals such as undervoltage protection (UV), overtemperature protection (OT), overcurrent protection (OC), and short-circuit protection (SC), the FAULT signal changes from a high level to a low level state, the signal is fed back to the MCU, and an action is immediately taken to cut off the signal, and the module stops working. The drive signal output circuit 56 includes the switch tubes Q1, Q2, and Q3 of the upper bridge arm and the switch tubes Q4, Q5, and Q6 of the lower bridge arm. When receiving the drive signal, it drives the external variable-frequency motor.

[0026] Specifically, the PWM signal buffer circuit includes several Schmidt triggers, several filter circuits, and several potential displacement circuits. The filter circuits are electrically connected to the Schmidt triggers and the potential displacement circuits respectively. The upper bridge arm drive circuit includes several dead-time interlock circuits, a delay circuit, a pulse generation circuit, a drive conduction circuit, a filter rectification circuit, and a latch circuit. The dead-time interlock circuit is electrically connected to the delay circuit and the pulse generation circuit respectively. The drive conduction circuit is electrically connected to the pulse generation circuit and the filter rectification circuit respectively. The latch circuit is electrically connected to the filter rectification circuit. The lower bridge arm drive circuit includes a comparator, MOSFET MOS5, and MOSFET MOS6. The comparator is electrically connected to the delay circuit, the pulse generation circuit, MOSFET MOS5, and MOSFET MOS6 respectively. The semiconductor device further includes an enable drive circuit, a power supply undervoltage protection circuit, and a fault output circuit. The enable drive circuit and the power supply undervoltage protection circuit are both electrically connected to the filter circuit and the fault logic control circuit respectively. The fault output circuit is electrically connected to the Schmidt trigger and the filter circuit respectively. The drive conduction circuit includes MOSFET MOS1 and MOSFET MOS2. The filter rectification circuit includes a DV / DT filter and a UV filter. The latch circuit includes a latch, a NOR logic gate, MOSFET MOS3, and MOSFET MOS4. MOSFET MOS1 and MOSFET MOS2 are both electrically connected to the pulse generation circuit, the DV / DT filter, and the UV filter respectively. The latch is electrically connected to the DV / DT filter, the UV filter, and the NOR logic gate respectively. MOSFET MOS3 and MOSFET MOS4 are both connected to the NOR logic gate. The pulse generation circuit includes a first pulse generation circuit and a second pulse generation circuit. The first pulse generation circuit receives the HIN input signal. The delay circuit is electrically connected to the first pulse generation circuit and the second pulse generation circuit respectively. The second pulse generation circuit is electrically connected to the drive conduction circuit.

[0027] It can be understood that the HIVC drive logic circuit is further divided into a high-side drive circuit and a low-side drive circuit; the high-side drive circuit 326 includes a first Schmitt trigger 300, a first filter circuit 301, a potential displacement circuit 302, a NAND logic gate 303, a pulse generation circuit 304, a dv / dt filter 305, a latch 306, a NOR logic gate 307, a NAND logic gate 308, a NAND logic gate 309, a UV filter circuit 311, as well as MOSFET transistors MOS1, MOSFET transistor MOS2, MOSFET transistor MOS3, MOSFET transistor MOS4, current-limiting resistors RS1, and current-limiting resistor RS2. The current-limiting resistors RS1 and RS2 form a bootstrap circuit; the input terminal of the Schmitt trigger 300 is the input terminal of the high-side drive circuit 326, and the output terminal of the first Schmitt trigger 300 is interconnected with the input terminal of the first filter circuit 301; the output terminal of the first filter circuit 301 is interconnected with the input terminal of the potential displacement circuit 302; the output terminal of the potential displacement circuit 302 is interconnected with the first input terminal of the dead-time interlock circuit 303 and the first input terminal of the dead-time interlock circuit 308; the output terminal of the dead-time interlock circuit 308 is interconnected with the input terminal of the dead-time interlock circuit 303; the output terminal of the dead-time interlock circuit 303 is interconnected with the input terminal of the pulse generation circuit 304; the output terminal of the pulse generation circuit 304 is interconnected with the gates of the MOSFET transistors MOS1 and MOS2, the drain terminal of MOS1 is interconnected with the input terminal of the dv / dt filter 305; the drain terminal of MOS2 is interconnected with the UV filter 311, the output terminal of the dv / dt filter 305 is interconnected with the input terminal S of the latch 306; the output terminal of the UV filter 311 is interconnected with the input terminal R of the latch 306; the output terminal Q of the latch 306 is interconnected with the input terminal of the NOR logic gate 307; the output terminal of the NOR logic gate 307 is interconnected with the gates of MOS3 and MOS4.It can be understood that in the signal transmission control process, the Schmitt trigger 300 is used to filter the PWM control signal output by the peripheral main control board MCU and then stably output it to the subsequent first filter circuit 302. The first filter circuit is used to perform high-frequency and narrow-band filtering on the received control signal, invert the control signal, and output it to the potential displacement circuit 302. The potential displacement circuit is used to compensate the coupled signal and add a DC level adjustment function when the amplitude of the coupled signal is large, so as to realize the stable output of the signal to the dead zone generation interlock circuits 303 and 308; the pulse generation circuit 304 is used to output to the gates of the MOSFET tubes MOS1 and MOS2 for driving conduction after receiving the high-level signal output by the dead zone generation interlock circuit 303. The gates and sources of the MOSFET tubes MOS1 and MOS2 are short-circuited to achieve unidirectional conduction, and the voltage is output to VB through the current-limiting resistors RS1 and RS2; the DV / DT filter 305 is used to receive the drain voltages of the MOSFET tubes MOS1 and MOS2 for filtering and rectifying to stabilize the voltage; the UV filter 311 receives the point level signal after the bootstrap resistor voltage division for filtering and rectifying; the latch 306 is used to temporarily store the signals of the DV / DT filter 305 and the UV filter 311, and finally make the output of the level signal synchronous; the NOR logic gate 307 is used to receive the signal of the latch 306 and control the driving and turning-on conditions of the MOSFET tubes MOS3 and MOS4 by comparing the input high and low levels of heat generation.

[0028] It can be understood that the low-voltage side drive circuit includes a Schmitt trigger 312, a second filter circuit 313, a potential displacement circuit 314, a dead zone interlock circuit 309, a delay circuit 310, a comparator 315, an MOSFET tube MOS5, and an MOSFET tube MOS6. The input end of the first Schmitt trigger 312 is the signal LIN input end, and the output end of the Schmitt trigger 321 is interconnected with the input end of the second filter circuit 313; the output end of the second filter circuit 313 is interconnected with the input end of the potential displacement circuit 314, and the output end of the potential displacement circuit 314 is interconnected with the input end of the dead zone generation interlock circuit 309; the output end of the dead zone generation interlock circuit 309 is interconnected with the delay circuit 310; the output end of the delay circuit 310 is interconnected with the input end of the comparator 315; the output end of the comparator 315 is interconnected with the gates of the MOSFET tube MOS5 and the MOSFET tube MOS6. The signal transmission control process: The Schmitt trigger 300 is used to filter the PWM control signal output by the peripheral main control board MCU and stably output it to the subsequent second filter circuit 313. The second filter circuit 313 is used to perform high-frequency and narrow-wave filtering on the received control signal, invert the control signal, and output it to the potential displacement circuit 314, and then output it to the dead zone interlock circuit 308 and the dead zone interlock circuit 309. The delay circuit 310 is used to delay the output of the control signal output by the dead zone interlock circuit 309 to avoid a short-circuit fault of the power inverter bridge circuits MOS5 and MOS6 caused by the simultaneous conduction of the lower-arm power tube and the upper-arm power tube of the high-voltage side drive circuit.

[0029] It can be understood that, as Figure 2 shown, the low-voltage signal EN enable terminal includes a Schmitt trigger 316, a third filter circuit 317, and an enable drive circuit 318; it is active high. When a fault occurs in the control system, the high level is converted to a low level for output. The low-voltage signal ITRIP terminal includes a Schmitt trigger 319, a fourth filter circuit 320, and a potential displacement circuit 321; it is active low. When a fault occurs in the control system, the low level is converted to a high level for output. The low-voltage signal PFCTRIP terminal includes a Schmitt trigger 322, a fourth filter circuit 323, and a potential displacement circuit 324; it is active low. When a fault occurs in the control system, the low level is converted to a high level for output. The low-voltage signal VCC terminal includes a Schmitt trigger 325, a fifth filter circuit 325, and a power supply undervoltage protection circuit. In a conventional drive control system, when the power supply voltage is lower than 12.5V (typical value), the module exhibits undervoltage protection, triggers the Fault terminal through the fault control system, outputs a low level, and the module stops working. The low-voltage signal FAULT terminal includes a Schmitt trigger 328, a fault output circuit 329, and a sixth filter circuit 330; it is active high. When a fault occurs in the control system, the high level is converted to a low level for output.

[0030] Figure 3 This is the internal structure topology diagram of the high-voltage side circuit in the present invention. The high-voltage side circuit includes a HIN signal input circuit 400, a Schmitt circuit 401, a level conversion logic circuit 402, a pulse generation circuit 403, high-voltage DMOS transistors 404, 405, a signal flip-flop circuit 406, high-voltage DMOS transistors 407, 408, and a VB / VS / HO signal output circuit 409. The HIN input drives a high-level signal, which is filtered by the Schmitt circuit 401, and then the level conversion circuit 402 outputs a HIN pulse signal. The pulse signal of the pulse generation circuit 403 is processed and outputs rising and falling edges respectively to drive the high-voltage DMOS transistors 404 and 405. The voltage rise and fall formed by the voltage pump realize the separation of high and low voltages. The on and off signals of the high-voltage DMOS transistors 404 and 405 are directly sent to the RS flip-flop 406 for temporary storage and output of the pulse signal, which are respectively given to the high-voltage DMOS transistors 407 and 408 to achieve synchronization of the HO and HIN drive signals.

[0031] Figure 4 This is the circuit structure diagram of the first embodiment of the present invention, including a HIN signal input circuit, a pulse generation circuit, high-voltage DMOS transistors DMOS1, DMOS2, pull-up resistors R1, R2, a signal flip-flop, high-voltage DMOS transistors DMOS3, DMOS4, and a VB / VS / HO signal output circuit. The pulse generation circuit 500 includes a pulse generation circuit 1, a delay circuit, and a pulse generation circuit 2. As Figure 5 shown, the control logic method is as follows: When the HIN input is at a high level and the pulse generation circuit detects the rising edge signal of HIN, the pulse generation circuit at the HINA terminal will output a pulse signal, and the high-voltage DMOS transistor DMOS1 will be turned on once. After a preset delay time, a second pulse signal will be output. At this time, the S of the flip-flop is low-level effective, and the Q output of the flip-flop is high level. At this time, HINB is at a low level, and the high-voltage DMOS transistor DMOS2 is in a cut-off state; when the double-pulse generation circuit detects the falling edge signal of HIN, the pulse generation circuit at the HINB terminal will output a pulse signal, and the high-voltage DMOS transistor DMOS2 will be turned on. The R of the flip-flop is low-level effective, and the Q of the flip-flop is high level. At this time, HINA is at a low level, and the high-voltage DMOS transistor DMOS1 is in a cut-off state. That is, the pulse width of the HIN input signal is consistent with the distance between the pulses output by HINA and HINB.

[0032] It can be understood that the design of the present invention is reasonable and the structure is unique. By adopting a double-pulse drive circuit inside the HIVC drive logic circuit, the problem that the RS flip-flop cannot record the signal sent by the single pulse GEN due to the long time for VS to recover from negative, and the problem of unstable operation of the HVIC is solved, effectively improving the use efficiency and stability of the HVIC.

[0033] The above embodiments of the present invention have been described in detail in conjunction with the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, without departing from the principle and spirit of the present invention, various changes, modifications, substitutions and variations made to these embodiments still fall within the protection scope of the present invention.

Claims

1. A semiconductor device includes an HIVC drive logic circuit, an upper bridge arm drive signal output circuit, and a lower bridge arm drive signal output circuit. The upper bridge arm drive signal output circuit and the lower bridge arm drive signal output circuit are both electrically connected to the HIVC drive logic circuit. Characterized in that: The HIVC drive logic circuit includes a PWM signal buffer circuit, an upper bridge arm drive circuit, a lower bridge arm drive circuit, and a fault logic control circuit. The PWM signal buffer circuit, the lower bridge arm drive circuit, and the fault logic control circuit are all electrically connected to the upper bridge arm drive circuit. The upper bridge arm drive circuit includes a plurality of dead zone interlock circuits, delay circuits, pulse generation circuits, drive conduction circuits, filter rectifier circuits, and latch circuits. The dead zone interlock circuits are electrically connected to the delay circuits and the pulse generation circuits respectively. The drive conduction circuits are electrically connected to the pulse generation circuits and the filter rectifier circuits respectively. The latch circuit is electrically connected to the filter rectifier circuit. The drive conduction circuit includes MOSFET MOS1 and MOSFET MOS2. The filter rectifier circuit includes a DV / DT filter and a UV filter. The latch circuit includes a latch, a NOR logic gate, MOSFET MOS3, and MOSFET MOS4. MOSFET MOS1 and MOSFET MOS2 are both electrically connected to the pulse generation circuit, the DV / DT filter, and the UV filter respectively. The latch is electrically connected to the DV / DT filter, the UV filter, and the NOR logic gate respectively. MOSFET MOS3 and MOSFET MOS4 are both electrically connected to the NOR logic gate. The HIN signal input terminal inputs a drive high-level signal, which is filtered by a Schmitt circuit and then the level conversion circuit outputs a HIN pulse signal. The HIN pulse signal is processed by a signal processor to drive MOSFET MOS1 and MOSFET MOS2 respectively at the rising edge and the falling edge. The voltage rise and fall formed by a voltage pump realizes the separation of high and low voltages. The on-signals and off-signals of MOSFET MOS1 and MOSFET MOS2 are directly sent to an RS flip-flop for temporary storage and the output pulse signals are given to MOSFET MOS3 and MOSFET MOS4 respectively, so as to realize the synchronization of the HO drive signal and the HIN drive signal.

2. The semiconductor device according to claim 1, Characterized in that: The PWM signal buffer circuit includes a plurality of Schmitt triggers, a plurality of filter circuits, and a plurality of potential displacement circuits. The filter circuits are electrically connected to the Schmitt triggers and the potential displacement circuits respectively.

3. The semiconductor device according to claim 1, Characterized in that: The lower bridge arm drive circuit includes a comparator, MOSFET MOS5, and MOSFET MOS6. The comparator is electrically connected to the delay circuit, the pulse generation circuit, MOSFET MOS5, and MOSFET MOS6 respectively.

4. The semiconductor device according to claim 2, It is characterized in that: It further includes an enable drive circuit, a power supply undervoltage protection circuit and a fault output circuit. The enable drive circuit and the power supply undervoltage protection circuit are respectively electrically connected to the filter circuit and the fault logic control circuit, and the fault output circuit is respectively electrically connected to the Schmitt trigger and the filter circuit.

5. The semiconductor device according to claim 1, It is characterized in that: The pulse generation circuit includes a first pulse generation circuit and a second pulse generation circuit. The first pulse generation circuit receives the HIN input signal. The delay circuit is respectively electrically connected to the first pulse generation circuit and the second pulse generation circuit, and the second pulse generation circuit is electrically connected to the drive conduction circuit.

6. The semiconductor device according to claim 1, It is characterized in that: When the input of the HIN pulse signal is at a high level, the rising edge signal of HIN is detected by the double pulse generation circuit. A pulse signal will be output at the HINA terminal of the double pulse generation circuit, and the MOSFET tube MOS1 will be turned on once. After a preset delay time, a second pulse signal will be output. At this time, the S terminal of the RS flip-flop is valid at a low level, and the Q terminal of the RS flip-flop outputs a high level. At this time, the HINB terminal of the pulse generation circuit is at a low level, and the MOSFET tube MOS2 is in the cut-off state; when the double pulse generation circuit detects that the HIN pulse signal is a falling edge signal, a pulse signal will be output at the HINB terminal, the MOSFET tube MOS2 will be turned on, the R terminal of the flip-flop is at a low level, and the Q terminal of the flip-flop is at a high level. At this time, the HINA terminal is at a low level, and the MOSFET tube MOS1 is in the cut-off state.

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