A voltage-resistant I2C interface system

Abstract

The present invention discloses a voltage-resistant I2C interface system, comprising: a power supply circuit in an electronic device, a microelectronic device, a voltage-resistant processing circuit, an I2C interface circuit and a peripheral application circuit; the peripheral application circuit is electrically connected to the power supply circuit and the microelectronic device arranged in the device through the I2C interface circuit; the I2C interface circuit, the microelectronic device, and the voltage-resistant processing circuit are respectively connected to the power supply circuit, and the voltage-resistant processing circuit is also electrically connected to the microelectronic device, so as to limit the voltage transmitted from the peripheral application circuit to the microelectronic device within its working voltage to improve the voltage-resistant performance. In the implementation of the present invention, the low-level voltage signal is shielded by the high-level selection module, and the high-level voltage signal is output, so that the voltage difference between any two ends of all field effect tubes in the system is within 1.8V, which effectively avoids the risk problem of voltage resistance, and the waveform signal input to the chip is shaped and filtered, thereby improving the stability of the input voltage.

Description

Technical Field

[0001] The invention relates to the technical field of I2C interface circuits in microelectronics technology, and in particular to a voltage-resistant I2C interface system. Background Art

[0002] Many electronic devices use the I2C interface for communication. With the continuous advancement of integrated circuit technology and process level, the size of transistors and devices on the chip is getting smaller and smaller, and the operating voltage of the device is getting lower and lower. However, many peripheral applications have fixed voltage requirements. For example, 28nm process devices can only withstand 1.8V voltage, while many peripheral applications are still 5V, so some step-down devices must be used in the periphery to reduce the voltage to below 1.8V, which increases the complexity and cost of peripheral design. Therefore, it is very meaningful to design an I2C interface circuit with 5V high voltage resistance under advanced technology for the development of the entire microelectronics. Summary of the invention

[0003] The size of transistors and components of existing integrated circuits is developing towards miniaturization, and the operating voltage is also getting lower, but the operating voltage of some peripheral applications has not changed. This requires that when the peripheral applications are connected using the I2C interface, their voltage needs to be reduced to below the operating voltage of the miniaturized device through a step-down device, which increases the complexity and cost of the peripheral application circuit design.

[0004] In view of the above problems, a voltage-resistant I2C interface system is proposed. By applying the peripheral application circuit to the peripheral voltage divider of the microelectronic device, the high-level selection module shields the low-level voltage signal and outputs a high-level voltage signal. This makes the voltage difference between any two ends of all field-effect tubes in the system within 1.8V, effectively avoiding the risk of voltage resistance, and shaping and filtering the waveform signal input to the chip, thereby improving the stability of the input voltage.

[0005] A voltage-resistant I2C interface system, comprising:

[0006] Electronic devices

[0007] Power supply circuit,

[0008] Microelectronic devices,

[0009] Withstand voltage processing circuit,

[0010] I2C interface circuit; and

[0011] Peripheral application circuit;

[0012] The peripheral application circuit is electrically connected to the power supply circuit and the microelectronic device arranged in the device through the I2C interface circuit;

[0013] The I2C interface circuit, the microelectronic device, and the voltage resistance processing circuit are respectively connected to the power supply circuit, and:

[0014] The voltage-resistant processing circuit is also electrically connected to the microelectronic device to limit the voltage transmitted from the peripheral application circuit to the microelectronic device within the working voltage of the microelectronic device to improve the voltage-resistant performance.

[0015] In conjunction with the voltage-resistant I2C interface system of the present invention, in a first possible implementation manner, the voltage-resistant processing circuit includes:

[0016] Inverter module;

[0017] Voltage divider module;

[0018] High level selection module;

[0019] Input module;

[0020] The inverter module is electrically connected to the voltage divider module, the high level selection module and the input module respectively, and is used to achieve 180-degree inversion of the input level signal;

[0021] The voltage dividing module is electrically connected to the inverter module, the high level selection module and the input module respectively, and is used to divide the peripheral voltage applied to the microelectronic device by the peripheral application circuit;

[0022] The high-level selection module is electrically connected to the inverter module, the voltage divider module and the input module respectively, and is used to shield the low-level voltage signal and output the high-level voltage signal to maintain the voltage difference between the two ends of the device stable;

[0023] The input module is used to perform filtering and shaping processing on the level signal input by the processing circuit to the internal chip of the electronic device.

[0024] In combination with the first possible implementation manner of the present invention, in a second possible implementation manner, the inverter module includes a CMOS inverter circuit and a pull-down circuit, and the CMOS inverter circuit is electrically connected to the pull-down circuit via a resistor R1.

[0025] In combination with the second possible implementation manner of the present invention, in a third possible implementation manner, the CMOS inverter circuit includes:

[0026] A first field effect transistor M1 and a second field effect transistor M2;

[0027] The first field effect transistor M1 is a P-type field effect transistor, the second field effect transistor M2 is an N-type field effect transistor, the source of the first field effect transistor M1 is connected to the power supply circuit, the drain is connected to the drain of the second field effect transistor M2, the gate of the first field effect transistor M1 is connected to the gate of the second field effect transistor M2, and the source of the second field effect transistor M2 is grounded;

[0028] In combination with the third possible implementation manner of the present invention, in a fourth possible implementation manner, the pull-down circuit includes:

[0029] A third field effect transistor M3, a fourth field effect transistor M4 and a fifth field effect transistor M5;

[0030] The third field effect transistor M3, the fourth field effect transistor M4 and the fifth field effect transistor M5 are N-type field effect transistors and are connected in series in sequence: the drain of the third field effect transistor M3 is connected to the microelectronic device, the source is connected to the drain of the fourth field effect transistor M4, the source of the fourth field effect transistor M4 is connected to the drain of the fifth field effect transistor M5, the source of the fifth field effect transistor M5 is grounded, the gates of the third field effect transistor M3 and the fourth field effect transistor M4 are respectively connected to the high level selection module, and the gate of the fifth field effect transistor M5 is connected to the drain common contact of the CMOS inverter circuit through the resistor R1.

[0031] In combination with the fourth possible implementation manner of the present invention, in a fifth possible implementation manner, the voltage divider module is a field effect tube series circuit module, including:

[0032] a sixth field effect transistor M6, a seventh field effect transistor M7, and an eighth field effect transistor M8; and

[0033] A first voltage-dividing output circuit D1 and a second voltage-dividing output circuit D2;

[0034] The source of the sixth field effect transistor M6 is connected to the microelectronic device, and the gate and the drain are short-circuited and respectively connected to the source of the seventh field effect transistor M7 and the first voltage-dividing output line D1, the gate and the drain of the seventh field effect transistor M7 are short-circuited and respectively connected to the source of the eighth field effect transistor M8 and the second voltage-dividing output line D2, and the gate and the drain of the eighth field effect transistor M8 are short-circuited and grounded.

[0035] In combination with the fifth possible implementation manner of the present invention, in a sixth possible implementation manner, the high level selection module includes:

[0036] a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, and a twelfth field effect transistor M12; and

[0037] A first high level output circuit H1 and a second high level output circuit H2;

[0038] The source of the ninth field effect transistor M9 and the gate of the tenth field effect transistor M10 are connected together and connected to the first voltage-dividing output circuit D1, the drain of the ninth field effect transistor M9 and the source of the tenth field effect transistor M10 are connected together and connected to one end of the first high-level output circuit H1, and the gate of the ninth field effect transistor M9 and the drain of the tenth field effect transistor M10 are connected together and connected to one end of the second high-level output circuit H2;

[0039] The source of the eleventh field effect transistor M11 and the gate of the twelfth field effect transistor M12 are connected together and then connected to the second voltage-dividing output circuit D2, the drain of the eleventh field effect transistor M11 and the source of the twelfth field effect transistor M12 are connected together and then connected to one end of the second high-level output circuit H2, and the gate of the eleventh field effect transistor M11 and the drain of the tenth field effect transistor M10 are connected together and then connected to the power supply circuit;

[0040] The other end of the first high level output circuit H1 is connected to the gate of the third field effect transistor M3 , and the other end of the second high level output circuit H2 is connected to the gate of the fourth field effect transistor M4 .

[0041] In combination with the sixth possible implementation manner of the present invention, in a seventh possible implementation manner, the input module includes:

[0042] Voltage dividing resistors R2 and R3, filter capacitor C2 and Schmitt trigger;

[0043] One end of the voltage-dividing resistor R2 is connected to the microelectronic device, and the other end is connected to one end of the voltage-dividing resistor R3. The other end of the voltage-dividing resistor R3 is connected to the drain of the eighth field effect transistor M8, the source of the second field effect transistor M2, the source of the fifth field effect transistor M5, one end of the filter capacitor C2 and the first feedback end of the Schmitt trigger and then grounded;

[0044] The second feedback terminal of the Schmitt trigger and the other end of the filter capacitor C2 are connected together and then connected between the voltage-dividing resistor R2 and the voltage-dividing resistor R3.

[0045] In conjunction with the voltage-resistant I2C interface system of the present invention, in an eighth possible implementation manner, the system further includes:

[0046] Slope control module;

[0047] The slope control module is used to form a fixed slope through negative feedback to control the rising edge and falling edge of the microelectronic device, including:

[0048] Resistor R1 and capacitor C1;

[0049] One end of the resistor R1 is connected to the drains of the first field effect transistor M1 and the second field effect transistor M2, the other end of the resistor R1 is connected to one end of the capacitor C1 and the gate of the fifth field effect transistor M5, and the other end of the capacitor C1 is connected to the drain of the third field effect transistor M3 and the source of the sixth field effect transistor M6.

[0050] In conjunction with the voltage-resistant I2C interface system of the present invention, in a ninth possible implementation manner, the operating voltage of the microelectronic device is 1.8V, and the operating voltage of the peripheral application circuit is 5V.

[0051] The voltage-resistant I2C interface system described in the present invention is implemented by applying a peripheral application circuit to the peripheral voltage division of the microelectronic device, and the high-level selection module shields the low-level voltage signal and outputs a high-level voltage signal, so that the voltage difference between any two ends of all field effect tubes in the system is within 1.8V, effectively avoiding the risk of voltage resistance, and shaping and filtering the waveform signal input to the chip, thereby improving the stability of the input voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 This is a schematic diagram of the logic connection of the voltage-resistant I2C interface system module of the present invention;

[0054] Figure 2 It is a schematic diagram of the connection of electronic components of the voltage-resistant I2C interface system of the present invention;

[0055] The names of the parts indicated by the numbers in the accompanying drawings are: 100 - electronic equipment, 110 - microelectronic device, 120 - power supply circuit, 130 - voltage resistance processing circuit, 131 - inverter module, 132 - voltage divider module, 133 - high level selection module, 134 - slope control module, 135 - input module, 200 - I2C interface circuit, 300 - peripheral application circuit. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings in the invention to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0057] The size of transistors and components of existing integrated circuits is developing towards miniaturization, and the operating voltage is also getting lower, but the operating voltage of some peripheral applications has not changed. This requires that when the peripheral applications are connected using the I2C interface, their voltage needs to be reduced to below the operating voltage of the miniaturized device through a step-down device, which increases the complexity and cost of the design of the peripheral application circuit 300.

[0058] In view of the above problems, a voltage-resistant I2C interface system is proposed.

[0059] A voltage-tolerant I2C interface system, such as Figure 1 , Figure 1 The present invention is a schematic diagram of the logic connection of the voltage-resistant I2C interface system module, including: a power circuit 120, a microelectronic device 110, a voltage-resistant processing circuit 130 and an I2C interface circuit 200 in an electronic device 100, and a peripheral application circuit 300 connected to the electronic device 100 through the I2C interface circuit 200. The peripheral application circuit 300 is electrically connected to the power circuit 120 and the microelectronic device 110 provided in the device through the I2C interface circuit 200; the I2C interface circuit 200, the microelectronic device 110, and the voltage-resistant processing circuit 130 are respectively connected to the power circuit 120, and: the voltage-resistant processing circuit 130 is also electrically connected to the microelectronic device 110, so as to limit the voltage transmitted from the peripheral application circuit 300 to the microelectronic device 110 to within its working voltage, so as to improve the voltage-resistant performance.

[0060] As a specific implementation, the operating voltage of the microelectronic device 110 is 1.8V, and the operating voltage of the peripheral application circuit 300 is 5V.

[0061] The microelectronic device 110 in the electronic device 100, such as a 28nm process chip (pad), or some microelectronic devices 110, has an operating voltage of only 1.8V, but the voltage of the peripheral application circuit 300 connected through the I2C interface is 5V. It is necessary to set a complex step-down circuit on the peripheral application circuit 300 to avoid the risk of voltage resistance of the microelectronic device 110 caused by the peripheral voltage. In order to reduce the complexity of the peripheral application circuit 300, in this application, a voltage resistance processing circuit 130 is set in the electronic device 100 and connected to the I2C interface circuit 200, which not only meets the communication protocol, but also avoids the voltage resistance risk brought by the peripheral application circuit 300, and also reduces the complexity of the peripheral application circuit 300.

[0062] As a preferred embodiment, the voltage-resistant processing circuit 130 may include an inverter module 131, a voltage divider module 132, a high-level selection module 133 and an input module 135; the inverter module 131 is electrically connected to the voltage divider module 132, the high-level selection module 133 and the input module 135, respectively, for realizing a 180-degree reversal of the input level signal; the voltage divider module 132 is electrically connected to the inverter module 131, the high-level selection module 133 and the input module 135, respectively, for dividing the peripheral voltage applied to the microelectronic device 110 by the peripheral application circuit 300; the high-level selection module 133 is electrically connected to the inverter module 131, the voltage divider module 132 and the input module 135, respectively, for shielding low-level voltage signals and outputting high-level voltage signals to maintain a stable voltage difference across the device; the input module 135 is used to filter and shape the level signal input by the processing circuit to the internal chip of the electronic device.

[0063] The high-level signal comes from the microelectronic device 110PAD, passes through the Schmitt trigger output, and is input into the chip inside the electronic device.

[0064] By applying the peripheral application circuit 300 to the peripheral voltage divider of the microelectronic device 110, the high-level selection module 133 shields the low-level voltage signal and outputs a high-level voltage signal, so that the voltage difference between any two ends of all field effect tubes in the system is within 1.8V, effectively avoiding the risk of voltage resistance, and shaping and filtering the waveform signal input to the chip, thereby improving the stability of the input voltage.

[0065] As a preferred embodiment, Figure 2 , Figure 2 1 is a schematic diagram of connecting electronic components of a voltage-resistant I2C interface system of the present invention. The inverter module 131 is implemented to include a CMOS inverter circuit and a pull-down circuit. The CMOS inverter circuit is electrically connected to the pull-down circuit via a resistor R1.

[0066] The CMOS inverter circuit is specifically implemented as including a first field effect transistor M1 and a second field effect transistor M2; the first field effect transistor M1 is a P-type field effect transistor, the second field effect transistor M2 is an N-type field effect transistor, the source of the first field effect transistor M1 is connected to the power supply circuit 120, the drain is connected to the drain of the second field effect transistor M2, the gate of the first field effect transistor M1 is connected to the gate of the second field effect transistor M2, and the source of the second field effect transistor M2 is grounded.

[0067] The pull-down circuit is specifically implemented to include: a third field effect transistor M3, a fourth field effect transistor M4 and a fifth field effect transistor M5; the third field effect transistor M3, the fourth field effect transistor M4 and the fifth field effect transistor M5 are N-type field effect transistors and are connected in series in sequence: the drain of the third field effect transistor M3 is connected to the microelectronic device 110, the source is connected to the drain of the fourth field effect transistor M4, the source of the fourth field effect transistor M4 is connected to the drain of the fifth field effect transistor M5, the source of the fifth field effect transistor M5 is grounded, the gates of the third field effect transistor M3 and the fourth field effect transistor M4 are respectively connected to the high level selection module 133, and the gate of the fifth field effect transistor M5 is connected to the drain common contact of the CMOS inverter circuit through the resistor R1.

[0068] As a preferred implementation, the voltage divider module 132 is implemented as a field effect transistor series circuit module, specifically including: a sixth field effect transistor M6, a seventh field effect transistor M7, an eighth field effect transistor M8 and a first voltage divider output circuit D1 and a second voltage divider output circuit D2.

[0069] The source of the sixth field effect transistor M6 is connected to the microelectronic device 110, and the gate and the drain are short-circuited and respectively connected to the source of the seventh field effect transistor M7 and the first voltage-dividing output line D1, the gate and the drain of the seventh field effect transistor M7 are short-circuited and respectively connected to the source of the eighth field effect transistor M8 and the second voltage-dividing output line D2, and the gate and the drain of the eighth field effect transistor M8 are short-circuited and grounded.

[0070] As a preferred implementation, the high level selection module 133 is specifically implemented to include: a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, a twelfth field effect transistor M12; and a first high level output circuit H1 and a second high level output circuit H2.

[0071] The source of the ninth field effect transistor M9 and the gate of the tenth field effect transistor M10 are connected together to the first voltage-dividing output circuit D1, the drain of the ninth field effect transistor M9 and the source of the tenth field effect transistor M10 are connected together to one end of the first high-level output circuit H1, and the gate of the ninth field effect transistor M9 and the drain of the tenth field effect transistor M10 are connected together to one end of the second high-level output circuit H2.

[0072] The source of the eleventh field effect transistor M11 and the gate of the twelfth field effect transistor M12 are connected together and connected to the second voltage division output circuit D2, the drain of the eleventh field effect transistor M11 and the source of the twelfth field effect transistor M12 are connected together and connected to one end of the second high level output circuit H2, and the gate of the eleventh field effect transistor M11 and the drain of the tenth field effect transistor M10 are connected together and connected to the power supply circuit 120.

[0073] The other end of the first high level output circuit H1 is connected to the gate of the third field effect transistor M3 , and the other end of the second high level output circuit H2 is connected to the gate of the fourth field effect transistor M4 .

[0074] In some implementations, a plurality of voltage-dividing resistors may be connected in series to form a voltage-dividing module to divide the peripheral voltage of the microelectronic device (PAD).

[0075] As a preferred embodiment, the input module 135 is specifically implemented as including a voltage-dividing resistor R2 and a voltage-dividing resistor R3, a filter capacitor C2 and a Schmitt trigger S; one end of the voltage-dividing resistor R2 is connected to the microelectronic device 110, and the other end is connected to one end of the voltage-dividing resistor R3, the other end of the voltage-dividing resistor R3 is connected to the drain of the eighth field effect transistor M8, the source of the second field effect transistor M2, the source of the fifth field effect transistor M5, one end of the filter capacitor C2 and the first feedback end of the Schmitt trigger and then grounded; the second feedback end of the Schmitt trigger is connected to the other end of the filter capacitor C2 and then connected between the voltage-dividing resistor R2 and the voltage-dividing resistor R3.

[0076] like Figure 2 , Figure 2 The diagram of the connection of the electronic components of the voltage-resistant I2C interface system of the present invention; the working principle of the voltage-resistant processing circuit 130 in the present application: when the circuit works normally and outputs a high level, the input signal is 1.8V, the inverter module 131 composed of the first field effect tube M1 and the second field effect tube M2 outputs 0V, the fifth field effect tube M5 is turned off, and the voltage on the microelectronic device 110 (PAD) is pulled to 5V by the external 5V power supply through the pull-up resistor. At this time, the first voltage-dividing output line D1 and the second voltage-dividing output line D2 in the voltage-dividing module 132 The voltages of the first high-level output circuit H1 and the second high-level output circuit H2 are respectively about 3.3V and 1.7V. After the voltages of the two circuits pass through the high-level selection module 133 composed of the ninth field effect tube M9, the tenth field effect tube M10, the eleventh field effect tube M11, and the twelfth field effect tube M12, the voltages of the first high-level output circuit H1 and the second high-level output circuit H2 are respectively 3.3V and 1.8V. So far, the voltage difference between any two ends of all field effect tubes in the voltage division module 132 and the high-level selection module 133 is within 1.8V, which effectively avoids the risk of voltage resistance. On the input path, the ratio of the second resistor R2 and the third resistor R3 is reasonably set so that the output voltage after voltage division is about 1.8V, so that the Schmitt trigger schmitt can recognize it as a high level and output a 1.8V output signal, while avoiding the risk of voltage resistance caused by the input voltage of the Schmitt trigger schmitt exceeding 1.8V. In addition, the second resistor R2, the third resistor R3 and the second capacitor C2 form a first-order filter to filter out the burr problem required to be filtered out in the I2C protocol.

[0077] When the circuit works normally and outputs a low level of 0V, the input signal is 0V, the inverter module 131 composed of the first field effect transistor M1 and the second field effect transistor M2 outputs 1.8V, the fifth field effect transistor M5 is turned on, and the voltage on the PAD is pulled to the ground 0V by the turned-on field effect transistors M3, M4, and M5. At this time, the voltages of the first voltage-dividing output circuit D1 and the first voltage-dividing output circuit D2 in the voltage-dividing module 132 are both 0V. After the voltages of these two circuits pass through the high level selection module 133 composed of the ninth field effect transistor M9, the tenth field effect transistor M10, the eleventh field effect transistor M11, and the twelfth field effect transistor M12, since the power supply VCC is 1.8V, the voltages of the first high level output circuit H1 and the second high level output circuit H2 are both 1.8V, and the field effect transistors M3, M4, and M5 remain in the on state, ensuring that the voltage on the PAD is pulled to the ground 0V without generating uncontrollable jitter or burrs. On the input path, the voltage divided by the second resistor R2 and the third resistor R3 is 0V, and the Schmitt trigger schmitt outputs an output signal of 0V.

[0078] When the power supply VCC is powered off to 0V and the circuit does not work properly, the inverter module 131 composed of the first field effect transistor M1 and the second field effect transistor M2 outputs 0V, and the fifth field effect transistor M5 is turned off. If the voltage on the PAD is pulled to 5V by the external 5V power supply through the pull-up resistor, the voltages of the first voltage-dividing output circuit D1 and the second voltage-dividing output circuit D2 in the voltage-dividing module 132 are approximately 3.3V and 1.7V respectively. After the voltages of these two circuits pass through the high-level selection module 133 composed of the ninth field effect transistor M9, the tenth field effect transistor M10, the eleventh field effect transistor M11, and the twelfth field effect transistor M12, the voltages of the first high-level output circuit H1 and the second high-level output circuit H2 are 3.3V and 1.7V respectively. At this time, the voltage difference between any two ends of all the field effect transistors in the voltage-dividing module 132 and the high-level selection module 133 is within 1.8V, which effectively protects the circuit from the risk of voltage resistance.

[0079] As a preferred embodiment, the voltage-resistant I2C interface system also includes a slope control module 134; the slope control module 134 is used to form a fixed slope through negative feedback to control the rising edge and falling edge of the microelectronic device 110 (PAD) to meet the requirements of the I2C communication protocol, and the slope control module 134 includes a resistor R1 and a capacitor C1; one end of the resistor R1 is connected to the drain of the first field effect transistor M1 and the second field effect transistor M2, the other end of the resistor R1 is connected to one end of the capacitor C1 and the gate of the fifth field effect transistor M5, and the other end of the capacitor C1 is connected to the drain of the third field effect transistor M3 and the source of the sixth field effect transistor M6. The capacitor C1 in the slope control module 134 needs to be implemented using a metal capacitor so that it is not limited by the 5V voltage resistance.

[0080] The voltage-resistant I2C interface system of the present invention is implemented by applying the peripheral application circuit 300 to the peripheral voltage division of the microelectronic device 110, and the high-level selection module 133 shields the low-level voltage signal and outputs a high-level voltage signal, so that the voltage difference between any two ends of all field effect tubes in the system is within 1.8V, effectively avoiding the risk of voltage resistance, and shaping and filtering the waveform signal input to the chip, thereby improving the stability of the input voltage.

[0081] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A voltage-resistant I2C interface system, characterized in that: include: Power supply circuits, microelectronic devices, voltage-resistant circuits, and I2C interface circuits in electronic equipment; And peripheral application circuits; Wherein, the voltage-resistant processing circuit includes an inverter module, a voltage divider module, a high-level selection module and an input module. The inverter module is electrically connected to the voltage divider module, the high-level selection module and the input module respectively, and is used to achieve a 180-degree reversal of the input level signal. The voltage divider module is electrically connected to the inverter module, the high-level selection module and the input module respectively, and is used to divide the peripheral voltage applied to the microelectronic device by the peripheral application circuit. The high-level selection module is electrically connected to the inverter module, the voltage divider module and the input module respectively, and is used to shield the low-level voltage signal and output the high-level voltage signal to maintain the voltage difference between the two ends of the device stable. The input module is used to filter and shape the level signal input from the processing circuit to the internal chip of the electronic device; The peripheral application circuit is electrically connected to the power supply circuit and the microelectronic device arranged in the device through the I2C interface circuit; The I2C interface circuit, the microelectronic device, and the voltage resistance processing circuit are respectively connected to the power supply circuit, and: The voltage-resistant processing circuit is also electrically connected to the microelectronic device to limit the voltage transmitted from the peripheral application circuit to the microelectronic device within the working voltage of the microelectronic device to improve the voltage-resistant performance.

2. The voltage-resistant I2C interface system according to claim 1, characterized in that: The inverter module includes a CMOS inverter circuit and a pull-down circuit. The CMOS inverter circuit is electrically connected to the pull-down circuit via a resistor R1.

3. The voltage-resistant I2C interface system according to claim 2, characterized in that: The CMOS inverter circuit comprises: A first field effect transistor M1 and a second field effect transistor M2; The first field effect transistor M1 is a P-type field effect transistor, the second field effect transistor M2 is an N-type field effect transistor, the source of the first field effect transistor M1 is connected to the power supply circuit, the drain is connected to the drain of the second field effect transistor M2, the gate of the first field effect transistor M1 is connected to the gate of the second field effect transistor M2, and the source of the second field effect transistor M2 is grounded.

4. The voltage-resistant I2C interface system according to claim 3, characterized in that: The pull-down circuit comprises: A third field effect transistor M3, a fourth field effect transistor M4 and a fifth field effect transistor M5; The third field effect transistor M3, the fourth field effect transistor M4 and the fifth field effect transistor M5 are N-type field effect transistors and are connected in series in sequence: the drain of the third field effect transistor M3 is connected to the microelectronic device, the source is connected to the drain of the fourth field effect transistor M4, the source of the fourth field effect transistor M4 is connected to the drain of the fifth field effect transistor M5, the source of the fifth field effect transistor M5 is grounded, the gates of the third field effect transistor M3 and the fourth field effect transistor M4 are respectively connected to the high level selection module, and the gate of the fifth field effect transistor M5 is connected to the drain common contact of the CMOS inverter circuit through the resistor R1.

5. The voltage-resistant I2C interface system according to claim 4, characterized in that: The voltage divider module is a field effect tube series circuit module, comprising: a sixth field effect transistor M6, a seventh field effect transistor M7, and an eighth field effect transistor M8; and A first voltage-dividing output circuit D1 and a second voltage-dividing output circuit D2; The source of the sixth field effect transistor M6 is connected to the microelectronic device, and the gate and the drain are short-circuited and respectively connected to the source of the seventh field effect transistor M7 and the first voltage-dividing output line D1, the gate and the drain of the seventh field effect transistor M7 are short-circuited and respectively connected to the source of the eighth field effect transistor M8 and the second voltage-dividing output line D2, and the gate and the drain of the eighth field effect transistor M8 are short-circuited and grounded.

6. The voltage-resistant I2C interface system according to claim 5, characterized in that: The high level selection module comprises: a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, and a twelfth field effect transistor M12; and A first high level output circuit H1 and a second high level output circuit H2; The source of the ninth field effect transistor M9 and the gate of the tenth field effect transistor M10 are connected together and connected to the first voltage-dividing output circuit D1, the drain of the ninth field effect transistor M9 and the source of the tenth field effect transistor M10 are connected together and connected to one end of the first high-level output circuit H1, and the gate of the ninth field effect transistor M9 and the drain of the tenth field effect transistor M10 are connected together and connected to one end of the second high-level output circuit H2; The source of the eleventh field effect transistor M11 and the gate of the twelfth field effect transistor M12 are connected together and then connected to the second voltage-dividing output circuit D2, the drain of the eleventh field effect transistor M11 and the source of the twelfth field effect transistor M12 are connected together and then connected to one end of the second high-level output circuit H2, and the gate of the eleventh field effect transistor M11 and the drain of the twelfth field effect transistor M12 are connected together and then connected to the power supply circuit; The other end of the first high level output circuit H1 is connected to the gate of the third field effect transistor M3 , and the other end of the second high level output circuit H2 is connected to the gate of the fourth field effect transistor M4 .

7. The voltage-resistant I2C interface system according to claim 6, characterized in that: The input module comprises: Voltage dividing resistors R2 and R3, filter capacitor C2 and Schmitt trigger; One end of the voltage-dividing resistor R2 is connected to the microelectronic device, and the other end is connected to one end of the voltage-dividing resistor R3. The other end of the voltage-dividing resistor R3 is connected to the drain of the eighth field effect transistor M8, the source of the second field effect transistor M2, the source of the fifth field effect transistor M5, one end of the filter capacitor C2 and the first feedback end of the Schmitt trigger schmitt and then grounded; The second feedback terminal of the Schmitt trigger and the other end of the filter capacitor C2 are connected together and then connected between the voltage-dividing resistor R2 and the voltage-dividing resistor R3.

8. The voltage-resistant I2C interface system according to any one of claims 5 to 7, characterized in that: The system further comprises: Slope control module; The slope control module is used to form a fixed slope through negative feedback to control the rising edge and falling edge of the microelectronic device, including: Resistor R1 and capacitor C1; One end of the resistor R1 is connected to the drains of the first field effect transistor M1 and the second field effect transistor M2, the other end of the resistor R1 is connected to one end of the capacitor C1 and the gate of the fifth field effect transistor M5, and the other end of the capacitor C1 is connected to the drain of the third field effect transistor M3 and the source of the sixth field effect transistor M6.

9. The voltage-resistant I2C interface system according to claim 8, characterized in that: The operating voltage of the microelectronic device is 1.8V, and the operating voltage of the peripheral application circuit is 5V.

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