Display panel and electronic device

Abstract

A display panel and an electronic device, the display panel comprising: a substrate substrate; and pixels disposed on the substrate substrate, wherein the pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel includes a first sub-pixel driving circuit and a first light-emitting element driven by the first sub-pixel driving circuit, the second sub-pixel includes a second sub-pixel driving circuit and a second light-emitting element driven by the second sub-pixel driving circuit, the first sub-pixel driving circuit and the second sub-pixel driving circuit are arranged in sequence along a first direction parallel to the substrate substrate and both extend along a second direction, the second direction is parallel to the substrate substrate and intersects with the first direction, wherein the first light-emitting element includes a first anode electrically connected to the first sub-pixel driving circuit, the second light-emitting element includes a second anode electrically connected to the second sub-pixel driving circuit, and the orthographic projection of each of the first anode and the second anode on the substrate substrate partially covers the orthographic projection of the first sub-pixel driving circuit on the substrate substrate and the orthographic projection of the second sub-pixel driving circuit on the substrate substrate, and the orthographic projection of the first anode on the substrate substrate does not overlap with the orthographic projection of the second anode on the substrate substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and an electronic device. Background Art

[0002] As a brand-new display technology, transparent display enables an observer to see the background behind the display screen through the display screen. This novel display effect broadens the application fields of displays and thus has received extensive attention.

[0003] Disclosed Content

[0004] Some embodiments of the present disclosure provide a display panel, including: a substrate; and pixels disposed on the substrate, wherein each pixel includes a first sub-pixel and a second sub-pixel, the first sub-pixel includes a first sub-pixel driving circuit and a first light-emitting element driven by the first sub-pixel driving circuit, the second sub-pixel includes a second sub-pixel driving circuit and a second light-emitting element driven by the second sub-pixel driving circuit, the first sub-pixel driving circuit and the second sub-pixel driving circuit are sequentially arranged in a first direction parallel to the substrate and both extend in a second direction, the second direction is parallel to the substrate and intersects with the first direction, wherein the first light-emitting element includes a first anode electrically connected to the first sub-pixel driving circuit, the second light-emitting element includes a second anode electrically connected to the second sub-pixel driving circuit, and the orthographic projection of each of the first anode and the second anode on the substrate partially covers the orthographic projection of the first sub-pixel driving circuit on the substrate and the orthographic projection of the second sub-pixel driving circuit on the substrate, and the orthographic projection of the first anode on the substrate does not overlap with the orthographic projection of the second anode on the substrate.

[0005] In some embodiments, both the first sub-pixel driving circuit and the second sub-pixel driving circuit include a detection transistor, a storage capacitor, and a switching transistor. In the second direction, the detection transistor and the switching transistor are respectively located on both sides of the storage capacitor. The orthographic projection of one of the first anode and the second anode on the substrate at least partially covers the orthographic projection of the detection transistor in the first sub-pixel driving circuit on the substrate and at least partially covers the orthographic projection of the detection transistor in the second sub-pixel driving circuit on the substrate. The orthographic projection of the other of the first anode and the second anode on the substrate at least partially covers the orthographic projection of the switching transistor in the first sub-pixel driving circuit on the substrate and at least partially covers the orthographic projection of the switching transistor in the second sub-pixel driving circuit on the substrate.

[0006] In some embodiments, the positive projection of one of the first anode and the second anode on the substrate covers the positive projection of a first portion of the storage capacitor in the first sub-pixel driving circuit on the substrate and covers the positive projection of a first portion of the storage capacitor in the second sub-pixel driving circuit on the substrate. The positive projection of the other of the first anode and the second anode on the substrate covers the positive projection of a second portion of the storage capacitor in the first sub-pixel driving circuit on the substrate and covers the positive projection of a second portion of the storage capacitor in the second sub-pixel driving circuit on the substrate. In each of the first sub-pixel driving circuit and the second sub-pixel driving circuit, the first portion of the storage capacitor is closer to the detection transistor than the second portion of the storage capacitor.

[0007] In some embodiments, the positive projection of one of the first anode and the second anode on the substrate completely covers the positive projection of the detection transistor in the first sub-pixel driving circuit on the substrate and completely covers the positive projection of the detection transistor in the second sub-pixel driving circuit on the substrate. The positive projection of the other of the first anode and the second anode on the substrate completely covers the positive projection of the switching transistor in the first sub-pixel driving circuit on the substrate and completely covers the positive projection of the switching transistor in the second sub-pixel driving circuit on the substrate.

[0008] In some embodiments, the pixel further includes a third sub-pixel and a fourth sub-pixel. The third sub-pixel includes a third sub-pixel driving circuit and a third light-emitting element driven by the third sub-pixel driving circuit. The fourth sub-pixel includes a fourth sub-pixel driving circuit and a fourth light-emitting element driven by the fourth sub-pixel driving circuit. The first sub-pixel driving circuit, the second sub-pixel driving circuit, the third sub-pixel driving circuit, and the fourth sub-pixel driving circuit are arranged in sequence along a first direction parallel to the substrate and all extend along the second direction;

[0009] Wherein, the third light-emitting element includes a third anode electrically connected to the third sub-pixel driving circuit, the fourth light-emitting element includes a fourth anode electrically connected to the fourth sub-pixel driving circuit. The positive projection of each of the third anode and the fourth anode on the substrate partially covers the positive projection of the third sub-pixel driving circuit on the substrate and the positive projection of the fourth sub-pixel driving circuit on the substrate. Any two of the positive projections of the first anode, the second anode, the third anode, and the fourth anode on the substrate do not overlap.

[0010] In some embodiments, both the third sub-pixel driving circuit and the fourth sub-pixel driving circuit include a detection transistor, a storage capacitor, and a switching transistor. In the second direction, in each sub-pixel driving circuit of the third sub-pixel driving circuit and the fourth sub-pixel driving circuit, the detection transistor and the switching transistor are respectively located on both sides of the storage capacitor; wherein, a positive projection of one of the third anode and the fourth anode on the substrate at least partially covers a positive projection of the detection transistor in the third sub-pixel driving circuit on the substrate and at least partially covers a positive projection of the detection transistor in the fourth sub-pixel driving circuit on the substrate, and a positive projection of the other of the third anode and the fourth anode on the substrate at least partially covers a positive projection of the switching transistor in the third sub-pixel driving circuit on the substrate and at least partially covers a positive projection of the switching transistor in the fourth sub-pixel driving circuit on the substrate.

[0011] In some embodiments, a positive projection of one of the third anode and the fourth anode on the substrate covers a positive projection of a first portion of the storage capacitor in the third sub-pixel driving circuit on the substrate and covers a positive projection of a first portion of the storage capacitor in the fourth sub-pixel driving circuit on the substrate, and a positive projection of the other of the third anode and the fourth anode on the substrate covers a positive projection of a second portion of the storage capacitor in the third sub-pixel driving circuit on the substrate and covers a positive projection of a second portion of the storage capacitor in the fourth sub-pixel driving circuit on the substrate. In each of the third sub-pixel driving circuit and the fourth sub-pixel driving circuit, the first portion of the storage capacitor is closer to the detection transistor than the second portion of the storage capacitor.

[0012] In some embodiments, a positive projection of one of the third anode and the fourth anode on the substrate completely covers a positive projection of the detection transistor in the third sub-pixel driving circuit on the substrate and completely covers a positive projection of the detection transistor in the fourth sub-pixel driving circuit on the substrate, and a positive projection of the other of the third anode and the fourth anode on the substrate completely covers a positive projection of the switching transistor in the third sub-pixel driving circuit on the substrate and completely covers a positive projection of the switching transistor in the fourth sub-pixel driving circuit on the substrate.

[0013] In some embodiments, the first sub-pixel driving circuit, the second sub-pixel driving circuit,

[0014] Each sub-pixel driving circuit in the third sub-pixel driving circuit and the fourth sub-pixel driving circuit further includes: a driving transistor, located on a side of the storage capacitor away from the detection transistor and between the storage capacitor and the switching transistor, the driving transistor including a source electrode, a gate electrode, and a drain electrode arranged in sequence away from the storage capacitor in the second direction, the detection transistor including a source electrode, a gate electrode, and a drain electrode arranged in sequence away from the storage capacitor in the second direction, the storage capacitor including a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode stacked in sequence on the substrate, and the source electrode of the driving transistor, the third capacitor electrode, and the source electrode of the detection transistor are arranged on the same layer and connected to each other as an integrated structure.

[0015] In some embodiments, the display panel further includes: a source-drain metal layer including the integrated structure in each sub-pixel driving circuit; an anode layer located on a side of the source-drain metal layer away from the substrate, including a first anode, a second anode, a third anode, and a fourth anode; and a planarization layer provided on a side of the source-drain metal layer away from the substrate and on a side of the anode layer facing the substrate. Wherein, the planarization layer is provided with: a first anode via through which the first anode is electrically connected to the integrated structure of the first sub-pixel driving circuit; a second anode via through which the second anode is electrically connected to the integrated structure of the second sub-pixel driving circuit; a third anode via through which the third anode is electrically connected to the integrated structure of the third sub-pixel driving circuit; and a fourth anode via through which the fourth anode is electrically connected to the integrated structure of the fourth sub-pixel driving circuit.

[0016] In some embodiments, the orthographic projection of one of the first anode via and the second anode via on the substrate falls within the orthographic projection of the source electrode of the detection transistor in the sub-pixel driving circuit electrically connected to the one anode via on the substrate; the orthographic projection of the other anode via of the first anode via and the second anode via on the substrate falls within the orthographic projection of the third capacitive electrode of the storage capacitor in the sub-pixel driving circuit electrically connected to the other anode via on the substrate, and is located in the second direction between the orthographic projection of the source electrode of the detection transistor in the sub-pixel driving circuit electrically connected to the other anode via on the substrate and the orthographic projection of the source electrode of the driving transistor in the sub-pixel driving circuit electrically connected to the other anode via on the substrate. The orthographic projection of one of the third anode via and the fourth anode via on the substrate falls within the orthographic projection of the source electrode of the detection transistor in the sub-pixel driving circuit electrically connected to the one anode via on the substrate; the orthographic projection of the other anode via of the third anode via and the fourth anode via on the substrate falls within the orthographic projection of the third capacitive electrode of the storage capacitor in the sub-pixel driving circuit electrically connected to the other anode via on the substrate, and is located in the second direction between the orthographic projection of the source electrode of the detection transistor in the sub-pixel driving circuit electrically connected to the other anode via on the substrate and the orthographic projection of the source electrode of the driving transistor in the sub-pixel driving circuit electrically connected to the other anode via on the substrate.

[0017] In some embodiments, the straight line connecting the center of the orthographic projection of the first anode via on the substrate and the center of the orthographic projection of one of the third anode via and the fourth anode via on the substrate extends along the first direction, and the straight line connecting the center of the orthographic projection of the second anode via on the substrate and the center of the orthographic projection of the other of the third anode via and the fourth anode via on the substrate extends along the first direction.

[0018] In some embodiments, the positive projection of the first anode via on the substrate falls within the positive projection of the source electrode of the detection transistor in the first sub-pixel driving circuit on the substrate; the positive projection of the second anode via on the substrate falls within the positive projection of the third capacitive electrode of the storage capacitor in the second sub-pixel driving circuit on the substrate, and is located between the positive projection of the source electrode of the detection transistor in the second sub-pixel driving circuit on the substrate and the positive projection of the source electrode of the driving transistor in the second sub-pixel driving circuit on the substrate in the second direction. The positive projection of the third anode via on the substrate falls within the positive projection of the third capacitive electrode of the storage capacitor in the third sub-pixel driving circuit on the substrate, and is located between the positive projection of the source electrode of the detection transistor in the third sub-pixel driving circuit on the substrate and the positive projection of the source electrode of the driving transistor in the third sub-pixel driving circuit on the substrate in the second direction; the positive projection of the fourth anode via on the substrate falls within the positive projection of the source electrode of the detection transistor in the fourth sub-pixel driving circuit on the substrate.

[0019] In some embodiments, each sub-pixel driving circuit further includes a capacitive via, and the third capacitive electrode of the storage capacitor is electrically connected to the first capacitive electrode through the capacitive via.

[0020] In some embodiments, in the first sub-pixel driving circuit, the capacitive via is located on a side of the first anode via close to the storage capacitor and between the first anode via and the storage capacitor. A straight line connecting the center of the positive projection of the capacitive via on the substrate with the center of the positive projection of the first anode via on the substrate extends along a second direction. The positive projection of the capacitive via on the substrate and the positive projection of the first anode via on the substrate both fall within the positive projection of the first anode on the substrate. In the second sub-pixel driving circuit, the capacitive via is located on a side of the second anode via close to the detection transistor. A straight line connecting the center of the positive projection of the capacitive via on the substrate with the center of the positive projection of the second anode via on the substrate extends along the second direction. The positive projection of the capacitive via on the substrate and the positive projection of the second anode via on the substrate both fall within the positive projection of the second anode on the substrate. In the third sub-pixel driving circuit, the capacitive via is located on a side of the third anode via close to the detection transistor. A straight line connecting the center of the positive projection of the capacitive via on the substrate with the center of the positive projection of the third anode via on the substrate extends along the second direction. The positive projection of the capacitive via on the substrate and the positive projection of the third anode via on the substrate both fall within the positive projection of the third anode on the substrate. In the fourth sub-pixel driving circuit, the capacitive via is located on a side of the fourth anode via close to the storage capacitor and between the fourth anode via and the storage capacitor. A straight line connecting the center of the positive projection of the capacitive via on the substrate with the center of the positive projection of the fourth anode via on the substrate extends along the second direction. The positive projection of the capacitive via on the substrate and the positive projection of the fourth anode via on the substrate both fall within the positive projection of the fourth anode on the substrate.

[0021] In some embodiments, each sub-pixel driving circuit further includes a source via. The detection transistor of each sub-pixel driving circuit further includes an active layer. The source of the detection transistor is connected to the active layer through the source via. Among them, the positive projection of the source via in the first sub-pixel driving circuit on the substrate falls within the positive projection of the first anode via on the substrate, and the positive projection of the source via in the fourth sub-pixel driving circuit on the substrate falls within the positive projection of the fourth anode via on the substrate.

[0022] In some embodiments, the display panel further includes: a pixel definition layer having: a first opening for accommodating the light-emitting material layer of the first light-emitting element; a second opening for accommodating the light-emitting material layer of the second light-emitting element; a third opening for accommodating the light-emitting material layer of the third light-emitting element; and a fourth opening for accommodating the light-emitting material layer of the fourth light-emitting element, wherein a positive projection of the first opening on the substrate falls within a positive projection of the first anode on the substrate, a positive projection of the second opening on the substrate falls within a positive projection of the second anode on the substrate, a positive projection of the third opening on the substrate falls within a positive projection of the third anode on the substrate, and a positive projection of the fourth opening on the substrate falls within a positive projection of the fourth anode on the substrate.

[0023] In some embodiments, a positive projection of the first opening on the substrate does not overlap with a positive projection of the first anode via on the substrate, and a positive projection of the first opening on the substrate does not overlap with a positive projection of the capacitance via of the first sub-pixel driving circuit on the substrate; a positive projection of the second opening on the substrate does not overlap with a positive projection of the second anode via on the substrate, and a positive projection of the second opening on the substrate does not overlap with a positive projection of the capacitance via of the second sub-pixel driving circuit on the substrate; a positive projection of the third opening on the substrate does not overlap with a positive projection of the third anode via on the substrate, and a positive projection of the third opening on the substrate does not overlap with a positive projection of the capacitance via of the third sub-pixel driving circuit on the substrate; a positive projection of the fourth opening on the substrate does not overlap with a positive projection of the fourth anode via on the substrate, and a positive projection of the fourth opening on the substrate does not overlap with a positive projection of the capacitance via of the fourth sub-pixel driving circuit on the substrate.

[0024] In some embodiments, the first anode, the second anode, the third anode, and the fourth anode are arranged in a 2×2 matrix, wherein the first anode and the second anode are arranged side by side along the second direction, and the third anode and the fourth anode are arranged side by side along the second direction.

[0025] In some embodiments, the pixel has a light-transmitting region and a display region arranged side by side along a first direction, and the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are located in the display region.

[0026] In some embodiments, the second direction is perpendicular to the first direction.

[0027] In some embodiments, the display panel is an OLED display panel.

[0028] Some embodiments of the present disclosure provide an electronic device including the display panel described in the foregoing embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments read with reference to the accompanying drawings:

[0030] Figure 1 FIG. is a plan view of a transparent display panel according to some embodiments of the present disclosure;

[0031] Figure 2 is Figure 1 an enlarged view of region A in;

[0032] Figure 3 FIG. is a cross-sectional structural view of a display area of a single pixel of a transparent display panel according to some embodiments of the present disclosure;

[0033] Figure 4 FIG. is a plan view of a single pixel of a transparent display panel according to some embodiments of the present disclosure;

[0034] Figure 5 FIG. is a circuit diagram of a single sub-pixel according to some embodiments of the present disclosure;

[0035] Figure 6 FIG. is a plan view of a single pixel of a transparent display panel after forming a pattern of a first metal layer during manufacturing according to some embodiments of the present disclosure;

[0036] Figure 7 is Figure 6 a cross-sectional structural view along line A-A in;

[0037] Figure 8 FIG. is a plan view of a single pixel of a transparent display panel after forming a pattern of an active material layer during manufacturing according to some embodiments of the present disclosure;

[0038] Figure 9 is Figure 8 a cross-sectional structural view along line A-A in;

[0039] Figure 10 FIG. is a plan view of a single pixel of a transparent display panel after forming a pattern of a second metal layer during manufacturing according to some embodiments of the present disclosure;

[0040] Figure 11 is Figure 10 a cross-sectional structural view along line A-A in;

[0041] Figure 12 Schematic plan view of a single pixel after forming a pattern of a third insulating layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure;

[0042] Figure 13 It is Figure 12 Schematic cross-sectional view along line A-A in

[0043] Figure 14 It is Figure 4 Schematic cross-sectional view along line A-A in

[0044] Figure 15 Schematic plan view of a single pixel after forming patterns of a fourth insulating layer and a planarization layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure;

[0045] Figure 16 It is Figure 15 Schematic cross-sectional view along line A-A in

[0046] Figure 17 Schematic plan view of a single pixel after forming a pattern of an anode layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure;

[0047] Figure 18 It is Figure 17 Schematic cross-sectional view along line A-A in

[0048] Figure 19 Schematic plan view of a single pixel after forming patterns of a pixel defining layer, a light emitting material layer, a cathode, and a packaging layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure;

[0049] Figure 20 It is Figure 19 Schematic cross-sectional view along line A-A in

[0050] Figure 21 Schematic distribution diagram of anodes in a single pixel according to a comparative example of the present disclosure;

[0051] Figure 22 Schematic distribution diagram of anodes of a single pixel of a transparent display panel according to some embodiments of the present disclosure;

[0052] Figure 23 Schematic distribution diagram of anodes of a single pixel of a transparent display panel according to some embodiments of the present disclosure; and

[0053] Figure 24 Schematic distribution diagram of anodes of a single pixel of a transparent display panel according to some embodiments of the present disclosure. Detailed implementation manners

[0054] The present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only for explaining the relevant invention and not for limiting the invention. Additionally, it should be noted that for the sake of description, only the parts related to the invention are shown in the drawings.

[0055] It should be noted that, without conflict, the embodiments and features in the present disclosure may be combined with each other.

[0056] In addition, in the following detailed description, for the sake of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments may also be implemented without these specific details.

[0057] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, the first element may be named the second element, and similarly, the second element may be named the first element. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items.

[0058] It should be understood that when an element or layer is referred to as being "formed on" another element or layer, the element or layer may be directly or indirectly formed on the other element or layer. That is, for example, there may be intermediate elements or intermediate layers. In contrast, when an element or layer is referred to as being "directly formed on" another element or layer, there are no intermediate elements or intermediate layers. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (for example, "between" and "directly between", "adjacent" and "directly adjacent", etc.).

[0059] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the embodiments. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will also be understood that when the terms "comprise" and / or "include" are used herein, it indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof.

[0060] In this document, unless otherwise specified, the expressions "located on the same layer" and "arranged on the same layer" generally mean that: the first component and the second component can be made of the same material and can be formed by the same lithography process. The expressions "located on different layers" and "arranged on different layers" generally mean that: the first component and the second component are formed by different lithography processes.

[0061] In this document, unless otherwise specified, the expression "pixel" generally refers to a pixel structure, and the expression "sub-pixel" generally refers to a sub-pixel structure.

[0062] In the following embodiments of the present disclosure, the transparent display panel is taken as an example of an OLED display panel. Those skilled in the art can understand that the transparent display panel can also be other types of display panels, such as a PLED display panel, a quantum dot display panel, etc.

[0063] Some embodiments of the present disclosure provide a display panel, specifically a transparent display panel. Figure 1 A plan view of a transparent display panel according to some embodiments of the present disclosure is shown, as Figure 1 shown, the transparent display panel 100 includes a substrate 10 and a plurality of pixels P arranged in an array on the substrate 10. The row direction of the pixel array is, for example, the first direction X, and the column direction is, for example, the second direction Y. The first direction X and the second direction Y intersect with each other, for example, perpendicularly.

[0064] Figure 2 For Figure 1 the enlarged schematic view of region A in Figure 2 only four pixels P are shown. As Figure 2 shown, each pixel P includes a light-transmitting region TA and a display region DA. In each pixel P, the light-transmitting region TA and the display region DA are arranged side by side in the first direction. In this embodiment, as Figure 2 shown, in each pixel P, the light-transmitting region TA and the display region DA are arranged left and right, and the light-transmitting region TA is located on the left side of the display region DA. Those skilled in the art can understand that in other embodiments, the light-transmitting region TA can be located on the right side of the display region DA. In some embodiments, it can also be that in some pixels, the light-transmitting region TA is located on the left side of the display region DA, and in other pixels, the light-transmitting region TA is located on the right side of the display region DA.

[0065] Figure 3 A cross-sectional structure schematic view of the display region of a pixel according to some embodiments of the present disclosure is shown, as Figure 3 shown, in the display region DA of the pixel P, as Figure 3As shown, a first metal layer 20, a first insulating layer 30, an active material layer 40, a second insulating layer 50, a second metal layer 60, a third insulating layer 70, a third metal layer 80, a fourth insulating layer 90, a fifth insulating layer 110, a first electrode layer 120, a pixel defining layer 130, a light emitting material layer 140, a second electrode layer 150, a packaging layer 160, a color filter layer CF, a black matrix layer BM, and a packaging cover plate 170 are sequentially disposed on a substrate 10. In some embodiments, the fourth insulating layer 90 may be omitted.

[0066] The substrate 10 and the packaging cover plate 170 are made of, for example, a glass material with good light transmission characteristics. The first insulating layer 30 is, for example, a buffer layer, which may also be referred to as the buffer layer 30 in this text. The second insulating layer 50 is, for example, a gate insulating layer, which may also be referred to as the gate insulating layer 50 in the text. The third insulating layer 70 is, for example, an interlayer dielectric layer, which may also be referred to as the interlayer dielectric layer 70 in this text. The fourth insulating layer 90 is, for example, a passivation layer, which may also be referred to as the passivation layer 90 in this text. The fifth insulating layer 110 is, for example, a planarization layer, which may also be referred to as the planarization layer 110 in this text. The planarization layer 110 is formed of, for example, an organic material such as resin, and the pixel defining layer 130 is also formed of an organic material. In some embodiments, since the planarization layer 110 itself has an insulating function, the passivation layer 90 may not be provided.

[0067] It can be understood that Figure 3 schematically shows a cross-sectional layer structure of a single sub-pixel in the pixel display area, which is only used to show the layers in the display area and does not reflect the specific positions of the layers in the plan view.

[0068] As Figure 3 shown, a single sub-pixel includes a driving transistor DT. The first metal layer 20 includes a shielding layer 21. The active material layer 40 includes an active layer 41 of the driving transistor DT. The shielding layer can be used to shield the active layer 41 of the driving transistor DT to prevent external light from entering the active layer 41 of the driving transistor DT and causing adverse effects on the display of the sub-pixel. The second metal layer 60 includes a gate 61 of the driving transistor DT. The third metal layer 80 includes a first electrode 81 of the driving transistor DT, for example, a drain, and a second electrode 82, for example, a source. The first electrode layer 120 is, for example, an anode layer, which is also referred to as the anode layer 120 in this text and includes an anode of a light emitting element D in the sub-pixel. The second electrode layer 150 is, for example, a cathode layer, which is also referred to as the cathode layer 150 in this text and includes a cathode of a light emitting element D in the sub-pixel. As an example, the packaging layer 160 may include a first inorganic layer 161, an organic layer 162, and a second inorganic layer 163 stacked in sequence along a direction perpendicular to the substrate 10.

[0069] In some embodiments, the color filter layer CF and the black matrix BM may be pre-formed on the cover plate 170, and then the cover plate 170 with the color filter layer CF and the black matrix BM is aligned and bonded to the display substrate after the encapsulation layer 160 is formed on the substrate 10 to form the transparent display panel 100. In some alternative embodiments, the color filter layer CF may be disposed on the display substrate including the substrate 10, for example, directly on the encapsulation layer 160 or between the planarization layer 110 and the third metal layer 80, and then the cover plate 170 is aligned and bonded to the display substrate to form the transparent display panel 100. In some embodiments, the black matrix BM may also be replaced by stacked color filter layers CF of different colors.

[0070] In some embodiments, the light-emitting material layer 140 is formed over the entire surface by evaporation, as Figure 3 shown. For example, all the light-emitting elements D emit white light, and the color filter layer CF transmits different colors in corresponding different sub-pixel regions, thereby realizing color display.

[0071] In some embodiments, the light-emitting material layer 140 may be formed in the opening regions of the pixel defining layer 130 by printing. Light-emitting material layers 140 emitting different colors of light may be printed for different color sub-pixels. In this case, the color filter layer CF may be omitted, and even the cover plate 170 and the black matrix may be omitted.

[0072] In some embodiments, at least one of the first metal layer 20, the second metal layer 60, the third metal layer 80, the anode layer 120, the planarization layer 110, the pixel defining layer 130, the black matrix BM, and the color filter layer CF that is opaque or has poor light-transmitting effect is not disposed in the light-transmitting region TA. For example, the above-mentioned layers are not disposed in the light-transmitting region TA to ensure the transparent effect of the light-transmitting region TA.

[0073] The single-pixel structure and the pixel driving circuit of a single pixel in the transparent display panel are introduced in detail in the following embodiments.

[0074] Figure 4 For Figure 2 the enlarged schematic view of region B in, a planar structure schematic view of the display region of a single pixel according to some embodiments of the present disclosure is shown, as Figure 4As shown, the display area DA of pixel P includes four sub-pixels, namely the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel. For example, the four sub-pixels can be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel respectively. Those skilled in the art can understand that each sub-pixel includes a sub-pixel driving circuit and a light-emitting element D located on the sub-pixel driving circuit, and the light-emitting elements of the four sub-pixels can be adjusted in shape and arrangement according to actual needs, as long as it is ensured that the sub-pixel driving circuit of each sub-pixel can drive its corresponding light-emitting element D. In the art, a pixel defining layer is used to define the position and shape of the light-emitting area of the light-emitting element, and the light-emitting material layer of the light-emitting element is disposed in the opening of the pixel defining layer. The position and shape of the opening of the pixel defining layer can be adjusted according to actual needs to adjust the position and shape of the light-emitting material layer of the organic light-emitting element.

[0075] To clearly show the structure and positional relationship of each sub-pixel, Figure 4 the light-emitting elements of each sub-pixel and the pixel defining layer surrounding each light-emitting element are not shown. The sub-pixel driving circuits of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are mainly shown, that is, the first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4. As Figure 4 shown, the first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 all extend along the second direction Y, and are arranged side by side in sequence along the first direction X in pixel P. The first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 constitute the pixel driving circuit of pixel P. Thus, Figure 4 can also be used as a schematic diagram of the structure of the pixel driving circuit of a single pixel according to some embodiments of the present disclosure. In this embodiment, the first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 are arranged away from the light-transmitting area TA of pixel P in sequence.

[0076] In this embodiment, a pixel structure with four sub-pixels is used as an example. Those skilled in the art can understand that in other embodiments, a single pixel can have other numbers of sub-pixels, such as three, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0077] Figure 5 is a circuit diagram of a single sub-pixel according to an embodiment of the present disclosure. The following is combined with Figure 4 and Figure 5An explanation of a single pixel P in the embodiments of the present disclosure is provided.

[0078] As Figure 4 shown, each pixel P corresponds to a first gate line GL1, a second gate line GL2, a first power supply line VDDL, a second power supply line VSSL, a detection line SL, and four data lines DL. As Figure 5 shown, each of the first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 includes a first transistor T1 (also referred to as a switching transistor T1), a second transistor T2 (also referred to as a driving transistor T2), and a third transistor T3 (also referred to as a detection transistor T3), and a storage capacitor Cst. The first gate line GL1 provides a first control signal G1 for each sub-pixel driving circuit, the second gate line GL2 provides a second control signal G2 for each sub-pixel, the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 provide data signals Data for the first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 respectively, the first power supply line VDDL provides a constant first voltage signal, such as a VDD voltage signal, for each sub-pixel driving circuit, and the second power supply line VSSL provides a constant second voltage signal, such as a VSS voltage signal, for each sub-pixel driving circuit. The detection line SL is used to provide a reset signal to each pixel driving circuit and is used to sample and detect the electrical characteristics of each sub-pixel driving circuit, such as the threshold voltage of the second transistor T2, to achieve external compensation and obtain a better display effect.

[0079] Specifically, each sub-pixel driving circuit includes a switching transistor T1, a driving transistor T2, a detection transistor T3, and a storage capacitor Cst. The driving transistor T2 is the Figure 3 driving transistor DT in, the gate of the switching transistor T1 receives the first control signal G1 provided by the first gate line GL1, the first pole of the switching transistor T1, such as the drain, receives the data signal Data provided by the data line DL, and the second pole of the switching transistor T1, such as the source, is electrically connected to the second capacitor electrode CstE2 of the storage capacitor Cst and the gate of the driving transistor T2, and the three are electrically connected at the first node G. The switching transistor T1 is configured to write the data signal Data to the gate of the driving transistor T2 and the storage capacitor Cst in response to the first control signal G1.

[0080] The first pole of the driving transistor T2, for example, the drain, is electrically connected to the first power supply line VDDL through the first power supply connection line VDDLS, receives the first voltage signal provided by the first power supply line VDDL, for example, the VDD voltage signal, the second pole of the driving transistor T2, for example, the source, is electrically connected to the second capacitor electrode CstE2 of the storage capacitor Cst, and is configured to be electrically connected to the anode of the light-emitting element D. The driving transistor T2 is configured to control the current for driving the light-emitting element D under the control of the voltage of the gate of the driving transistor T2.

[0081] The gate of the detection transistor T3 receives the second control signal G2 provided by the second gate line GL2. The first pole of the detection transistor T3, for example, the source, is electrically connected to the second pole of the driving transistor T2 and the first capacitor electrode CstE1 of the storage capacitor Cst, and the three are electrically connected at the second node S. The second pole of the detection transistor T3, for example, the drain, is electrically connected to the detection line SL through the detection connection line SLS, obtains the reset signal from the detection line SL, and provides the sampling detection signal SEN to the detection line SL. The detection transistor T3 is configured to detect the electrical characteristics of the sub-pixel driving circuit to which it belongs in response to the second control signal G2 to achieve external compensation; the electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the switching transistor T1, or the threshold voltage, driving current, etc. of the light-emitting element.

[0082] The anode of the light-emitting element D is electrically connected to the second pole of the driving transistor T2, for example, the source. The cathode of the light-emitting element D is electrically connected to the second power supply line VSSL, for example, through a via hole, and accesses the VSS voltage signal. The light-emitting element D emits light based on the current flowing through it, and the light-emitting intensity is determined by the intensity of the current flowing through the light-emitting element D.

[0083] In some embodiments, the storage capacitor Cst may include a third capacitor electrode CstE3 electrically connected to the first capacitor electrode CstE1. The first capacitor electrode CstE1, the second capacitor electrode CstE2, and the third capacitor electrode CstE2 are sequentially stacked on the substrate 10. The first capacitor electrode CstE1 and the second capacitor electrode CstE2 have an overlapping region, and the first capacitor electrode CstE1 and the second capacitor electrode CstE2 form the first capacitor. The third capacitor electrode CstE3 and the second capacitor electrode CstE2 have an overlapping region, and the third capacitor electrode CstE3 and the second capacitor electrode CstE2 form the second capacitor. The storage capacitor Cst can be regarded as the parallel connection of the first capacitor and the second capacitor, thereby increasing the capacitance of the storage capacitor Cst.

[0084] In embodiments of the present disclosure, the transistors employed may all be thin film transistors or field effect transistors or other switching devices with the same characteristics. In the embodiments of the present disclosure, thin film transistors are taken as examples for illustration. The source and drain of the transistors adopted here may be symmetric in structure, so there may be no difference between them in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other as the second pole. In addition, the transistors can be classified into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages). It should be noted that in the descriptions herein, N-type transistors are taken as examples for illustration, but this does not limit the present disclosure.

[0085] As Figure 4 shown, within the region corresponding to a single pixel P, that is, Figure 4 within the range shown, both the first gate line GL1 and the second gate line GL2 extend along the first direction X, for example, in a straight line shape. The first gate line GL1 and the second gate line GL2 are respectively disposed on both sides of the light-transmitting region TA, that is, the light-transmitting region TA is sandwiched between the first gate line GL1 and the second gate line GL2. In other embodiments, the first gate line GL1 and the second gate line GL2 may also pass through the light-transmitting region TA. Within the region corresponding to a single pixel P, that is, Figure 4Within the shown range, the first power supply line VDDL, the second power supply line VSSL, the detection line SL, and the four data lines DL all extend along the second direction Y, for example, in a straight line shape. Specifically, the detection line SL is located between the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3. The first data line DL1 and the second data line DL2 are arranged between the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2. The first data line DL1 is closer to the first sub-pixel driving circuit SPC1 than the second data line DL2, and the second data line DL2 is closer to the second sub-pixel driving circuit SPC2 than the first data line DL1. That is, the first data line DL1 is located between the first sub-pixel driving circuit SPC1 and the second data line DL2, and the second data line DL2 is located between the first data line DL1 and the second sub-pixel driving circuit SPC2. The third data line DL3 and the fourth data line DL4 are arranged between the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4. The third data line DL3 is closer to the third sub-pixel driving circuit SPC3 than the fourth data line DL4, and the fourth data line DL4 is closer to the fourth sub-pixel driving circuit SPC4 than the third data line DL3. That is, the third data line DL3 is located between the third sub-pixel driving circuit SPC3 and the fourth data line DL4, and the fourth data line DL4 is located between the third data line DL3 and the fourth sub-pixel driving circuit SPC4. The second power supply line VSSL is located on the side of the first sub-pixel driving circuit SPC1 away from the first data line DL1, that is, between the light-transmitting region TA and the first sub-pixel driving circuit SPC1. The first power supply line VDDL is located on the side of the fourth sub-pixel driving circuit SPC4 away from the fourth data line DL4. In this embodiment, the structure of the first sub-pixel driving circuit SPC1 and the structure of the fourth sub-pixel driving circuit SPC4 are mirror-symmetrical with respect to the detection line SL, and the structure of the second sub-pixel driving circuit SPC2 and the structure of the third sub-pixel driving circuit SPC3 are mirror-symmetrical with respect to the detection line SL.

[0086] Figure 4 , Figures 6 - 14 FIG. [FIG. ID] is a schematic diagram of the manufacturing process of the display panel according to the embodiment of the present disclosure, showing the structure of a pixel P of the transparent display panel. In this embodiment, the transparent display panel is taken as an example of a top-emitting OLED display panel for illustration. A single pixel P includes a display area DA and a light-transmitting area TA. In the display area DA, a first sub-pixel driving circuit SPC1, a second sub-pixel driving circuit SPC2, a third sub-pixel driving circuit SPC3, and a fourth sub-pixel driving circuit SPC4 are arranged in sequence away from the light-transmitting area TA. The pixel driving circuit of each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0087] Figure 6is a schematic diagram of a planar structure of a single pixel after a pattern of a first metal layer is formed in a manufacturing process of a transparent display panel according to some embodiments of the present disclosure, Figure 7 for Figure 6 Schematic diagram of the cross-sectional structure along line AA. (It should be noted that Figure 6 The section position indicated by the line AA in FIG. 1 is consistent with the section position indicated by the line AA in other subsequent drawings. Figure 6 and 7 As shown, first, a pattern of a first metal layer 20 is formed on a substrate. Specifically, a first metal film is deposited on a substrate 10, and the first metal film is patterned by a patterning process to form a pattern of a first metal layer 20 on the substrate 10. The pattern of the first metal layer 20 includes a shielding layer 21 and a detection connection line SLS. Each sub-pixel driving circuit includes a shielding layer 21. The detection connection line SLS is a strip structure that spans four sub-pixel driving circuits and extends along a first direction X. The detection connection line SLS is configured to connect a detection line SL formed subsequently, so that the detection line SL provides a reset signal to each sub-pixel driving circuit, and is used to sample and detect the electrical characteristics of each sub-pixel driving circuit, such as the threshold voltage of the second transistor T2, to achieve external compensation. In some embodiments, the shielding layer 21 is a long rectangular strip and extends along the second direction Y. The shielding layer 21 is configured to shield the channel of each transistor formed subsequently, reduce the light intensity irradiated on the transistor, reduce the leakage current, and thus reduce the influence of light on the transistor characteristics. The middle portion of the shielding layer 21 (circled by the dotted box) serves as a capacitor electrode of the first capacitor, namely the first capacitor electrode CstE1, which is configured to form a first capacitor with the second capacitor electrode CstE2 formed subsequently. In the second direction Y, the length of the shielding layer 21 is greater than the distance between the gate of the switching transistor T1 formed subsequently and the gate of the detection transistor T3. In some embodiments, the length of the shielding layer 21 is greater than the distance between the drain of the switching transistor T1 formed subsequently and the drain of the third transistor T3. Figure 4 and Figure 6 As shown, the pattern of the first metal layer 20 in the first sub-pixel driving circuit SPC1 and the pattern of the first metal layer 20 in the fourth sub-pixel driving circuit SPC4 are mirror-symmetric with respect to the detection line SL formed subsequently. The pattern of the first metal layer 20 in the second sub-pixel driving circuit SPC2 and the pattern of the first metal layer 20 in the third sub-pixel driving circuit SPC3 are mirror-symmetric with respect to the detection line SL formed subsequently. After this patterning process, the shielding layer 21 and the detection connection line SLS are formed in the display area DA, and the first metal layer is not provided in the light-transmitting area TA.

[0088] Figure 8Schematic plan view of a single pixel after forming a pattern of an active material layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 9 is Figure 8 Schematic cross-sectional structure along A-A in Figure 8 、 9 shown, a pattern of the active material layer 40 is formed. Specifically, on the substrate 10 with the aforementioned pattern formed thereon, a first insulating thin film and an active material thin film, such as a metal oxide thin film, are sequentially deposited. The active material thin film is patterned through a patterning process to form a first insulating layer 30 covering the pattern of the first metal layer 20, and a pattern of the active material layer 40 formed on the first insulating layer 30. The active material layer 40 includes an active layer of the switching transistor T1 disposed in each sub-pixel driving circuit, also referred to as the first active layer T1a, an active layer of the driving transistor T2, also referred to as the second active layer T2a, an active layer of the detection transistor T3, also referred to as the third active layer T3a, and a second capacitor electrode CstE2. The orthographic projection of the second capacitor electrode CstE2 on the substrate 10 overlaps with the orthographic projection of the first capacitor electrode CstE1 on the substrate 10, and the first capacitor electrode CstE1 and the second capacitor electrode CstE2 form a first capacitor.

[0089] In some embodiments, the orthographic projections of the first active layer T1a, the second active layer T2a, and the third active layer T3a on the substrate 10 overlap with the orthographic projection of the shielding layer 21 on the substrate 10, such that the shielding layer 21 can block the channel regions of the switching transistor T1, the driving transistor T2, and the detection transistor T3, avoiding the influence of light on the channels and preventing the channels from affecting the display effect due to the generation of photocurrent leakage. Any two of the first active layer T1a, the second active layer T2a, the third active layer T3a, and the second capacitor electrode CstE2 are spaced apart, that is, there is no overlapping region between the orthographic projection of the first active layer T1a on the substrate 10, the orthographic projection of the second active layer T2a on the substrate 10, the orthographic projection of the third active layer T3a on the substrate 10, and the orthographic projection of the second capacitor electrode CstE2 on the substrate 10, which is beneficial for designing the channel width-to-length ratios of the switching transistor T1, the driving transistor T2, and the detection transistor T3 according to relevant requirements. In some embodiments, as Figure 8 and 9 shown, there is a spaced region 42 between the second capacitor electrode CstE2 and the third active layer T3a in the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4, and a notch region 43 is provided in the middle of the second capacitor electrode CstE2 in the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3. There is no active material layer 40 in the spaced region 42 and the notch region 43. In some embodiments, asFigure 4 Combined Figure 8 As shown, the pattern of the active material layer 40 in the first sub-pixel driving circuit SPC1 and the pattern of the active material layer 40 in the fourth sub-pixel driving circuit SPC4 are mirror-symmetrical with respect to the subsequently formed detection line SL. The pattern of the active material layer 40 in the second sub-pixel driving circuit SPC2 and the pattern of the active material layer 40 in the third sub-pixel driving circuit SPC3 are mirror-symmetrical with respect to the subsequently formed detection line SL. After this patterning process, the pattern of the active material layer 40 is formed in the display area DA and not in the light-transmitting area TA. The light-transmitting area TA includes the substrate 10 and the first insulating layer 30 provided on the substrate 10.

[0090] Figure 10 FIG. is a schematic plan view of a single pixel after forming the pattern of the second metal layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 11 Is Figure 10 The cross-sectional structure schematic diagram along line A-A in. As Figure 10 And 11 As shown, then the pattern of the second metal layer 60 is formed, including: depositing a second insulating thin film and a second metal thin film in sequence on the substrate 10 formed with the aforementioned pattern, and patterning the second insulating thin film and the second metal thin film through a patterning process to form the pattern of the second insulating layer 50 and the pattern of the second metal layer 60 provided on the second insulating layer 50. In some embodiments, the pattern of the second insulating layer 50 and the pattern of the second metal layer 60 are formed using the same mask and have the same pattern. The pattern of the second metal layer 60 includes the first gate line GL1, the second gate line GL2, the first power connection line VDDLS, the first auxiliary line 62, the second auxiliary line 63 corresponding to each pixel P, and the gates of the switching transistor T1, also known as the first gate T1g, the driving transistor T2, also known as the second gate T2g, and the detection transistor T3, also known as the third gate T3g formed in each sub-pixel driving circuit. The pattern of the second metal layer 60 also includes the first gate connection line 64 and the second gate connection line 65 formed in each sub-pixel driving circuit. As Figure 10 As shown, in the area corresponding to a single pixel P, that is, in the area shown in Figure 10 As shown, the first gate line GL1 and the second gate line GL2 are arranged in parallel and both extend linearly along the first direction X. The first gate line GL1 is located below the light-transmitting area TA, and the second gate line GL2 is located above the light-transmitting area TA. That is, the light-transmitting area TA is sandwiched between the first gate line GL1 and the second gate line GL2. Each sub-pixel driving circuit is also sandwiched between the first gate line GL1 and the second gate line GL2.

[0091] The first gate T1g extends along the first direction X and straddles the first active layer T1a, and is electrically connected to the first gate line GL1 through a first gate connection line 64 extending along the second direction Y. Specifically, the first gate T1g includes a connection end T1g1 and a free end T1g2, and the first gate connection line 64 includes a first end 641 and a second end 642. The first end 641 of the first gate connection line 64 is electrically connected to the first gate line GL1, and the second end 642 of the first gate connection line 64 is electrically connected to the connection end T1g1 of the first gate T1g. In some embodiments, the first gate T1g1, the first gate connection line 64, and the first gate line GL1 are an integral structure. The second gate T2g extends along the first direction X, straddles the second active layer T2a, and has an overlapping region with the second capacitive electrode CstE2. The third gate T3g extends along the first direction X, straddles the third active layer T3a, and is electrically connected to the second gate line GL2 through a second gate connection line 65 extending along the second direction Y. Specifically, the third gate T3g includes a connection end T3g1 and a free end T3g2, and the second gate connection line 65 includes a first end 651 and a second end 652. The first end 651 of the second gate connection line 65 is electrically connected to the second gate line GL2, and the second end 652 of the second gate connection line 65 is electrically connected to the connection end T3g1 of the third gate T3g. In some embodiments, the third gate T3g, the second gate connection line 65, and the second gate line GL2 are an integral structure.

[0092] The first auxiliary line 62 is formed in the region where the second power supply line VSSL is located, extends along the second direction Y, and is configured to electrically connect the subsequently formed second power supply line VSSL. Thus, the subsequently formed second power supply line VSSL is arranged in parallel with the first auxiliary line 62 through vias, thereby effectively reducing the impedance of the second power supply line VSSL. In some embodiments, the first auxiliary line 62 is located between the first gate T1g and the third gate T3g. Those skilled in the art can understand that the first auxiliary line 62 is not necessary, and in some embodiments, the first auxiliary line 62 can be omitted.

[0093] The second auxiliary line 63 is formed in the region where the first power supply line VDDL is located, extends along the second direction Y, and is configured to electrically connect the subsequently formed first power supply line VDDL. Thus, the subsequently formed first power supply line VDDL is arranged in parallel with the second auxiliary line 63 through vias, thereby effectively reducing the impedance of the first power supply line VDDL. In some embodiments, the second auxiliary line 63 is located between the first gate T1g and the third gate T3g. Those skilled in the art can understand that the second auxiliary line 63 is not necessary, and in some embodiments, the second auxiliary line 63 can be omitted.

[0094] The first power connection line VDDLS extends along the first direction X and straddles four sub-pixel driving circuits, and is configured to be electrically connected to the first power line VDDL formed subsequently. In some embodiments, the first power connection line VDDLS may be electrically connected to the second auxiliary line 63, and the two are, for example, an integral structure.

[0095] As Figure 11 shown, the pattern of the second insulating layer 50 is the same as the pattern of the second metal layer 60, that is, the second insulating layer 50 is located below the second metal layer 60, and there is no second insulating layer 50 in the area outside the second metal layer 60. As Figure 10 shown, except for the first power connection line VDDLS, the pattern of the second metal layer in the first sub-pixel driving circuit SPC1 and the pattern of the second metal layer in the fourth sub-pixel driving circuit SPC4 are mirror-symmetrical with respect to the detection line SL formed subsequently, and the pattern of the second metal layer in the second sub-pixel driving circuit SPC2 and the pattern of the second metal layer in the third sub-pixel driving circuit SPC3 are mirror-symmetrical with respect to the detection line SL formed subsequently.

[0096] In some embodiments, this process further includes a conductorization process. The conductorization process is to perform plasma processing using the pattern of the second metal layer 60 including the first gate T1g, the second gate T2g, and the third gate T3g as a mask after forming the pattern of the second metal layer 60. The active material layer 40 in the areas blocked by the first gate T1g, the second gate T2g, and the third gate T3g (that is, the area where the active material layer 40 overlaps with the first gate T1g, the second gate T2g, and the third gate T3g) serves as the channel region of the transistor respectively. The active material layer 40 in the area not blocked by the second metal layer 60 is conductorized to form a conductorized second capacitor electrode CstE2 and a conductorized source-drain region. After this patterning process, the pattern of the second metal layer 60 is formed in the display area DA and not in the light-transmitting area TA. The light-transmitting area TA includes the substrate 10 and the first insulating layer 30 provided on the substrate 10.

[0097] Figure 12 It is a schematic plan view of a single pixel after forming the pattern of the third insulating layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 13 For Figure 12 is the schematic cross-sectional structure along line A-A in Figure 12 and Figure 13As shown, a pattern of the third insulating layer 70 is then formed. Forming the pattern of the third insulating layer 70 includes: depositing a third insulating thin film on the substrate 10 on which the aforementioned pattern is formed, patterning the third insulating thin film through a patterning process to form a pattern of the third insulating layer 70 covering the aforementioned structure. A plurality of vias are formed in the third insulating layer 70. The plurality of vias include: a first via V1 and a second via V2 on both sides of the first gate T1g, a third via V3 and a fourth via V4 on both sides of the second gate T2g, a fifth via V5 and a sixth via V6 on both sides of the third gate T3g, a seventh via at the overlapping position of the detection connection line SLS and the detection line, an eighth via V8 at the overlapping position of the detection connection line SLS and the drain of the detection transistor T3, a ninth via V9 at the junction of the second gate T2g and the second capacitor electrode CstE2, a tenth via V10 at the position of the shielding layer 21 not covered by the active material layer 40, such as at the position of the spacer region 42 or the notch region 43, and a fourteenth via V14. A plurality of eleventh vias V11 are located at the position of the first auxiliary line 62, and a plurality of twelfth vias V12 are located at the position of the second auxiliary line 63.

[0098] The third insulating layer 70 within the first vias V1 and second vias V2 is etched away, exposing the surfaces at both ends of the first active layer T1a. The third vias V3 are provided at the junction of the first power connection line VDDLS and the second active layer T2a. The third insulating layer 70 within the third vias V3 is etched away, simultaneously exposing the surface of the second active layer T2a and the surface of the first power connection line VDDLS. The third insulating layer 70 within the fourth vias V4 is etched away, exposing the surface of the second active layer T2a. The third insulating layer 70 within the fifth vias V5 and sixth vias V6 is etched away, exposing the surfaces at both ends of the third active layer T3a. The seventh vias V7 are located at the position where the detection connection line SLS overlaps with the subsequently formed detection line SL. An eighth via V8 is formed within each sub-pixel driving circuit. The first insulating layer 30 and the third insulating layer 70 within the seventh vias V7 and eighth vias V8 are etched away, exposing the surface of the detection connection line SLS. The ninth vias V9 are located at the junction of the second gate T2g and the second capacitor electrode CstE2. The third insulating layer 70 within the ninth vias V9 is etched away, exposing the surface of the second gate T2g and the surface of the second capacitor electrode CstE2. The positive projection of the tenth vias V10 in the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4 on the substrate 10 is located within the positive projection of the spaced region 42 between the second capacitor electrode CstE2 and the third active layer T3a on the substrate 10. The positive projection of the tenth vias V10 in the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3 on the substrate is located within the positive projection of the notch region 43 in the middle of the second capacitor electrode CstE2 on the substrate 10. The first insulating layer 30 and the third insulating layer 70 within the tenth vias V10 are etched away, exposing the surface of the shielding layer 21.

[0099] The third insulating layer 70 within the fourteenth via V14 is etched away to expose the first insulating layer 30. The fourteenth via V14 is designed for process symmetry and is formed only in the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3. The positive projection of the fourteenth via V14 on the substrate 10 is located within the positive projection of the notch region 43 in the middle of the second capacitor electrode CstE2 on the substrate 10, and does not exist in the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4. In subsequent processes, a thirteenth via V13 for connecting to the anode is formed in each sub-pixel driving circuit. In the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4, the subsequently formed thirteenth via V13 covers the sixth via V6 that only penetrates the third insulating layer 70 to form a nested via. In the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3, the subsequently formed thirteenth via V13 is located at the notch region 43 and is close to the tenth via V10. For the process symmetry of the sub-pixel driving circuit, a fourteenth via V14 similar to the sixth via V6 in the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4 is formed at the position where the thirteenth via V13 is located in the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3, so that the subsequently formed thirteenth via V13 covers the fourteenth via V14 to form a nested via. The fourteenth via V14 is not necessary, and in some embodiments, the fourteenth via can be not provided.

[0100] The eleventh via V11 is located on the first auxiliary line 62, that is, the positive projections of multiple eleventh vias V11 on the substrate 10 fall within the positive projection of the first auxiliary line 62 on the substrate 10. Multiple eleventh vias V11 are arranged at intervals, and the third insulating layer 70 within the eleventh via V11 is etched away to expose the surface of the first auxiliary line 62.

[0101] Multiple twelfth vias V12 are located on the second auxiliary line 63, and the positive projections of multiple twelfth vias V12 on the substrate 10 fall within the positive projection of the second auxiliary line 63 on the substrate 10. Multiple twelfth vias V12 are arranged at intervals, and the third insulating layer 70 within the twelfth via V12 is etched away to expose the surface of the second auxiliary line 63. After this patterning process, multiple via patterns are formed in the display area DA, and the light-transmitting area TA includes the first insulating layer 30 and the third insulating layer 70 stacked on the substrate 10.

[0102] Figure 4 It is a schematic plan view of a single pixel after forming the pattern of the third metal layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 14 It is Figure 4 The cross-sectional structure schematic diagram along line A-A in Figure 4 andFigure 14 As shown, a pattern of the third metal layer 80 is then formed. Specifically, on the substrate on which the foregoing pattern is formed, a third metal thin film is deposited, and the third metal thin film is patterned through a patterning process to form a third metal layer pattern on the third insulating layer 70. The third metal layer 80 includes: a first power supply line VDDL, a second power supply line VSSL, a detection line SL, and four data lines DL corresponding to each pixel P, and source and drain electrodes of a switching transistor T1 formed in each sub-pixel, also referred to as a first source T1s and a first drain T1d, source and drain electrodes of a driving transistor T2, also referred to as a second source T2s and a second drain T2d, source and drain electrodes of a detection transistor T3, also referred to as a third source T3s and a third drain T3d, and a third capacitor electrode CstE3. Figure 14 is Figure 4 a cross-sectional schematic view along line A-A in. As Figure 4 and 14 shown, the first drain T1d and the first source T1s are electrically connected to the conductivized ends of the first active layer T1a on both sides of the first gate T1g through a first via V1 and a second via V2, respectively, to form the switching transistor T1. The second drain T2d and the second source T2s are electrically connected to the conductivized ends of the second active layer T2a on both sides of the second gate T2g through a third via V3 and a fourth via V4, respectively, to form the driving transistor T2. At the same time, the second drain T2d is also electrically connected to the first power supply connection line VDDLS through the third via V3. The third drain T3d and the third source T3s are electrically connected to the conductivized ends of the third active layer T3a on both sides of the third gate T3g through a fifth via V5 and a sixth via V6, respectively, to form the detection transistor T3. In addition, the third drain T3d is also electrically connected to the detection connection line SLS through an eighth via V8, and the detection line SL is electrically connected to the detection connection line SLS through a seventh via, thereby electrically connecting the detection line to the drain T3d of the detection transistor T3 of each sub-pixel driving circuit. The first source T1s is also electrically connected to the second gate T2g and the second capacitor electrode CstE2 through a ninth via V9, and the first node G in Figure 5 can be understood at the ninth via V9. The third capacitor electrode CstE3 is electrically connected to the shielding layer 21 through a tenth via V10 and fills the fourteenth via V14. The third capacitor electrode CstE3 is electrically connected to the second source T2s and the third source T3s and can be an integral structure. The second power supply line VSSL is electrically connected to the first auxiliary line 62 through a plurality of eleventh vias V11 to reduce the transmission resistance of the second power supply line VSSL. The first power supply line VDDL is electrically connected to the second auxiliary line 63 through a plurality of twelfth vias V12 to reduce the transmission resistance of the first power supply line VDDL, and transmits the VDD voltage signal to the second drain T2d of the driving transistor T2 through the second auxiliary line 63 via the first power supply connection line VDDLS. AsFigure 4 As shown, the pattern of the third metal layer 80 in the first sub-pixel driving circuit SPC1 and the pattern of the third metal layer 80 in the fourth sub-pixel driving circuit SPC4 are mirror-symmetrical with respect to the subsequently formed detection line SL, and the pattern of the third metal layer 80 in the second sub-pixel driving circuit SPC2 and the pattern of the third metal layer 80 in the third sub-pixel driving circuit SPC3 are mirror-symmetrical with respect to the subsequently formed detection line SL.

[0103] After this patterning process, the pattern of the third metal layer 80 is formed in the display area DA and not in the light-transmitting area TA. The light-transmitting area TA includes the substrate 10 and the first insulating layer 30 and the third insulating layer 70 provided on the substrate 10.

[0104] Figure 15 FIG. is a schematic plan view of a single pixel after forming the patterns of the fourth insulating layer and the planarization layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 16 is Figure 15 a schematic cross-sectional structure along A-A in FIG. Then, as Figure 15 and Figure 16 shown, the patterns of the fourth insulating layer 90 and the planarization layer 110 are formed. Specifically, on the substrate 10 having the aforementioned patterns formed thereon, a fourth insulating thin film is first deposited, and the pattern of the fourth insulating layer 90 is formed by a patterning process of the fourth insulating thin film, such as exposure, development, etching, etc. The pattern of the fourth insulating layer 90 has vias in each sub-pixel driving circuit. Then, a planarization film is coated on the substrate 10 on which the pattern of the fourth insulating layer 90 is formed, and the pattern of the planarization layer 110 is formed by a patterning process of the planarization film, such as exposure, development, etching, etc. The pattern of the planarization layer 110 is only provided in the display area DA of the pixel P and not in the light-transmitting area TA. The pattern of the planarization layer 110 also has vias in each sub-pixel driving circuit. In each sub-pixel driving circuit, the via of the planarization layer 110 is aligned with the via of the fourth insulating layer 90, and the two together form a thirteenth via V13 that penetrates the planarization layer 110 and the fourth insulating layer 90. The size of the thirteenth via V13 is significantly larger than other vias. In some embodiments, as Figure 15 、 16As shown, in the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4, the thirteenth via V13 is located at the position where the source T3s of the detection transistor T3 is located. Specifically, the thirteenth via V13 covers the sixth via V6, that is, the orthographic projection of the sixth via V6 on the substrate 10 falls within the orthographic projection of the thirteenth via V13 on the substrate 10. Thereby, the layout space can be saved, and the opening area of the pixel defining layer formed subsequently can be made as large as possible. The fourth insulating layer 90 and the planarization layer 110 in the thirteenth via V13 are etched away, exposing the surface of the source T3s of the detection transistor T3. In the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3, the thirteenth via V13 is located at the position where the opening 43 of the second capacitor electrode CstE2 is located, adjacent to the tenth via V10. In some embodiments, the thirteenth via V13 covers the fourteenth via V14, that is, the orthographic projection of the fourteenth via V14 on the substrate 10 falls within the orthographic projection of the thirteenth via V13 on the substrate 10. Thereby, a nested via structure similar to that in the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4 is formed, improving process uniformity. The fourth insulating layer 90 and the planarization layer 110 in the thirteenth via V13 are etched away, exposing the surface of the third capacitor electrode CstE3. In each sub-pixel driving circuit, the thirteenth via V13 is adjacent to the tenth via V10, and the two are aligned in the second direction Y, that is, the straight line connecting the centers of the thirteenth via V13 and the tenth via V10 is parallel to the second direction Y. In the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4, the thirteenth via V13 is closer to the second gate line GL2 than the tenth via V10. In the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3, the thirteenth via V13 is farther from the second gate line GL2 than the tenth via V10. Those skilled in the art should understand that the tenth via V10 of each sub-pixel driving circuit should be shielded by the fourth insulating layer 90 and the planarization layer 110. However, in order to clearly show the positional relationship between the tenth via V10 and the thirteenth via V13, Figure 15 the tenth via V10 of each sub-pixel driving circuit is shown in a dashed pattern. As Figure 15As shown, the patterns of the fourth insulating layer 90 and the planarization layer 110 in the first sub-pixel driving circuit SPC1 and the patterns of the fourth insulating layer 90 and the planarization layer 110 in the fourth sub-pixel driving circuit SPC4 are mirror-symmetrical with respect to the detection line SL formed subsequently, and the patterns of the fourth insulating layer 90 and the planarization layer 110 in the second sub-pixel driving circuit SPC2 and the patterns of the fourth insulating layer 90 and the planarization layer 110 in the third sub-pixel driving circuit SPC3 are mirror-symmetrical with respect to the detection line SL formed subsequently. After this patterning process, the light-transmitting region TA includes the first insulating layer 30, the third insulating layer 70, and the fourth insulating layer 90 stacked on the substrate 10.

[0105] Figure 17 FIG. is a schematic plan view of a single pixel after forming a pattern of an anode layer in the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 18 is Figure 17 a schematic cross-sectional structure view along line A-A in. Then, as Figure 17 and Figure 18 shown, a pattern of the anode layer 120 is formed. Specifically, on the substrate having the aforementioned pattern, a transparent conductive thin film is deposited, such as ITO or IZO, and the transparent conductive thin film is patterned through a patterning process to form a pattern of the anode layer 120 on the planarization layer 110. The anode layer 120 at least includes anodes 1200 of light-emitting elements D of each sub-pixel, that is, a first anode 1201 of a first light-emitting element of a first sub-pixel, a second anode 1202 of a second light-emitting element of a second sub-pixel, a third anode 1203 of a third light-emitting element of a third sub-pixel, and a fourth anode 1204 of a fourth light-emitting element of a fourth sub-pixel. The source electrodes T2s of the driving transistors T2, the source electrodes T3s of the detection transistors T3, and the third capacitor electrodes CstE3 in each sub-pixel driving circuit are integrally connected. In each sub-pixel, the anode 1200 is electrically connected to the integral structure through a thirteenth via V13 (also referred to as an anode via V13 in this article) in the corresponding sub-pixel driving circuit. Therefore, the anode 1200 of each sub-pixel is electrically connected to the source electrode T2s of the driving transistor T2 of its sub-pixel driving circuit. In Figure 17 each sub-pixel driving circuit, the thirteenth via V13 should be shielded by the anode 1200, but in order to clearly show the positional relationship between the thirteenth via V13 and the anode 1200, Figure 17 the thirteenth via V13 of each sub-pixel driving circuit is shown in a dashed pattern. In some embodiments, the four anodes 1200 are all located within the display area DA, and each anode 1200 may be quadrilateral, such as rectangular, rhombic, square, etc. In other embodiments, each anode 1200 may be other shapes, such as circular, polygonal, etc. The four anodes 1200 are arranged in a 2×2 matrix within the display area DA. In some embodiments, asFigure 17 and 18 As shown, the first anode 1201 is located in the upper left corner and is electrically connected to the source electrode T3s of the detection transistor T3 of the first sub-pixel driving circuit SPC1 through the thirteenth via V13 of the first sub-pixel driving circuit SPC1. The second anode 1202 is located in the lower left corner and is electrically connected to the third capacitor electrode CstE3 of the second sub-pixel driving circuit SPC2 through the thirteenth via V13 of the second sub-pixel driving circuit SPC2. The third anode 1203 is located in the lower right corner and is electrically connected to the third capacitor electrode CstE3 of the third sub-pixel driving circuit SPC3 through the thirteenth via V13 of the third sub-pixel driving circuit SPC3. The fourth anode 1204 is located in the upper right corner and is electrically connected to the source electrode T3s of the detection transistor T3 of the fourth sub-pixel driving circuit SPC4 through the thirteenth via V13 of the fourth sub-pixel driving circuit SPC4.

[0106] In some possible embodiments, the arrangement of the anodes 1200 in the display area DA can be adjusted according to actual needs, and the present disclosure does not make specific limitations here. The anode layer 120 is generally not provided in the light-transmitting area TA to ensure the light transmittance of the light-transmitting area TA. After this patterning process, the film layer structure of the light-transmitting area TA remains unchanged.

[0107] Figure 19 FIG. is a schematic plan view of a single pixel after forming patterns of a pixel definition layer, a light-emitting material layer, a cathode, and a packaging layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 20 is Figure 19 a schematic cross-sectional structure diagram along line A-A in FIG., and for clarity, Figure 19 the patterns of the pixel definition layer, the light-emitting material layer, the cathode, and the packaging layer are omitted, and only the opening of the pixel definition layer is shown. The pixel definition layer, the light-emitting material layer, the cathode, and the packaging layer are shown in Figure 20 FIG. As Figure 19, as shown in FIG. 20, a pixel defining layer, a light-emitting material layer, a cathode, and a packaging layer pattern are formed. Specifically, a pixel defining film layer is coated on the substrate 10 on which the aforementioned patterns are to be formed, and a pattern of the pixel defining layer 130 is formed through a mask, exposure, and development process. The pixel defining layer 130 has openings 1300 corresponding to the anodes 1200 of the respective sub-pixels, that is, a first opening 1301, a second opening 1302, a third opening 1303, and a fourth opening 1304 corresponding to the first anode 1201, the second anode 1202, the third anode 1203, and the fourth anode 1204, respectively. The first opening 1301, the second opening 1302, the third opening 1303, and the fourth opening 1304 respectively define the light-emitting regions of the first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element. The orthographic projection of each opening 1300 on the substrate 10 falls within the orthographic projection of its corresponding anode 1200 on the substrate, and each opening 1300 exposes a part of its corresponding anode 1200. Subsequently, a light-emitting material layer 140 is formed in the formed openings 1300, and the light-emitting material layer 140 is electrically connected to the corresponding anode 1200. Subsequently, a cathode thin film is deposited, and a pattern of the cathode layer 150 is formed through a patterning process. The cathode layer 150 at least includes the cathodes of the light-emitting elements D of the respective sub-pixels, and the cathode layer 150 is electrically connected to the light-emitting material layer 140 and the second power supply line VSSL, respectively. In some embodiments, as Figure 19 and 20 shown, the cathodes of the light-emitting elements D of the respective sub-pixels are of an integral structure. In some embodiments, the cathodes of the light-emitting elements D of the respective sub-pixels of multiple pixels P are integrally formed, being of an integral structure, covering the light-transmitting region TA and the display region DA of multiple pixels P. Subsequently, a packaging layer 160 is formed on the cathode layer 150. The packaging layer 160 is, for example, a stacked structure including an inorganic material / an organic material / an inorganic material. In some embodiments, the cathode layer 150 can be electrically connected to the second power supply line VSSL in various ways, such as laser drilling. After this process, in some embodiments, the light-transmitting region TA may include the substrate 10, the first insulating layer 30, the third insulating layer 70, the fourth insulating layer 90, the cathode layer 150, and the packaging layer 160 provided on the substrate 10. Those skilled in the art can understand that the first insulating layer 30, the third insulating layer 70, the fourth insulating layer 90, the cathode layer 150, and the packaging layer 160 in the light-transmitting region TA are not essential. In some embodiments, in the formation processes of the above-mentioned layers, the above-mentioned layers in the light-transmitting region TA can be removed according to actual needs.

[0108] Thus far, the pixel structure of the transparent display panel has been basically completed. As Figures 4 - 20As shown, for a pixel P, in the display area DA of the pixel P, the first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 are arranged in sequence along the first direction X parallel to the substrate 10, and all extend along the second direction Y perpendicular to the first direction X. In each of the first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4, the detection transistor T3, the storage capacitor Cst, and the switching transistor T1 are arranged in sequence along the second direction Y, and the detection transistor T3 and the switching transistor T1 are respectively located on both sides of the storage capacitor Cst. The first gate line GL1 is located on the side of the switching transistor T1 away from the storage capacitor Cst, and the second gate line GL2 is located on the side of the detection transistor T3 away from the storage capacitor Cst. The first anode 1201, the second anode 1202, the third anode 1203, and the fourth anode 1204 are arranged in a 2×2 matrix in the display area DA. Specifically, the first anode 1201 is located at the upper left position of the 2×2 matrix arrangement. The orthographic projection of the first anode 1201 on the substrate 10 covers at least the orthographic projection of the detection transistor T3 in the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2 on the substrate 10, and covers the orthographic projection of the part of the storage capacitor Cst in the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2 close to the detection transistor T3 on the substrate 10, that is, covers the orthographic projection of the first part Cst1 of the storage capacitor Cst in the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2 on the substrate 10. The second anode 1202 is located at the lower left position of the 2×2 matrix arrangement. The orthographic projection of the second anode 1202 on the substrate 10 covers at least the orthographic projection of the switching transistor T1 in the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2 on the substrate 10, and covers the orthographic projection of the part of the storage capacitor Cst in the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2 close to the switching transistor T1 on the substrate 10, that is, covers the orthographic projection of the second part Cst2 of the storage capacitor Cst in the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2 on the substrate 10.The third anode 1203 is located at the lower right position of the 2×2 matrix arrangement. The positive projection of the second anode 1202 on the substrate 10 covers at least the positive projection of the switching transistor T1 in the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4 on the substrate 10, and covers the positive projection of the part of the storage capacitor Cst in the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4 close to the switching transistor T1 on the substrate 10, that is, covers the positive projection of the second part Cst2 of the storage capacitor Cst in the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4 on the substrate 10. The fourth anode 1204 is located at the upper right position of the 2×2 matrix arrangement. The positive projection of the fourth anode 1204 on the substrate 10 covers at least the positive projection of the detection transistor T3 in the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4 on the substrate 10, and covers the positive projection of the part of the storage capacitor Cst in the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4 close to the detection transistor T3 on the substrate 10, that is, covers the positive projection of the first part Cst1 of the storage capacitor Cst in the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4 on the substrate 10.

[0109] In the comparative example, as Figure 21 shown, the anodes 1200' of the light-emitting elements of the four sub-pixels basically only cover their corresponding sub-pixel driving circuits. The anodes 1200' of each light-emitting element are basically long and narrow strips extending along the second direction, resulting in each light-emitting element also being a long and narrow strip extending along the second direction Y, and being arranged in sequence along the first direction X in the display area DA. When the transparent display panel has a high resolution, the width of a single display area DA along the first direction X is relatively narrow, for example, thus the width of the light-emitting area of each light-emitting element along the first direction is very small, increasing the manufacturing process difficulty and easily causing display color bleeding of each light-emitting element.

[0110] Compared with the comparative example, in some embodiments of the present disclosure, the first anode 1201, the second anode 1202, the third anode 1203, and the fourth anode 1204 all cover the width of two sub-pixel driving circuits on the substrate in the first direction X. The widths of the first to fourth light-emitting elements where the first anode 1201, the second anode 1202, the third anode 1203, and the fourth anode 1204 are located are relatively wide in the first direction X, which is easy to manufacture and can reduce or avoid the problem of display color bleeding of each light-emitting element.

[0111] Those skilled in the art can understand that Figure 17The shapes of the first anode 1201, the second anode 1202, the third anode 1203, and the fourth anode 1204 shown in the figure and their positional relationships with wirings such as the first gate line GL1, the second gate line GL2, the data line DL, the detection line SL, the first power supply line VDDL, and the second power supply line VSSL in the display area are only illustrative. Those skilled in the art can design the sizes, shapes, etc. of the anodes 1200 according to actual needs. In some embodiments, each of the first anode 1201, the second anode 1202, the third anode 1203, and the fourth anode 1204 may cover at least a part of the above-mentioned traces adjacent thereto, as long as there is no overlap or contact between any two of the first anode 1201, the second anode 1202, the third anode 1203, and the fourth anode 1204.

[0112] In some embodiments, as Figures 4 - 20 shown, in each sub-pixel driving circuit, the driving transistor T2 includes a source T2s, a gate T2g, and a drain T2d that are sequentially away from the storage capacitor Cst in the second direction Y. The detection transistor T3 includes a source T3s, a gate T3g, and a drain T3d that are sequentially away from the storage capacitor Cst in the second direction. The storage capacitor Cst includes a first capacitor electrode CstE1, a second capacitor electrode CstE2, and a third capacitor electrode CstE3 that are sequentially stacked on the substrate 10. The positive projection of the first capacitor electrode CstE1 on the substrate 10 overlaps with the positive projection of the second capacitor electrode CstE2 on the substrate 10, and the two form a first capacitor. The positive projection of the third capacitor electrode CstE3 on the substrate 10 overlaps with the positive projection of the second capacitor electrode CstE2 on the substrate 10, and the two form a second capacitor. The first capacitor electrode CstE1 and the third capacitor electrode CstE3 are electrically connected through the tenth via V10 (also referred to as a capacitor via in this article). The storage capacitor Cst can be considered as a parallel connection of the first capacitor and the second capacitor. Compared with a storage capacitor having only two capacitor electrodes, the capacity of the storage capacitor can be increased.

[0113] In each sub-pixel driving circuit, the source T2s of the driving transistor T2, the third capacitor electrode CstE3, and the source T3s of the detection transistor T3 are connected as an integrated structure, and they are all located in the third metal layer 80 (also referred to as the source-drain metal layer 80 in this article). The anode 1200 is electrically connected to the above structure through the thirteenth via V13 (also referred to as the anode via V13 in this article) that penetrates the fourth insulating layer 90 and the planarization layer 110 to realize the driving of the corresponding light-emitting element by the sub-pixel driving circuit. The anode via V13 in each sub-pixel driving circuit is covered by the corresponding anode 1200. Due to the long-strip arrangement of the four sub-pixel driving circuits and the 2×2 matrix arrangement of the four anodes 1200 (as Figure 17As shown, the anode via V13 of the first sub-pixel driving circuit SPC1 needs to be located in the portion of the first sub-pixel driving circuit SPC1 that is close to the second gate line GL2 and covered by the first anode 1201. The anode via V13 of the second sub-pixel driving circuit SPC2 needs to be located in the portion of the second sub-pixel driving circuit SPC2 that is close to the first gate line GL1 and covered by the second anode 1202. The anode via V13 of the third sub-pixel driving circuit SPC3 needs to be located in the portion of the third sub-pixel driving circuit SPC3 that is close to the first gate line GL1 and covered by the third anode 1203. The anode via V13 of the fourth sub-pixel driving circuit SPC4 needs to be located in the portion of the fourth sub-pixel driving circuit SPC4 that is close to the second gate line GL2 and covered by the fourth anode 1204.

[0114] Specifically, as Figures 4 - 20As shown, in the first sub-pixel driving circuit SPC1, the positive projection of the anode via V13 (hereinafter also referred to as the first anode via V13 in the first sub-pixel driving circuit SPC1, denoted as V131) on the substrate 10 falls within the positive projection of the source electrode T3s of the detection transistor T3 on the substrate 10. The first anode 1201 is electrically connected to the source electrode T3s of the detection transistor T3 through the first anode via V131. The source electrode T3s of the detection transistor T3 is electrically connected to the active layer T3a through the sixth via V6 (also referred to as the source via V6 in this article). The relatively large first anode via V131 is stacked above the source via V6 to form a nested via, and the positive projection of the source via V6 on the substrate 10 falls within the positive projection of the first anode via V131 on the substrate 10. In the second sub-pixel driving circuit SPC2, the positive projection of the anode via V13 (hereinafter also referred to as the second anode via V13 in the second sub-pixel driving circuit SPC2, denoted as V132) on the substrate 10 falls within the positive projection of the third capacitor electrode CstE3 of the storage capacitor Cst on the substrate 10. The second anode 1202 is electrically connected to the third capacitor electrode CstE3 of the storage capacitor Cst through the second anode via V132. In the third sub-pixel driving circuit SPC3, the positive projection of the anode via V13 (hereinafter also referred to as the third anode via V13 in the third sub-pixel driving circuit SPC3, denoted as V133) on the substrate 10 falls within the positive projection of the third capacitor electrode CstE3 of the storage capacitor Cst on the substrate 10. The third anode 1203 is electrically connected to the third capacitor electrode CstE3 of the storage capacitor Cst through the third anode via V133. In the fourth sub-pixel driving circuit SPC4, the positive projection of the anode via V13 (hereinafter also referred to as the fourth anode via V13 in the fourth sub-pixel driving circuit SPC4, denoted as V134) on the substrate 10 falls within the positive projection of the source electrode T3s of the detection transistor T3 on the substrate 10. The fourth anode 1204 is electrically connected to the source electrode T3s of the detection transistor T3 through the fourth anode via V134. The source electrode T3s of the detection transistor T3 is electrically connected to the active layer T3a through the sixth via V6 (also referred to as the source via V6 in this article). The relatively large fourth anode via V134 is stacked above the source via V6 to form a nested via, and the positive projection of the source via V6 on the substrate 10 falls within the positive projection of the fourth anode via V134 on the substrate 10.

[0115] In some embodiments, such as Figures 4 - 20As shown, the shapes and sizes of the first anode via V131, the second anode via V132, the third anode via V133, and the fourth anode via V134 are substantially the same. The straight connection line between the center of the orthographic projection of the first anode via V131 on the substrate 10 and the center of the orthographic projection of the fourth anode via V134 on the substrate extends along the first direction X. That is to say, the distance from the first anode via V131 to the second gate line GL2 is substantially equal to the distance from the fourth anode via V134 to the second gate line GL2. The straight connection line between the center of the orthographic projection of the second anode via V132 on the substrate 10 and the center of the orthographic projection of the third anode via V133 on the substrate extends along the first direction X. That is to say, the distance from the second anode via V132 to the first gate line GL1 is substantially equal to the distance from the third anode via V133 to the first gate line GL1, thereby ensuring process uniformity.

[0116] In some embodiments, the anode via V13 penetrates the fourth insulating layer 90 and the thick planarization layer 110. Thus, a large step is generated in the anode via V13, and the flatness of the upper surface of the planarization layer 110 near the anode via V13 is poor. The capacitor via V10 penetrates the first insulating layer 30 and the third insulating layer 70, and it has a relatively large depth. Compared with the vias that only penetrate a single insulating layer, a relatively large step will be generated. Although the capacitor via V10 is covered by the planarization layer 110, the flatness of the planarization layer 110 at the capacitor via V10 is also not good. Subsequently, when forming the light-emitting material layer 140 of each light-emitting element, it needs to be formed on the part of the planarization layer 110 with good flatness to ensure good light-emitting uniformity of the light-emitting element. Thus, when forming the opening 1300 of the subsequent pixel defining layer 130, it is necessary to avoid the anode via V13 and the capacitor via V10, as Figure 19 shown. Thus, in order to facilitate the design of the opening 1300 and maximize the opening 1300 as much as possible, in each sub-pixel driving circuit, both the anode via V13 and the capacitor via V10 are adjacent. In each narrow sub-pixel driving circuit, both the anode via V13 and the capacitor via V10 are adjacent. For example, they can be arranged in sequence along the extending direction of the sub-pixel driving circuit, i.e., the second direction Y. Specifically, in each sub-pixel driving circuit, the anode via V13 and the capacitor via V10 are adjacent, and the two are aligned in the second direction Y, that is, the straight connection line between the center of the anode via V13 and the center of the capacitor via V10 is parallel to the second direction Y.

[0117] Figure 19 shows the positions of the openings 1300 of the pixel defining layer 130, and the positions of the anode via V13 and the capacitor via V10 are marked with a dotted pattern. As Figure 19As shown, the anode via V13 and the capacitor via V10 are both covered by the pixel defining layer 130 and the anode layer 120. The first opening 1301 defines the light-emitting area of the first light-emitting element of the first sub-pixel. The orthographic projection of the first opening 1301 on the substrate 10 falls within the orthographic projection of the first anode 1201 on the substrate 10, and the first opening 1301 avoids the anode via V13 and the capacitor via V10 in the first sub-pixel driving circuit SPC1, that is, the orthographic projection of the first opening 1301 on the substrate 10 does not overlap with the orthographic projections of the anode via V13 and the capacitor via V10 in the first sub-pixel driving circuit SPC1 on the substrate 10. The second opening 1302 defines the light-emitting area of the second light-emitting element of the second sub-pixel. The orthographic projection of the second opening 1302 on the substrate 10 falls within the orthographic projection of the second anode 1202 on the substrate 10, and the second opening 1301 avoids the anode via V13 and the capacitor via V10 in the second sub-pixel driving circuit SPC2, that is, the orthographic projection of the second opening 1302 on the substrate 10 does not overlap with the orthographic projections of the anode via V13 and the capacitor via V10 in the second sub-pixel driving circuit SPC2 on the substrate 10. The third opening 1303 defines the light-emitting area of the third light-emitting element of the third sub-pixel. The orthographic projection of the third opening 1303 on the substrate 10 falls within the orthographic projection of the third anode 1203 on the substrate 10, and the third opening 1303 avoids the anode via V13 and the capacitor via V10 in the third sub-pixel driving circuit SPC3, that is, the orthographic projection of the third opening 1303 on the substrate 10 does not overlap with the orthographic projections of the anode via V13 and the capacitor via V10 in the third sub-pixel driving circuit SPC3 on the substrate 10. The fourth opening 1304 defines the light-emitting area of the fourth light-emitting element of the fourth sub-pixel. The orthographic projection of the fourth opening 1304 on the substrate 10 falls within the orthographic projection of the fourth anode 1204 on the substrate 10, and the fourth opening 1304 avoids the anode via V13 and the capacitor via V10 in the fourth sub-pixel driving circuit SPC4, that is, the orthographic projection of the fourth opening 1304 on the substrate 10 does not overlap with the orthographic projections of the anode via V13 and the capacitor via V10 in the fourth sub-pixel driving circuit SPC4 on the substrate 10.

[0118] In the manufacturing process of the transparent display panel, the anode via V13 usually has a relatively large area and a relatively deep depth. Therefore, in the layout design, the opening 1300 cannot be too close to the anode via V13, otherwise it is easy to cause the collapse of the pixel defining layer between the opening 1300 and the via V13. Therefore, a relatively large distance should be maintained between the opening 1300 and the via V13, for example, greater than a predetermined distance. In some embodiments, such as Figure 19As shown, in each sub-pixel driving circuit, the anode via V13 and the capacitor via V10 are adjacent and aligned in the second direction Y, and the line connecting the center of the anode via V13 and the capacitor via V10 is parallel to the second direction Y. Moreover, in the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4, the anode via V13 is closer to the second gate line GL2 than the tenth via V10, while in the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3, the anode via V13 is farther from the second gate line GL2 than the tenth via V10. Based on the above design, while ensuring that the distance between each of the first opening 1301 and the second opening 1302 and the anode via V13 in the second pixel driving circuit SPC2 is greater than a predetermined distance, the first opening 1301 can be as close as possible to the second opening 1302, maximizing the area of the first opening 1301. Similarly, while ensuring that the distance between each of the third opening 1303 and the fourth opening 1304 and the anode via V13 in the second pixel driving circuit SPC4 is greater than a predetermined distance, the fourth opening 1304 can be as close as possible to the third opening 1303, maximizing the area of the fourth opening 1304.

[0119] In the above embodiment, as Figure 19As shown, the first anode 1201, the second anode 1202, the third anode 1203, and the fourth anode 1204 are arranged in a 2×2 matrix in the display area DA. The first anode 1201 substantially covers the upper half of the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2. The second anode 1202 substantially covers the lower half of the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2. The third anode 1203 substantially covers the lower half of the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4. The fourth anode 1204 substantially covers the upper half of the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4. The first anode via V131 is located in the upper half of the first sub-pixel driving circuit SPC1. The second anode via V132 is located in the lower half of the second sub-pixel driving circuit SPC2. The third anode via V133 is located in the lower half of the third sub-pixel driving circuit SPC3. The fourth anode via V134 is located in the upper half of the fourth sub-pixel driving circuit SPC4. In the transparent display panel with this design, four light-emitting elements are easy to manufacture, and the problem of display color bleeding of each light-emitting element can be reduced or avoided. Optionally, the first anode via V131 and the fourth anode via V134 are aligned in the first direction X, that is, the straight line connecting the centers of the first anode via 131 and the fourth anode via V134 extends along the first direction X. The second anode via V132 and the third anode via V133 are aligned in the first direction X, that is, the straight line connecting the centers of the second anode via 132 and the third anode via V133 extends along the first direction X, thereby improving the uniformity of the manufacturing process of the transparent display panel.

[0120] In some embodiments, such as Figure 22As shown, the first anode 1201, the second anode 1202, the third anode 1203, and the fourth anode 1204 are arranged in a 2×2 matrix in the display area DA. The first anode 1201 substantially covers the lower half of the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2. The second anode 1202 substantially covers the upper half of the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2. The third anode 1203 substantially covers the lower half of the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4. The fourth anode 1204 substantially covers the upper half of the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4. The first anode via V131 is located in the lower half of the first sub-pixel driving circuit SPC1. The second anode via V132 is located in the upper half of the second sub-pixel driving circuit SPC2. The third anode via V133 is located in the lower half of the third sub-pixel driving circuit SPC3. The fourth anode via V134 is located in the upper half of the fourth sub-pixel driving circuit SPC4. In the transparent display panel with this design, four light-emitting elements are easy to manufacture, and the problem of color bleeding between light-emitting elements can be reduced or avoided. Optionally, the first anode via V131 and the third anode via V133 are aligned in the first direction X, that is, the straight line connecting the centers of the first anode via 131 and the third anode via V133 extends along the first direction X. The second anode via V132 and the fourth anode via V134 are aligned in the first direction X, that is, the straight line connecting the centers of the second anode via 132 and the fourth anode via V134 extends along the first direction X. Thereby, the uniformity of the manufacturing process of the transparent display panel can be improved.

[0121] In some embodiments, such as Figure 23As shown, the first anode 1201, the second anode 1202, the third anode 1203, and the fourth anode 1204 are arranged in a 2×2 matrix in the display area DA. The first anode 1201 substantially covers the lower half of the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2. The second anode 1202 substantially covers the upper half of the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2. The third anode 1203 substantially covers the upper half of the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4. The fourth anode 1204 substantially covers the lower half of the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4. The first anode via V131 is located in the lower half of the first sub-pixel driving circuit SPC1. The second anode via V132 is located in the upper half of the second sub-pixel driving circuit SPC2. The third anode via V133 is located in the upper half of the third sub-pixel driving circuit SPC3. The fourth anode via V134 is located in the lower half of the fourth sub-pixel driving circuit SPC4. In the transparent display panel with this design, four light-emitting elements are easy to manufacture, and the problem of color bleeding in the display of each light-emitting element can be reduced or avoided. Optionally, the first anode via V131 and the fourth anode via V134 are aligned in the first direction X, that is, the straight line connecting the centers of the first anode via 131 and the fourth anode via V134 extends along the first direction X. The second anode via V132 and the third anode via V133 are aligned in the first direction X, that is, the straight line connecting the centers of the second anode via 132 and the third anode via V133 extends along the first direction X, thereby improving the uniformity of the manufacturing process of the transparent display panel.

[0122] In some embodiments, such as Figure 24As shown, the first anode 1201, the second anode 1202, the third anode 1203, and the fourth anode 1204 are arranged in a 2×2 matrix in the display area DA. The first anode 1201 substantially covers the upper half of the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2. The second anode 1202 substantially covers the lower half of the first sub-pixel driving circuit SPC1 and the second sub-pixel driving circuit SPC2. The third anode 1203 substantially covers the upper half of the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4. The fourth anode 1204 substantially covers the lower half of the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4. The first anode via V131 is located in the upper half of the first sub-pixel driving circuit SPC1. The second anode via V132 is located in the lower half of the second sub-pixel driving circuit SPC2. The third anode via V133 is located in the upper half of the third sub-pixel driving circuit SPC3. The fourth anode via V134 is located in the lower half of the fourth sub-pixel driving circuit SPC4. In the transparent display panel with this design, four light-emitting elements are easy to manufacture, and the problem of display crosstalk of each light-emitting element can be reduced or avoided. Optionally, the first anode via V131 and the third anode via V133 are aligned in the first direction X, that is, the straight line connecting the centers of the first anode via 131 and the third anode via V133 extends along the first direction X. The second anode via V132 and the fourth anode via V134 are aligned in the first direction X, that is, the straight line connecting the centers of the second anode via 132 and the fourth anode via V134 extends along the first direction X. Thus, the uniformity of the manufacturing process of the transparent display panel can be improved.

[0123] Those skilled in the art can understand that in the above embodiment, when the anode via V13 is located in the upper half of its corresponding sub-pixel driving circuit, the sub-pixel driving circuit can adopt Figures 4 - 20 the structure of the first sub-pixel driving circuit SPC1 or the first sub-pixel driving circuit SPC4 in Figures 4 - 20 When the anode via V13 is located in the lower half of its corresponding sub-pixel driving circuit, the sub-pixel driving circuit can adopt

[0124] Some embodiments of the present disclosure provide an electronic device, specifically a transparent electronic device, including the transparent display panel described in any of the above embodiments. The transparent electronic device can be used for products or components with perspective and display functions such as perspective display windows and vehicle windows.

[0125] The above description is only a preferred embodiment of the present disclosure and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present disclosure.

Claims

1. A display panel, comprising: a substrate substrate; and pixels disposed on the substrate substrate, wherein the pixel includes a first sub-pixel and a second sub-pixel, the first sub-pixel includes a first sub-pixel driving circuit and a first light-emitting element driven by the first sub-pixel driving circuit, the second sub-pixel includes a second sub-pixel driving circuit and a second light-emitting element driven by the second sub-pixel driving circuit, the first sub-pixel driving circuit and the second sub-pixel driving circuit are sequentially arranged in a first direction parallel to the substrate substrate and both extend in a second direction, the second direction is parallel to the substrate substrate and intersects the first direction, wherein the first light-emitting element includes a first anode electrically connected to the first sub-pixel driving circuit, the second light-emitting element includes a second anode electrically connected to the second sub-pixel driving circuit, and the orthographic projection of each of the first anode and the second anode on the substrate substrate partially covers the orthographic projection of the first sub-pixel driving circuit on the substrate substrate and the orthographic projection of the second sub-pixel driving circuit on the substrate substrate, and the orthographic projection of the first anode on the substrate substrate does not overlap with the orthographic projection of the second anode on the substrate substrate; wherein the first sub-pixel driving circuit and the second sub-pixel driving circuit both include a detection transistor, a storage capacitor, and a switching transistor, and in the second direction, the detection transistor and the switching transistor are respectively located on both sides of the storage capacitor; wherein the orthographic projection of one of the first anode and the second anode on the substrate substrate covers the orthographic projection of a first portion of the storage capacitor in the first sub-pixel driving circuit on the substrate substrate and covers the orthographic projection of a first portion of the storage capacitor in the second sub-pixel driving circuit on the substrate substrate, and the orthographic projection of the other of the first anode and the second anode on the substrate substrate covers the orthographic projection of a second portion of the storage capacitor in the first sub-pixel driving circuit on the substrate substrate and covers the orthographic projection of a second portion of the storage capacitor in the second sub-pixel driving circuit on the substrate substrate. In each of the first sub-pixel driving circuit and the second sub-pixel driving circuit, the first portion of the storage capacitor is closer to the detection transistor than the second portion of the storage capacitor.

2. The display panel according to claim 1, wherein, The orthographic projection of one of the first anode and the second anode on the substrate substrate at least partially covers the orthographic projection of the detection transistor in the first sub-pixel driving circuit on the substrate substrate and at least partially covers the orthographic projection of the detection transistor in the second sub-pixel driving circuit on the substrate substrate, and the orthographic projection of the other of the first anode and the second anode on the substrate substrate at least partially covers the orthographic projection of the switching transistor in the first sub-pixel driving circuit on the substrate substrate and at least partially covers the orthographic projection of the switching transistor in the second sub-pixel driving circuit on the substrate substrate.

3. The display panel according to claim 2, wherein, The positive projection of one of the first anode and the second anode on the substrate completely covers the positive projection of the detection transistor in the first sub-pixel driving circuit on the substrate and completely covers the positive projection of the detection transistor in the second sub-pixel driving circuit on the substrate, and the positive projection of the other of the first anode and the second anode on the substrate completely covers the positive projection of the switching transistor in the first sub-pixel driving circuit on the substrate and completely covers the positive projection of the switching transistor in the second sub-pixel driving circuit on the substrate.

4. The display panel according to any one of claims 2-3, wherein, The pixel further includes a third sub-pixel and a fourth sub-pixel. The third sub-pixel includes a third sub-pixel driving circuit and a third light-emitting element driven by the third sub-pixel driving circuit. The fourth sub-pixel includes a fourth sub-pixel driving circuit and a fourth light-emitting element driven by the fourth sub-pixel driving circuit. The first sub-pixel driving circuit, the second sub-pixel driving circuit, the third sub-pixel driving circuit, and the fourth sub-pixel driving circuit are sequentially arranged in a first direction parallel to the substrate and all extend in the second direction; Wherein, the third light-emitting element includes a third anode electrically connected to the third sub-pixel driving circuit, the fourth light-emitting element includes a fourth anode electrically connected to the fourth sub-pixel driving circuit, and the positive projection of each of the third anode and the fourth anode on the substrate partially covers the positive projection of the third sub-pixel driving circuit on the substrate and the positive projection of the fourth sub-pixel driving circuit on the substrate, and any two of the positive projections of the first anode, the second anode, the third anode, and the fourth anode on the substrate do not overlap.

5. The display panel according to claim 4, wherein, Both the third sub-pixel driving circuit and the fourth sub-pixel driving circuit include a detection transistor, a storage capacitor, and a switching transistor. In the second direction, in each sub-pixel driving circuit of the third sub-pixel driving circuit and the fourth sub-pixel driving circuit, the detection transistor and the switching transistor are respectively located on both sides of the storage capacitor; Wherein, the positive projection of one of the third anode and the fourth anode on the substrate at least partially covers the positive projection of the detection transistor in the third sub-pixel driving circuit on the substrate and at least partially covers the positive projection of the detection transistor in the fourth sub-pixel driving circuit on the substrate, and the positive projection of the other of the third anode and the fourth anode on the substrate at least partially covers the positive projection of the switching transistor in the third sub-pixel driving circuit on the substrate and at least partially covers the positive projection of the switching transistor in the fourth sub-pixel driving circuit on the substrate.

6. The display panel according to claim 5, wherein, The orthographic projection of one of the third anode and the fourth anode on the substrate covers the orthographic projection of the first part of the storage capacitor in the third sub-pixel driving circuit on the substrate and covers the orthographic projection of the first part of the storage capacitor in the fourth sub-pixel driving circuit on the substrate. The orthographic projection of the other of the third anode and the fourth anode on the substrate covers the orthographic projection of the second part of the storage capacitor in the third sub-pixel driving circuit on the substrate and covers the orthographic projection of the second part of the storage capacitor in the fourth sub-pixel driving circuit on the substrate. In each of the third sub-pixel driving circuit and the fourth sub-pixel driving circuit, the first part of the storage capacitor is closer to the detection transistor than the second part of the storage capacitor.

7. The display panel according to claim 5 or 6, wherein, The orthographic projection of one of the third anode and the fourth anode on the substrate completely covers the orthographic projection of the detection transistor in the third sub-pixel driving circuit on the substrate and completely covers the orthographic projection of the detection transistor in the fourth sub-pixel driving circuit on the substrate. The orthographic projection of the other of the third anode and the fourth anode on the substrate completely covers the orthographic projection of the switching transistor in the third sub-pixel driving circuit on the substrate and completely covers the orthographic projection of the switching transistor in the fourth sub-pixel driving circuit on the substrate.

8. The display panel according to claim 5, wherein, Each of the first sub-pixel driving circuit, the second sub-pixel driving circuit, the third sub-pixel driving circuit, and the fourth sub-pixel driving circuit further includes: A driving transistor, located on a side of the storage capacitor away from the detection transistor and between the storage capacitor and the switching transistor. The driving transistor includes a source electrode, a gate electrode, and a drain electrode arranged successively away from the storage capacitor in the second direction. The detection transistor includes a source electrode, a gate electrode, and a drain electrode arranged successively away from the storage capacitor in the second direction. The storage capacitor includes a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode stacked successively on the substrate. The source electrode of the driving transistor, the third capacitor electrode, and the source electrode of the detection transistor are arranged on the same layer and connected to form an integral structure.

9. The display panel according to claim 8, further comprising: A source-drain metal layer, including the integral structure in each sub-pixel driving circuit; An anode layer, located on a side of the source-drain metal layer away from the substrate, including a first anode, a second anode, a third anode, and a fourth anode; A planarization layer, provided on a side of the source-drain metal layer away from the substrate and on a side of the anode layer facing the substrate; Wherein, the planarization layer is provided with: A first anode via, through which the first anode is electrically connected to the integral structure of the first sub-pixel driving circuit; A second anode via, through which the second anode is electrically connected to the integral structure of the second sub-pixel driving circuit; The third anode via, the third anode is electrically connected to the integrated structure of the third sub-pixel driving circuit through the third anode via; The fourth anode via, the fourth anode is electrically connected to the integrated structure of the fourth sub-pixel driving circuit through the fourth anode via.

10. The display panel according to claim 9, wherein, The positive projection of one of the first anode via and the second anode via on the substrate falls within the positive projection of the source electrode of the detection transistor in the sub-pixel driving circuit electrically connected to the one anode via on the substrate; The positive projection of the other anode via of the first anode via and the second anode via on the substrate falls within the positive projection of the third capacitive electrode of the storage capacitor in the sub-pixel driving circuit electrically connected to the other anode via on the substrate, and is located in the second direction between the positive projection of the source electrode of the detection transistor in the sub-pixel driving circuit electrically connected to the other anode via on the substrate and the positive projection of the source electrode of the driving transistor in the sub-pixel driving circuit electrically connected to the other anode via on the substrate; The positive projection of one of the third anode via and the fourth anode via on the substrate falls within the positive projection of the source electrode of the detection transistor in the sub-pixel driving circuit electrically connected to the one anode via on the substrate; The positive projection of the other anode via of the third anode via and the fourth anode via on the substrate falls within the positive projection of the third capacitive electrode of the storage capacitor in the sub-pixel driving circuit electrically connected to the other anode via on the substrate, and is located in the second direction between the positive projection of the source electrode of the detection transistor in the sub-pixel driving circuit electrically connected to the other anode via on the substrate and the positive projection of the source electrode of the driving transistor in the sub-pixel driving circuit electrically connected to the other anode via on the substrate.

11. The display panel according to claim 9 or 10, wherein, The straight connection line between the center of the positive projection of the first anode via on the substrate and the center of the positive projection of one of the third anode via and the fourth anode via on the substrate extends along the first direction, and the straight connection line between the center of the positive projection of the second anode via on the substrate and the center of the positive projection of the other of the third anode via and the fourth anode via on the substrate extends along the first direction.

12. The display panel according to claim 9, wherein, The positive projection of the first anode via on the substrate falls within the positive projection of the source electrode of the detection transistor in the first sub-pixel driving circuit on the substrate; The positive projection of the second anode via on the substrate falls within the positive projection of the third capacitive electrode of the storage capacitor in the second sub-pixel driving circuit on the substrate, and is located between the positive projection of the source electrode of the detection transistor in the second sub-pixel driving circuit on the substrate and the positive projection of the source electrode of the driving transistor in the second sub-pixel driving circuit on the substrate in the second direction; The positive projection of the third anode via on the substrate falls within the positive projection of the third capacitive electrode of the storage capacitor in the third sub-pixel driving circuit on the substrate, and is located between the positive projection of the source electrode of the detection transistor in the third sub-pixel driving circuit on the substrate and the positive projection of the source electrode of the driving transistor in the third sub-pixel driving circuit on the substrate in the second direction; The positive projection of the fourth anode via on the substrate falls within the positive projection of the source electrode of the detection transistor in the fourth sub-pixel driving circuit on the substrate.

13. The display panel according to claim 12, wherein, Each sub-pixel driving circuit further includes a capacitive via, and the third capacitive electrode of the storage capacitor is electrically connected to the first capacitive electrode through the capacitive via.

14. The display panel according to claim 13, wherein, In the first sub-pixel driving circuit, the capacitive via is located on a side of the first anode via close to the storage capacitor and between the first anode via and the storage capacitor. A straight line connecting the center of the positive projection of the capacitive via on the substrate and the center of the positive projection of the first anode via on the substrate extends along the second direction. The positive projection of the capacitive via on the substrate and the positive projection of the first anode via on the substrate both fall within the positive projection of the first anode on the substrate, In the second sub-pixel driving circuit, the capacitive via is located on a side of the second anode via close to the detection transistor. A straight line connecting the center of the positive projection of the capacitive via on the substrate and the center of the positive projection of the second anode via on the substrate extends along the second direction. The positive projection of the capacitive via on the substrate and the positive projection of the second anode via on the substrate both fall within the positive projection of the second anode on the substrate, In the third sub-pixel driving circuit, the capacitive via is located on a side of the third anode via close to the detection transistor. A straight line connecting the center of the positive projection of the capacitive via on the substrate and the center of the positive projection of the third anode via on the substrate extends along the second direction. The positive projection of the capacitive via on the substrate and the positive projection of the third anode via on the substrate both fall within the positive projection of the third anode on the substrate, In the fourth sub-pixel driving circuit, the capacitor via hole is located on a side of the fourth anode via hole close to the storage capacitor and between the fourth anode via hole and the storage capacitor. A straight line connecting the center of the positive projection of the capacitor via hole on the substrate with the center of the positive projection of the fourth anode via hole on the substrate extends along the second direction. The positive projection of the capacitor via hole on the substrate and the positive projection of the fourth anode via hole on the substrate both fall within the positive projection of the fourth anode on the substrate.

15. The display panel according to claim 12, wherein, Each sub-pixel driving circuit further includes a source via hole. The detection transistor of each sub-pixel driving circuit further includes an active layer. The source of the detection transistor is connected to the active layer through the source via hole. Among them, the positive projection of the source via hole in the first sub-pixel driving circuit on the substrate falls within the positive projection of the first anode via hole on the substrate. The positive projection of the source via hole in the fourth sub-pixel driving circuit on the substrate falls within the positive projection of the fourth anode via hole on the substrate.

16. The display panel according to claim 13 or 14, further comprising: A pixel defining layer having: A first opening for accommodating the light-emitting material layer of the first light-emitting element; A second opening for accommodating the light-emitting material layer of the second light-emitting element; A third opening for accommodating the light-emitting material layer of the third light-emitting element; And A fourth opening for accommodating the light-emitting material layer of the fourth light-emitting element, wherein the positive projection of the first opening on the substrate falls within the positive projection of the first anode on the substrate, the positive projection of the second opening on the substrate falls within the positive projection of the second anode on the substrate, the positive projection of the third opening on the substrate falls within the positive projection of the third anode on the substrate, and the positive projection of the fourth opening on the substrate falls within the positive projection of the fourth anode on the substrate.

17. The display panel according to claim 16, wherein The positive projection of the first opening on the substrate does not overlap with the positive projection of the first anode via hole on the substrate, and the positive projection of the first opening on the substrate does not overlap with the positive projection of the capacitor via hole of the first sub-pixel driving circuit on the substrate; The positive projection of the second opening on the substrate does not overlap with the positive projection of the second anode via hole on the substrate, and the positive projection of the second opening on the substrate does not overlap with the positive projection of the capacitor via hole of the second sub-pixel driving circuit on the substrate; The positive projection of the third opening on the substrate does not overlap with the positive projection of the third anode via hole on the substrate, and the positive projection of the third opening on the substrate does not overlap with the positive projection of the capacitor via hole of the third sub-pixel driving circuit on the substrate; The orthographic projection of the fourth opening on the substrate substrate does not overlap with the orthographic projection of the fourth anode via on the substrate substrate, and the orthographic projection of the fourth opening on the substrate substrate does not overlap with the orthographic projection of the capacitance via of the fourth sub-pixel driving circuit on the substrate substrate.

18. The display panel according to claim 4, wherein, The first anode, the second anode, the third anode, and the fourth anode are arranged in a 2×2 matrix, wherein the first anode and the second anode are arranged side by side along the second direction, and the third anode and the fourth anode are arranged side by side along the second direction.

19. The display panel according to claim 4, wherein, The pixel has a light-transmitting region and a display region arranged side by side along the first direction, and the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are located in the display region.

20. The display panel according to any one of claims 1-3, wherein, The second direction is perpendicular to the first direction.

21. The display panel according to any one of claims 1-3, wherein, The display panel is an OLED display panel.

22. An electronic device, comprising the display panel according to any one of claims 1-21.

Images