Dual oxide analog switch for neuromorphic switching

Abstract

An exemplary semiconductor structure for neuromorphic applications can include a first layer of a capping substrate material. The first layer can be or can include a first oxide material. The structure can include a second layer disposed adjacent to the first layer. The second layer can be or can include a second oxide material. The structure can also include an electrode material deposited capping the second layer.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 860,313, filed June 12, 2019, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This technology relates to semiconductor processes and equipment. More specifically, this technology relates to the production of semiconductor devices for neuromorphic applications. Background Technology

[0004] Integrated circuits are made possible by processes that create complex patterned material layers on substrate surfaces. Creating patterned materials on substrates requires controlled methods for material deposition and removal. However, producing high-quality material layers presents new challenges for novel device designs.

[0005] Therefore, there is a need for improved systems and methods for producing high-quality devices and structures. This invention addresses these and other needs. Summary of the Invention

[0006] An exemplary semiconductor structure for neuromorphic applications may include a first layer covering a substrate material. The first layer may be or may include a first oxide material. The structure may include a second layer disposed adjacent to the first layer. The second layer may be or may include a second oxide material. The structure may also include electrode material deposited covering the second layer.

[0007] In some embodiments, the first layer may be formed in contact with a substrate material. The substrate material in contact with the first layer may be or may include an electrode material. The electrode material may be or may include at least one of platinum, titanium nitride, or tantalum nitride. The first oxide material and the second oxide material may be or may include one or more of the following: titanium oxide, hafnium oxide, silicon oxide, zirconium oxide, aluminum oxide, magnesium oxide, tantalum oxide, dysprosium oxide, scandium oxide, or lanthanum oxide. The first layer may be or may include silicon oxide, and the second layer may be or may include titanium oxide. The structure may also include a resistive material disposed between the first layer and the substrate material. The resistive material may be or may include one or more of silicon, germanium, gallium, or carbon. The resistive material may be or may include amorphous silicon. The setup and reset current of the semiconductor structure at a 1V on-state voltage may be less than or about 100μA.

[0008] The technology described in this case may also cover methods for forming components for neuromorphic applications. The method may include the step of forming a layer of silicon-containing material covering a substrate. The substrate may be or may contain a metal electrode material, on which the silicon-containing material is formed. The method may also include the step of forming a layer of metal oxide material covering the silicon-containing material.

[0009] In some implementations, the silicon-containing material can be or can include amorphous silicon, and forming the layer of metal oxide material can cause the amorphous silicon to transform into silicon oxide. The silicon oxide can be characterized by a thickness of less than or about 2 nm. At least a portion of the amorphous silicon can remain proximate to the metal electrode material during the transformation. The metal electrode material can include at least one of platinum, titanium nitride, or tantalum nitride. The metal oxide material can be or can include one or more of titanium oxide, hafnium oxide, zirconium oxide, tantalum oxide, dysprosium oxide, scandium oxide, or lanthanum oxide. The method can also include a step of forming an additional electrode material overlying the metal oxide material. The metal oxide material can be characterized by a thickness of greater than or about 5 nm. The formed neuromorphic device can be characterized by bulk switching, as opposed to filamentary switching within the neuromorphic device. The formed device can be characterized by a set and reset current of the neuromorphic device of less than or about 100 μΑ at an ON voltage of 1 V.

[0010] The above-described techniques can provide numerous benefits over conventional systems and techniques. For example, the processes can produce structures capable of including multiple bits per cell operation based on multiple intermediate operating states between a high current state and a low current state. In addition, the processes can provide increased stability of the intermediate states as compared to conventional devices. These and other implementations, along with many of their advantages and features, are described in more detail in conjunction with the below description and attached figures. BRIEF DESCRIPTION OF DRAWINGS

[0011] A further understanding of the nature and advantages of the disclosed technology can be realized by reference to the remaining portions of the specification and the drawings.

[0012] Figure 1 A plan view is shown illustrating one implementation of an exemplary processing system according to some implementations of the present technology.

[0013] Figure 2 A chart is shown illustrating exemplary operations in a method of producing structures for neuromorphic applications according to some implementations of the present technology.

[0014] Figures 3A-3D A cross-sectional view is shown illustrating a substrate processed according to some implementations of the present technology.

[0015] Figure 4 A chart is shown illustrating filamentary device operation according to some implementations of the present technology.

[0016] Figure 5 A chart is shown illustrating structures performing neuromorphic operations according to some implementations of the present technology.

[0017] Figure 6FIG. 1 is a diagram illustrating a structure to perform a neuromorphic operation in accordance with some embodiments of the present technology.

[0018] Figures 7A-7B FIG. 1 is a diagram illustrating a structure to perform a neuromorphic operation in accordance with some embodiments of the present technology.

[0019] Some of the drawings are included as schematic representations. It will be appreciated that these drawings are merely meant to be illustrative and not definitive. Unless otherwise indicated, the drawings are not drawn to scale or proportion. In addition, as schematic representations, the drawings provide what is useful to aid understanding and can not include all aspects or information as compared to a realistic representation, and can include exaggerated materials for illustrative purposes.

[0020] In the drawings, like reference numerals can be used to denote similar components throughout the several views. Additionally, various components of the same type can be distinguished from one another by a letter following the reference numeral. If only the first reference numeral is used in the specification, the description is applicable to any one of the similar components having the same first reference numeral irrespective of the letter. DETAILED DESCRIPTION

[0021] As devices produced in semiconductor processing continue to shrink, alternative structures are being sought to increase the capabilities of the devices while continuing to reduce the device footprint. For example, conventional memory structures include certain limitations. Dynamic random access memory is a structure that is volatile despite featuring relatively advantageous speed. Thus, when the system power is turned off, the memory tends to lose data. Flash memory does not suffer from this loss and maintains data throughout power cycles, however, the read and write processes are performed in multiple cycles, which can be a slower process. Thus, improved memory structures are being developed with various newer material layers. For example, conductive bridge RAM, oxide RAM, magnetic RAM, correlated electron RAM, resistive RAM, and other memory structures are being developed. Many of these structures include new material layers that utilize transition metals or metalloids, which can enhance the operational characteristics of the resulting cells.

[0022] Generally, a dielectric material in a metal-insulator-metal or resistive memory structure is switched between a high resistance state and a lower resistance state by applying a voltage across the metal electrodes. By applying a voltage, such as a set voltage, a conductive path can be formed through the dielectric material, which can be homogeneous or localized. This path can be due to a phase change, formation of a filament, electroforming, or metal insulator transition, which can cause the material to operate as one or both of a memory or a switch. By breaking the conductive path, such as by a reset, the material can revert to a higher resistance state.

[0023] These resistive memory structures often operate by creating a filament or conductive path between electrodes. However, this operation to create these filaments can incur a fundamental conductance limit with a high switching dynamic range, which can limit the cell to 1-bit data, as it can be difficult to maintain a stable intermediate state. For example, a conventional filamentary device can include a metal oxide material between two electrodes. Because of the nature of the oxide, when an insufficient voltage is applied, there can be no conductive path, which can be the low current state or high resistance state of the device. When a sufficient voltage pulse is applied, a conductive filament can be formed, which can quickly transition the device to a high current state or low resistance state. These two stable states can be the storage of data 0 or 1, resulting in a 1-bit cell. Because of the threshold and switching operation, it is often not possible to maintain an intermediate storage state, resulting in these devices being limited to 1-bit data.

[0024] To increase storage to 2-bit data or 4-bit data per cell, 2^(number of bits) stable storage levels can be provided. While resistive RAM as described above can not produce these states, cells for neuromorphic applications improve storage and capability by increasing the number of stable storage values between the 0 and 1 low current state and high current state. The present technology overcomes the problems associated with filamentary resistive RAM by producing more than two stable storage states per cell. By forming a dual oxide structure featuring set and reset currents that can be one or more orders of magnitude lower than conventional resistive RAM, multiple intermediate states can be provided to increase storage to 4, 8, 16, or more storage levels.

[0025] While the remainder of the disclosure will, as is customary, identify specific structures, such as switches, as structures and methods of the present technology can employ, it will be readily understood that this system and method is equally applicable to any number of structures and devices that can benefit from the functionality or characteristics of the developed devices. Thus, the present technology should not be considered limited to use with any particular structure. Moreover, while an exemplary tool system will be described to provide a foundation for the present technology, it will be understood that the present technology can be implemented in any number of semiconductor processing chambers and tools that can perform some or all of the operations to be described.

[0026] Figure 1A plan view of one embodiment of a processing system 100 of deposition, etch, bake, and cure chambers according to some embodiments of the present technology is shown, and the processing system 100 can be particularly configured to perform some or all of the operations described below. In the figure, a pair of front opening unified pods (FOUPs) 102 supply substrates of various sizes, which are received by a robot arm 104 and placed into a low pressure holding area 106, which is then placed into one of the substrate processing chambers 108a-108f located in a tandem section 109a-109c. Although a tandem system is depicted, it should be understood that the present technology equally encompasses platforms incorporating standalone chambers. A second robot arm 110 can be used to transfer substrate wafers from the holding area 106 to the substrate processing chambers 108a-108f and back. Each substrate processing chamber 108a-108f can be equipped to perform a number of substrate processing operations, including any number of deposition processes, including cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), as well as etching, precleaning, annealing, plasma treatment, degassing, orientation, and other substrate processes.

[0027] The substrate processing chambers 108a-108f can include one or more system components for depositing, annealing, curing, and / or etching a material film on a substrate or wafer. In one configuration, two pairs of processing chambers, e.g., 108c-108d and 108e-108f, can be used to deposit a material on a substrate, and a third pair of processing chambers, e.g., 108a-108b, can be used to cure, anneal, or otherwise process the deposited film. In another configuration, all three pairs of chambers, e.g., 108a-108f, can be configured to deposit a film on a substrate and cure the film. Any one or more of the processes described can be performed in additional chambers separate from the manufacturing system shown in different embodiments. It should be understood that the system 100 contemplates additional configurations of deposition, etching, annealing, and curing chambers for material films. Additionally, the present technology can utilize any number of other processing systems, which can incorporate chambers for performing any one of the particular operations. In some embodiments, the chamber system can provide access to multiple processing chambers while maintaining a vacuum environment in each section (as described holding and transfer areas), which can allow for performing operations in multiple chambers while maintaining a particular vacuum environment between discrete processes.

[0028] The system 100, or more specifically the chambers incorporated into the system 100 or other processing systems, can be used to produce structures according to some embodiments of the present technology. Figure 2FIG. 2 illustrates exemplary operations in a method 200 of forming a semiconductor structure for neuromorphic applications in accordance with some embodiments of the present technology. The method 200 can be performed in one or more processing chambers, such as the chambers incorporated into the system 100. The method 200 can or can not include one or more operations prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that can be performed prior to the operations described. The method can include several optional operations as indicated by the figure, which can or can not be specifically associated with some embodiments of the method in accordance with the present technology. The operations illustrated in the method 200 will be described in conjunction with the operations of the method 200, which are illustrated in FIG. 1. Figures 3A-3D The operations illustrated in the method 200 will be described in conjunction with the operations of the method 200, which are illustrated in FIG. 1. Figures 3A-3D It should be understood that FIG. 3 merely illustrates a partial schematic with limited detail, and in some embodiments, the substrate can contain any number of transistors or semiconductor portions having aspects as illustrated in the figure, as well as alternative structural aspects that can still benefit from any aspect of the present technology.

[0029] The method 200 can include optional operations of developing the semiconductor structure for particular fabrication operations. Although in some embodiments the method 200 can be performed on a base structure, in some embodiments the method can be performed after subsequent transistor or other material formation. As Figure 3A As illustrated, the semiconductor structure can represent a device 300 after completion of front-end or other processing. For example, the substrate 305 can be a planar material, or can be a structured device that can include a variety of materials configured as pillars, trenches, or other structures as will be appreciated are similarly encompassed by the present technology. The substrate 305 can include any number of conductive and / or dielectric materials including metals that can include transition metals, post-transition metals, metalloids, and oxides, nitrides, and carbides of any of these materials, as well as any other materials that can be incorporated within the structure.

[0030] One or more layers of material can be formed over some or all of the substrate 305, and at least partially within the substrate, to produce a structure that in embodiments can be a planarized conductive material located within a dielectric material. For example, in some embodiments, the electrode material 310 can optionally be formed to cover the substrate 305, or to be recessed within portions of the substrate material 305. As one non-limiting example, at the exposed surface of the substrate 305 can be a dielectric material, such as silicon oxide or any other dielectric, within which a conductive material can be formed. The electrode material 310 can be a continuous layer across the substrate, or can be formed intermittently across the surface of the substrate as depicted. In one non-limiting example, the conductive material can be or can include a metal that can be formed intermittently across the substrate 305. The metal can include tantalum, praseodymium, hafnium, titanium, iridium, rhodium, platinum, or any other material that can operate as an electrode in a memory structure, or that can be present in alternative structures, for example, and in some embodiments can include a combination of materials and oxides or nitrides of any of these materials.

[0031] In some embodiments, the electrode material 310 can be etched, planarized, or otherwise processed to produce an intermittent pattern that via etching or other formation can expose portions of the substrate 305 between segments of the electrode material 310. Although depicted as a single instance, it should be understood that any number of portions of the electrode material 310 can be included. Additionally, although schematically depicted as including straight sidewalls, the formation or removal process of the electrode material 310 can produce sloped sidewalls. Thus, in some embodiments, the segments of the electrode material 310 can be characterized by a frustum shape, or sloped surfaces along one or more faces of the segments. The substrate 305 that can include the electrode material 310 can be housed or located in a processing region of a semiconductor processing chamber, and the method 200 can be performed to form a semiconductor structure for neuromorphic applications on the substrate.

[0032] The method 200 can include forming a layer of a first oxide material that covers the substrate and the electrode material 310 in operation 205. The first oxide material can be or can include a variety of materials that can operate with a second oxide material to produce a switching material between electrodes of a structured device. The first oxide material can be formed across the electrode material 310, as Figure 3B depicted as a first oxide material 320 in the middle, and the first oxide material 320 can extend completely across the material to cover both areas of the electrode material 310 and the substrate material 305.

[0033] The first oxide material can be formed by any number of deposition techniques, including chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Additionally, the first oxide material can be created by a transformation operation as explained below, where a material that can not include oxygen can first be formed, followed by a secondary operation to transform the material into the first oxide material. The first oxide material can be or can include one or more metal or metal oxide materials that include transition metals, metalloids, or poor metals. Exemplary materials from this list, without being considered limiting, include titanium oxide, hafnium oxide, silicon oxide, zirconium oxide, aluminum oxide, magnesium oxide, tantalum oxide, dysprosium oxide, scandium oxide, or lanthanum oxide, which can include any oxidation state or compound of the material.

[0034] The method 200 can also include the step of forming a layer of a second oxide material adjacent to or in contact with the first oxide material at operation 210. The second oxide material can be the same or different from the first oxide material, and in some embodiments can also include any of the above mentioned formation operations and materials. In some embodiments of the present technology, the second oxide material and the first oxide material can be selected based on the oxygen affinity between the materials. For example, as opposed to filament formation, the first oxide material can provide a weak oxygen exchange layer, facilitating analog bulk switching across the material layer. Thus, the first oxide material and the second oxide material can be selected based on the affinity for oxygen exchange between these layers, which can result in a bulk switching layer and limit or prevent filament formation through the switching material, which can interfere with the stability of the intermediate layer as described above. Additionally, by creating an oxygen exchange layer according to embodiments of the present technology, bulk switching can be performed at lower set and reset currents, and can be orders of magnitude lower compared to filamentary devices.

[0035] To accommodate the oxygen affinity, in some embodiments the second oxide material can be characterized by a higher affinity for oxygen than the first oxide material. Additionally, the first oxide material can be characterized by a sufficient affinity for oxygen to create a certain retention of oxygen. For example, in one non-limiting example, and understanding that many other material pairs can be used, the first oxide material can be or can include silicon oxide, and the second oxide material can be or can include titanium oxide. Titanium oxide can be characterized by a higher affinity for oxygen, which can facilitate the initial state of bonding with titanium. Additionally, titanium can readily donate oxygen to silicon when a sufficient turn-on voltage is applied. Finally, silicon can be characterized by a sufficient affinity for oxygen to retain the oxygen once delivered. For example, when the silicon of this example is replaced with germanium, germanium can be characterized by a lower affinity, and can not be able to sufficiently retain the oxygen when the voltage is removed, essentially forming a volatile memory that can not provide analog bulk switching according to embodiments of the present technology.

[0036] The thickness of the resulting layers can additionally affect the operation described, and thus in some embodiments, the thickness of the second oxide layer can be greater than or about twice the thickness of the first oxide layer. In some embodiments, the thickness of the second oxide layer can be at least or about 3 times, at least or about 4 times, at least or about 5 times, at least or about 6 times, at least or about 7 times, at least or about 8 times, at least or about 10 times, at least or about 12 times, at least or about 15 times, at least or about 20 times, or more, the thickness of the first oxide layer.

[0037] For example, in some embodiments, the first oxide layer (which can be silicon oxide as one example) can be characterized by a thickness of less than or about 5 nm, and can be characterized by a thickness of less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, less than or about 0.5 nm, or less. However, maintaining the first oxide layer within a suitable range can facilitate bulk switching. For example, when the first oxide layer is increased to greater than or about 5 nm, the current distribution can be too low for the device to function adequately. Additionally, if the thickness is reduced to less than or about 1 nm or 0.5 nm, oxygen exchange can not occur between the layers, and more filamentary effects can occur.

[0038] In some embodiments, the first layer can directly contact the electrode material. In some embodiments, an additional resistive layer can be incorporated between the first layer and the electrode material. The resistive material can improve bulk switching by further tuning the current / voltage distribution of the material. Without wishing to be bound by any particular theory, the incorporation of a resistive material can provide a series resistance to the switching structure, can control over-programming of the switching material, and control intermediate switching states. The resistive material can be an amorphous material or some crystalline material disposed between the electrode material and the first oxide material.

[0039] Exemplary materials can include any metalloid, poor metal, or other material that can further tune the structure. In one embodiment, the resistive material can be a chalcogenide, such as carbon, silicon, germanium, or tin. Additional materials can be or can include materials that provide similar or other resistive properties, can include materials such as gallium, vanadium, niobium, and combination materials such as silicon germanium, and many other materials that can similarly be used to adjust the resistance through the structure. The resistive layer can be formed to a thickness that facilitates control of the voltage distribution of the device. Thus, to produce a sufficient effect, the resistive layer can be greater than or about 2 nm, and in some embodiments can be greater than or about 3 nm, greater than or about 4 nm, greater than or about 5 nm, greater than or about 6 nm, greater than or about 8 nm, greater than or about 10 nm, or more.

[0040] The step of producing a resistive layer of material can be performed in one or more ways, including by deposition or formation by any of the methods described above. In this way, Figure 3B A resistive layer of material formed over the bottom electrode can be depicted in some embodiments. Additionally, in some embodiments, this resistive material can be used to form a first oxide material. For example, although any of the first oxide materials can be deposited over an electrode material or a resistive material, in some embodiments, a transformation can be performed at optional operation 215 of method 200. As one non-limiting example, and continuing with the previously mentioned materials, silicon, such as amorphous silicon, can be deposited over an electrode on a substrate. When a second material layer, such as titanium oxide, is formed, a portion of the amorphous silicon can be transformed into silicon oxide. In some embodiments, the entire thickness of the amorphous silicon can be transformed into silicon oxide, although in some embodiments, a quantified amount of amorphous silicon can remain between the resulting silicon oxide and the electrode material.

[0041] Thus, Figure 3C A number of embodiments can be depicted. For example, layer 320 can be a first oxide material as previously discussed, and can optionally not include layer 330. In some embodiments, layer 320 can be a resistive layer deposited over a substrate, and in some embodiments, layer 330 can be a first oxide material formed over the resistive material. In some embodiments, layer 340 can be a second oxide material formed over the first oxide material, although as described above, in some embodiments, the second oxide material layer 340 can be formed directly to cover the resistive material, which can transform some or all of the resistive material into a first oxide material as previously described. In optional operation 220 of method 200, additional electrode material can be formed to cover the second oxide material, and can be any of the electrode materials previously described. As Figure 3D As depicted in FIG. 4, electrode material 350 (which can be the same as or different from electrode material 310) can be formed to cover the second electrode material 340. From Figure 3D The depicted devices can not include all of the layers depicted, depending on the incorporation of a resistive material and / or transformation operations used to produce a first oxide material can accommodate each of the variations mentioned above.

[0042] Figure 4 A chart 400 illustrating filament device operation in accordance with some embodiments of the present technology is shown. As previously described, the filament device can be formed in accordance with any of the methods described above, and can include any of the materials described above. Figure 4In contrast to the filamentary device switching illustrated, the present technology can perform analog bulk switching, which can be produced based on the structure or thickness of the material layers. As previously described, the filamentary device can be characterized by a more abrupt change in characteristics of the high dynamic on-off range. As illustrated, when no filament is present, the device can be in a low current state or high resistance state, as illustrated at 410. When a voltage is applied to the device sufficient to produce a filament, the current state changes abruptly, which can almost completely switch the device to a high current state, as illustrated at 420. When another voltage pulse is applied, a thicker filament can be produced, increasing the current state, although still within the range of high current position, as illustrated at 430. Thus, due to the nature of the switching element, there is little or no intermediate state between the low current state and the high current state.

[0043] Figure 5 A graph 500 illustrating device operation for neuromorphic applications according to some embodiments of the present technology is shown. Graph 500 can illustrate the multiple intermediate states possible between a high current on state and a low current off state for a bulk switching or analog switching device according to some embodiments of the present technology. As illustrated at 510, when a voltage pulse is applied across the device, a low current state can be formed based on a relatively thin depletion layer between a first oxide material and a second oxide material. As the voltage continues to be pulsed, an intermediate, stable, higher current state 520 can be produced related to the amount of depletion extending into the first oxide material. Because this depletion layer can be controlled in the structure according to embodiments of the present technology, the intermediate position can be stabilized. As the voltage continues to be applied to the device, the device can transition through a number of additional stable states as illustrated before reaching the highest current state 530 of the device. A device according to the present technology can be characterized by controlled transitions between stable intermediate states between the low current state and the high current state.

[0044] Figure 6A graph 600 illustrating device operation for neuromorphic applications according to some embodiments of the present technology is shown. Graph 600 can plot on a logarithmic scale current-voltage characteristics of a device according to some embodiments of the present technology. As shown, a device for neuromorphic applications according to the present technology can be characterized by lower set and reset currents than conventional devices. For example, at an ON voltage of 1 V, many filamentary RAM devices can be characterized by set and reset currents greater than or about 100 μΑ, and can be characterized by set and reset currents greater than or about 500 μΑ, greater than or about 1 mA, greater than or about 10 mA, or greater. A device according to some embodiments of the present technology can be characterized by lower set and reset currents as shown. For example, at an ON voltage of 1 V, a device according to some embodiments of the present technology can be characterized by set and reset currents less than or about 100 μΑ, and the characteristics of other operating ON voltages can be characterized by set and reset currents less than or about 50 μΑ, less than or about 20 μΑ, less than or about 10 μΑ, less than or about 5 μΑ, less than or about 1 μΑ, less than or about 0.5 μΑ, less than or about 0.1 μΑ, less than or about 0.05 μΑ, less than or about 0.01 μΑ, or less.

[0045] Figures 7A-7B A graph illustrating device operation for neuromorphic applications according to some embodiments of the present technology is shown. Figure 7A Devices without additional resistive layers can be plotted according to some embodiments of the present technology, while Figure 7B Devices incorporating a resistive layer between the first oxide layer and the electrode of the device can be plotted. As shown, while devices without a resistive layer provide a current distribution as previously discussed to facilitate analog switching, incorporating a resistive layer can further modify the current-voltage distribution of the device. By allowing the conductive linear through the device stack to be modified and straightened, this can allow greater flexibility and control over the intermediate states, which can result in further stability and control over voltage pulses to adjust between intermediate states of the device. Thus, by creating a device for neuromorphic applications according to some embodiments of the present technology, bulk switching can be provided to allow an increased number of bits per cell operation, and improved characteristics compared to filamentary resistive devices.

[0046] In the foregoing description, for purposes of explanation, numerous details are set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments can be practiced without some or all of these details.

[0047] Having disclosed several embodiments, those skilled in the art will recognize, in light of the present disclosure, that many changes can be made within the spirit of the embodiments and will have ideas for modifications of their own. Thus, nothing in the present cases should be taken as a limitation on these scopes. In addition, methods or processes can be described as sequential or in steps, but it is to be understood that operations can be performed simultaneously, or in different order than listed.

[0048] When a range of values is provided, it is understood that each intervening value, to the minimum resolution of the range, between the upper and lower limits of that range is also specifically disclosed. Any narrower ranges given throughout this specification are also specifically disclosed. The upper and lower limits of these smaller ranges can independently be included in the range, or be excluded from the range, and each range where either, neither, or both limits are included in the smaller ranges is also contemplated. Where the described range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0049] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural reference unless the context clearly dictates otherwise. Thus, for example, a reference to "a precursor" includes a plurality of such precursors, and a reference to "the layer" is a reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0050] Further, as used in the specification and the claims, the words "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including" when used in this specification and in the following claims are taken to specify the presence of stated features, integers, steps, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, steps, components, operations, acts, or groups.

Claims

1. A semiconductor structure for neuromorphic applications, the semiconductor structure comprising: a first layer overlying a substrate material, wherein the first layer comprises a first oxide material, and wherein the first layer is formed in contact with the substrate material; a second layer disposed adjacent to the first layer, wherein the second layer comprises a second oxide material; and an electrode material deposited overlying the second layer, wherein the first oxide material and the second oxide material are characterized by: an oxygen affinity of the second oxide material relative to an oxygen affinity of the first oxide material resulting in an exchange between the second oxide material and the first oxide material sufficient to cause bulk switching in the semiconductor structure and prevent filament formation when a set current is applied to the semiconductor structure.

2. The semiconductor structure for neuromorphic applications of claim 1, wherein the substrate material in contact with the first layer comprises an electrode material.

3. The semiconductor structure for neuromorphic applications of claim 2, wherein the electrode material comprises at least one of platinum, titanium nitride, or tantalum nitride.

4. The semiconductor structure for neuromorphic applications of claim 1, wherein the first oxide material and the second oxide material comprise one or more of titanium oxide, hafnium oxide, silicon oxide, zirconium oxide, aluminum oxide, magnesium oxide, tantalum oxide, dysprosium oxide, scandium oxide, or lanthanum oxide.

5. The semiconductor structure for neuromorphic applications of claim 4, wherein the first layer comprises silicon oxide, and wherein the second layer comprises titanium oxide.

6. The semiconductor structure for neuromorphic applications of claim 1, further comprising a resistive material disposed between the first layer and the substrate material, wherein the resistive material comprises one or more of silicon, germanium, gallium, or carbon.

7. The semiconductor structure for neuromorphic applications of claim 1, wherein a set and reset current of the semiconductor structure is less than or about 100 µA at a turn-on voltage of 1 V.

8. A method of forming a device for neuromorphic applications, the method comprising the steps of: forming a layer of a silicon-containing material overlying a substrate, wherein the substrate comprises a metallic electrode material over which the silicon-containing material is formed; and forming a layer of a metallic oxide material overlying the silicon-containing material, wherein the silicon-containing material comprises amorphous silicon, and wherein the step of forming the layer of the metallic oxide material results in a transformation of the amorphous silicon to silicon oxide.

9. The method of forming a device for neuromorphic applications of claim 8, wherein the silicon oxide is characterized by a thickness of less than or about 2 nm, and wherein at least a portion of the amorphous silicon is maintained in close proximity to the metallic electrode material during the transformation.

10. The method of forming a device for neuromorphic applications of claim 8, wherein the metallic electrode material comprises at least one of platinum, titanium nitride, or tantalum nitride.

11. The method of forming a device for neuromorphic applications of claim 8, wherein the metal oxide material is characterized by a thickness greater than or about 5 nm, and wherein the metal oxide material comprises one or more of: titanium oxide, hafnium oxide, zirconium oxide, tantalum oxide, dysprosium oxide, scandium oxide, or lanthanum oxide.

12. The method of forming a device for neuromorphic applications of claim 8, further comprising the steps of: forming an additional electrode material covering the metal oxide material.

13. The method of forming a device for neuromorphic applications of claim 8, wherein the formed device is characterized by bulk switching as compared to filamentary switching within the device, and wherein the formed device is characterized by a set and reset current of the device less than or about 100 µA at an on voltage of 1 V.

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