Method and address remapping unit for virtual addresses to physical addresses

Abstract

This disclosure proposes a method and an address remapping unit for remapping a virtual address to a physical address. The method includes: receiving a remapping request by a remapping processing unit of the address mapping unit, decoding the remapping request, and determining whether the remapping request has a Direct Memory Access (DMA) remapping request; and when the remapping request has the DMA remapping request, executing a remapping procedure to translate a virtual address corresponding to the remapping request to a physical address.

Description

Technical Field

[0001] This disclosure relates to the field of microelectronics, and in particular to a method and address remapping unit for remapping virtual addresses to physical addresses. Background Technology

[0002] In computer systems, I / O devices are a crucial component. Increased computing power of the Central Processing Unit (CPU) can improve data processing speed, but this requires data to be delivered to the CPU in real time. Therefore, the processing power of I / O devices is a key indicator of a computer system's performance. I / O virtualization aims to solve the problem of data exchange between I / O devices and virtual machines. With the development of virtualization technology and heterogeneous computing, improving the efficiency of address remapping and the speed of cache lookups have become pressing issues. Summary of the Invention

[0003] The following disclosure is exemplary only and is not intended to limit in any way. In addition to the illustrative aspects, implementations, and features described, other aspects, implementations, and features will also become apparent from the accompanying drawings and the detailed description below. That is, the following disclosure is provided to introduce concepts, key points, benefits, and novel and non-obvious technical advantages described herein. Selected, and not all, embodiments will be further described in detail below. Therefore, the following disclosure is not intended to represent all essential features of the claimed subject matter, nor is it intended to determine the scope of use of the claimed subject matter.

[0004] This disclosure proposes a method for remapping a virtual address to a physical address in an address mapping unit, comprising: receiving a remapping request by a remapping processing unit of the address mapping unit, decoding the remapping request, and determining whether the remapping request has a Direct Memory Access (DMA) remapping request; and when the remapping request has the DMA remapping request, executing a remapping procedure by the remapping processing unit: translating a virtual address corresponding to the remapping request to a physical address.

[0005] In some embodiments, the method further includes: receiving a remapping request transmitted by an endpoint device through a remapping request interface of the address mapping unit; and receiving the remapping request transmitted by the remapping request interface through an arbitrator of the address mapping unit, and transmitting the remapping request to the remapping processing unit.

[0006] In some embodiments, the method further includes: when the remapping processing unit determines that the remapping request is erroneous, transmitting an error message to an error message control unit to report that the remapping request is erroneous; and transmitting an interruption result to an output result unit to discard the remapping request.

[0007] In some embodiments, the method further includes: when the remapping processing unit determines that the remapping request has an interruption request, the remapping process is interrupted by the remapping processing unit.

[0008] In some embodiments, when the remapping request has the DMA remapping request, the method further includes: issuing a search command to a cache control logic unit by the remapping processing unit; wherein when the cache control logic unit completes the search for the virtual address, it issues a cache hit signal for the virtual address to an output result unit and executes the remapping procedure, or issues a cache miss signal for the virtual address to a reordering control unit.

[0009] In some embodiments, the method further includes: after the reordering control unit receives the cache miss signal transmitted by the remapping processing unit, the reordering control unit issues a read request to a memory; the reordering control unit receives data transmitted by the memory and determines whether the data includes an error message; and when the data includes the error message, the reordering control unit discards the remapping request and transmits the error message to an error message control unit to report that the remapping request is erroneous.

[0010] In some embodiments, when the data does not include the error information, the reordering control unit issues an update command to update the cache control logic unit.

[0011] In some embodiments, the update command has a higher priority than the search command.

[0012] In some embodiments, the method further includes: receiving the physical address transmitted by the remapping processing unit through a physical address output interface of the address mapping unit, and transmitting a remapping response including the physical address to the endpoint device.

[0013] In some embodiments, the cache control logic unit includes: Context cache, PASID cache, IOTLB cache, PML5 cache, PML4 cache, PDPE cache, PDE cache and IRTE cache. This includes a context cache, a process address space identifier (PASID) cache, an input / output translation lookaside buffer (IOTLB) cache, a PML5 cache, a PML4 cache, a PDPE cache, a PDE cache, and an interrupt remapping table entry (IRTE) cache. In another embodiment, the cache control logic unit 210 can support search commands, update commands, and invalidation commands. In one embodiment of the present invention, the cache control logic unit 210 may include a 5-level page-map level-4 (PML4) table, a 4-level page-map level-4 (PML4) table, a page-directory-pointer (PDP) table, a page directory (PD) table, a page table (PT), and physical pages. The PML4 table consists of PML4 table entries (PML4E), and the PDP table consists of PDP table entries (PDP...). The table is composed of TableEntry (PDPE), the PD table is composed of PD Table Entry (PDE), and the PT is composed of PT Entry (PTE).

[0014] In some embodiments, when the error information control unit receives the error information, it records the error information to an error recording register or a resident error log in a memory, and sends a message signaled interrupt (MSI) to a processor.

[0015] In some embodiments, the method further includes: receiving a page request or an invalid request corresponding to a page through a page request and invalidation control interface via a page request and invalidation control logic unit of the address mapping unit; determining whether the page request or the invalid request includes an error message through the page request and invalidation control logic unit; and when the page request or the invalid request includes the error message, transmitting the error message to an error message control unit through the page request and invalidation control logic unit to report that the page request or the invalid request is erroneous.

[0016] In some embodiments, the method further includes: issuing a page search command to a cache control logic unit via the page request and invalidation control logic unit; wherein when the cache control logic unit completes the page search, it issues a cache hit signal or a cache miss signal to the page request and invalidation control logic unit; and when the page request and invalidation control logic unit receives the cache miss signal, it transmits the page request carrying the cache miss signal to one of the miss queue processing units of the reordering control unit.

[0017] In some embodiments, after receiving the page request, the reordering control unit further includes: issuing a read request to a memory to perform a page walk; receiving data transmitted from the memory and determining whether the data includes an error message; and when the data includes the error message, discarding the page request and transmitting the error message to an error message control unit to report that the page request is erroneous.

[0018] In some embodiments, the method further includes: when the data does not include the error information, updating the cache control logic unit by issuing an update command through the reordering control unit.

[0019] In some embodiments, the method further includes: receiving, via an uplink stream arbitrator of the address mapping unit, the remapping request from the remapping processing unit, the message signal interrupt from the error information control unit, the read request from the reordering control unit, and a page request or an invalid request from the page request and invalidation control logic unit; and transmitting, via the uplink stream arbitrator, the remapping request, the message signal interrupt, the read request, and the page request or the invalidation request to the memory or the processor in a sequential manner through an uplink stream control interface.

[0020] This disclosure proposes an address remapping unit, comprising: a remapping processing unit including four parallel processing units, wherein a first processing unit of the processing unit receives a remapping request, decodes the remapping request, and determines whether the remapping request has a Direct Memory Access (DMA) remapping request; and when the remapping request has the DMA remapping request, executes a remapping procedure: translating a virtual address corresponding to the remapping request to a physical address. Attached Figure Description

[0021] Figure 1 This is a schematic diagram showing a single-chip system according to an embodiment of the invention.

[0022] Figure 2 This is a structural diagram showing an address remapping unit according to an embodiment of the present invention.

[0023] Figure 3 This is a flowchart illustrating a method for remapping a virtual address to a physical address according to an embodiment of this disclosure.

[0024] Figure 4 This is a schematic diagram showing a context cache according to an embodiment of the present disclosure.

[0025] Figure 5 This is a schematic diagram illustrating a fast search cache method according to an embodiment of the present disclosure.

[0026] Figure 6 This is a schematic diagram showing a page structure cache according to an embodiment of the present disclosure.

[0027] Figure 7 This is a schematic diagram illustrating a fast search cache method according to an embodiment of the present disclosure.

[0028] Figure 8 This is a schematic diagram showing a page structure cache according to an embodiment of the present disclosure.

[0029] Figure 9 This is a schematic diagram illustrating a fast search cache method according to an embodiment of the present disclosure.

[0030] Figure 10 This demonstrates an exemplary operating environment for implementing embodiments of the present disclosure. Detailed Implementation

[0031] A wider description of various aspects of this disclosure will be given below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as being limited to any particular structure or function presented throughout this disclosure. Rather, providing these aspects will make this disclosure comprehensive and complete, and will give those skilled in the art a full understanding of its scope. Based on the teachings herein, those skilled in the art will recognize that the scope of this disclosure is intended to cover any aspect disclosed herein, whether implemented alone or in combination with any other aspect of this disclosure. For example, it may be implemented using any number of the means or methods presented herein. Furthermore, in addition to the various aspects of this disclosure presented herein, the scope of this disclosure is also intended to cover means or methods implemented using other structures, functions, or structures and functions. It should be understood that any aspect disclosed herein may be embodied by one or more elements of the claims.

[0032] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” No aspect of this disclosure or design described herein as “exemplary” is necessarily to be construed as preferred or superior to other aspects of this disclosure or design. Furthermore, the same numerals indicate the same elements in all the various figures, and unless otherwise specified in the description, the articles “a” and “above” include multiple references.

[0033] It is understood that when an element is described as being “connected” or “coupled” to another element, the element may be directly connected to or coupled to the other element, or there may be intermediate elements. Conversely, when an element is described as being “directly connected” or “directly coupled” to another element, there are no intermediate elements. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between”, “adjacent” vs. “directly adjacent”, etc.).

[0034] Figure 1 This is a schematic diagram showing a System on a Chip (SoC) system 100 according to an embodiment of the invention. (See attached diagram.) Figure 1 As shown, the system-on-a-chip system 100 includes a processor 110, a northbridge chip 120, a memory 140, and multiple endpoint devices 130.

[0035] Processor 110 refers to a central processing unit (CPU) of any type of architecture, such as an embedded processor, mobile processor, microcontroller, digital signal processor, superscalar computer, vector processor, single instruction multiple data (SIMD) computer, complex instruction set (CISC) computer, reduced instruction set computer (RISC), very long instruction word (VLIW) or hybrid architecture processor.

[0036] Endpoint device 130 can be divided into two types: (1) Shared Virtual Memory (SVM) device or PCIE (Peripheral Component Interface Express) device that supports Process Address Space ID (PASID) and ATS functions; (2) Traditional devices, such as traditional serial bus (SB), universal serial bus (USB), serial ATA (Serial Advanced Technology Attachment), etc.

[0037] Memory 140 is coupled to processor 110 and includes multiple pages, wherein memory 140 is dynamic random access memory (DRAM). Northbridge chip 120 is coupled to processor 110 and endpoint device 130, and includes at least an address remapping unit 122. When an endpoint device 130 issues a remapping request through northbridge chip 120, address remapping unit 122 can remap the virtual address of the corresponding endpoint device 130 to a physical address according to a mapping table, and transmit the physical address to processor 110. Processor 110 then performs write or read operations on the physical address in memory 140.

[0038] In addition to address remapping, the address remapping unit 122 can also perform interrupt remapping for Extend Advanced Programmable Interrupt Controller (EPC) functionality. To achieve high performance, the address remapping unit 122 will include some caching (also referred to as a cache) in this invention. When the system-on-a-chip (SoC) 100 settings change, the software portion of SoC 100 can notify the address remapping unit 122 to invalidate its cache. The following describes... Figure 1 right Figure 2 Please provide an explanation.

[0039] Figure 2This is a structural diagram showing the address remapping unit 122 according to an embodiment of the present invention.

[0040] like Figure 2 As shown, the address remapping unit 122 includes a remapping request interface 202 and an arbitrator 204. The remapping request interface 202 receives remapping requests 1 to n transmitted from multiple endpoint devices and forwards them to the arbitrator 204. Each endpoint device is coupled to a separate remapping request interface 202 to reduce mutual interference between endpoint devices. The remapping request interface 202 can also support asynchronous or synchronous interface control for different interface protocols. The arbitrator 204 is coupled to the remapping request interface 202 and transmits remapping requests to the remapping processing unit 206. When the arbitrator 204 receives multiple remapping requests simultaneously, it can arbitrate the multiple remapping requests to determine the transmission order. The arbitrator 204 can support synchronous devices, support both normal and high-priority arbitration algorithms, and support a round-robin arbitration algorithm.

[0041] like Figure 2 As shown, the address remapping unit 122 also includes a remapping processing unit 206, a reordering control unit 208, a cache control logic unit 210, an error information control unit 212, a page request and invalidation control logic unit 214, an output result unit 216, a page request and invalidation control interface 218, an uplink stream arbitrator 220, and an uplink stream control interface 222.

[0042] The remapping processing unit 206 includes four parallel processing units CMPQ0 to CMPQ3, wherein each of the processing units CMPQ0 to CMPQ3 can receive a remapping request, decode the remapping request, and determine whether the remapping request has a Direct Memory Access (DMA) remapping request.

[0043] Since the waiting period for the remapping processing unit 206 to process the DMA remapping request is four cycles (4T), the four parallel processing units CMPQ0 to CMPQ3 can ensure that the DMA remapping request can be processed in each cycle. When the remapping processing unit 206 determines that the remapping request has a DMA remapping request, the remapping processing unit 206 executes a remapping procedure: translating a virtual address corresponding to the remapping request to a physical address.

[0044] It should be noted that when the remapping processing unit 206 simultaneously receives requests from both the reordering control unit 208 and the arbitrator 204, the request from the reordering control unit 208 will be processed first, as it has a higher priority than the request from the arbitrator 204. Furthermore, to avoid deadlock, the time when the remapping processing unit 206 sends its request to the reordering control unit 208 and the time when the reordering control unit 208 sends its request to the remapping processing unit 206 must fall within the same period T.

[0045] When the remapping processing unit 206 determines that the remapping request is erroneous, it transmits an error message Err to the error information control unit 212 to report the error. The remapping processing unit 206 then transmits an interrupt result to the output result unit 216 to discard the erroneous remapping request. In one embodiment, after receiving the error message Err, the error information control unit 212 can record the error message Err to an error recording register or a resident error log in the memory 140, and transmit a message signaled interrupt (MSI) to the processor 110.

[0046] When the remapping processing unit 206 determines that the remapping request has an interrupt request INT, the remapping processing unit 206 interrupts the remapping procedure.

[0047] After the processing units CMPQ0 to CMPQ3 determine that the above remapping request has the above DMA remapping request, they can issue a search command SCH to the cache control logic unit 210. When the cache control logic unit 210 completes the search for the above virtual address, it will issue a cache hit signal of the above virtual address to an output result unit 216 and execute the remapping procedure, or issue a cache miss signal of the above virtual address to the reordering control unit 208.

[0048] In one embodiment, the cache control logic unit 210 may include: a context cache, a PASID cache, an IOTLB cache, a PML5 cache, a PML4 cache, a PDPE cache, a PDE cache, and an IRTE cache. In another embodiment, the cache control logic unit 210 may support search commands, update commands, and invalidation commands. In one embodiment of the present invention, the cache control logic unit 210 may include a 5-level page-map level-4 (PML4) table, a 4-level page-map level-4 (PML4) table, a page-directory-pointer (PDP) table, a page directory (PD) table, a page table (PT), and physical pages. Among them, the PML4 table is composed of PML4 table entries (PML4E), the PDP table is composed of PDP table entries (PDPE), the PD table is composed of PD table entries (PDDE), and the PT table is composed of PT entries (PTEntry, PTE).

[0049] The reordering control unit 208 includes an eight-layer cache miss processing unit 2082. When the reordering control unit 208 receives a cache miss signal from the remapping processing unit 206, it can issue a read request to the memory 140. Next, the reordering control unit 208 receives data from the memory 140 and determines whether the data includes an error message Err. If the data includes the error message Err, the remapping request is discarded, and the error message Err is transmitted to the error message control unit 212 to report that the remapping request is erroneous. If the data does not include the error message Err, the reordering control unit 208 issues an update command to update the cache control logic unit 210. In one embodiment, the update command has a higher priority than the search command SCH.

[0050] The physical address output interface 216 is coupled to the remapping processing unit 206, receives the physical address transmitted by the remapping processing unit 206, and transmits remapping response 1 to remapping response n, including the physical address, to the endpoint device.

[0051] The page request and invalidation control logic unit 214 supports two invalidation methods: a register-based method and a queued invalidation method, and confirms the sequential requirements of invalid request, invalid response, page request, and page response. The page request and invalidation control logic unit 214 can receive a page request or an invalidation request corresponding to a page transmitted by an endpoint device through a page request and invalidation control interface 218. After receiving a page request or invalidation request, the page request and invalidation control logic unit 214 can determine whether the page request or invalidation request includes an error message Err. When the page request or invalidation request includes the error message Err, the page request and invalidation control logic unit 214 transmits the error message Err to the error message control unit 212 to report that the page request or invalidation request is erroneous.

[0052] The page request and invalidation control logic unit 214 can transmit invalidation responses and page responses to the endpoint device through the page request and invalidation control interface 218.

[0053] In one embodiment, the page request and invalidation control logic unit 214 may further issue a page search command to the cache control logic unit 210. When the cache control logic unit 210 completes the page search, it issues a cache hit signal or a cache miss signal to the page request and invalidation control logic unit 214. After receiving the cache miss signal, the page request and invalidation control logic unit 214 will transmit the page request carrying the cache miss signal to one of the miss queue processing units 2082 of the reordering control unit 218 for processing.

[0054] After receiving a page request, the reordering control unit 208 sends a read request to the memory 140 to perform a page walk. Next, the reordering control unit 208 receives data transmitted from the memory 140 and determines whether the data includes an error message Err. If the data includes Err, the page request is discarded, and the error message Err is transmitted to the error information control unit 212 to report an error in the page request. If the data does not include Err, the reordering control unit 208 can issue an update command to update the cache control logic unit 210. Furthermore, the reordering control unit 208 can also send an update result to the remapping processing unit 206, which can determine whether to search the cache control logic unit 210 again based on the update result.

[0055] Uplink stream arbitrator 220 is coupled to remapping processing unit 206, error information control unit 212, reordering control unit 208, and page request and invalidation control logic unit 214. Uplink stream arbitrator 220 receives remapping requests from remapping processing unit 206, message signal interruptions from error information control unit 212, read requests from reordering control unit 208, and a page request or an invalidation request from page request and invalidation control logic unit 214. Uplink stream arbitrator 220 arbitrates the aforementioned remapping requests, message signal interruptions, read requests, page requests, and invalidation requests, and transmits these requests sequentially to memory 140 or processor 110 via uplink stream control interface 222, wherein uplink stream control interface 222 has a four-level request queue and supports an automatic operation interface.

[0056] Figure 3 This is a flowchart illustrating a method 300 for remapping a virtual address to a physical address according to an embodiment of this disclosure. Please also refer to... Figure 1 and Figure 2 ,like Figure 3 As shown, in step S305, the remapping processing unit 206 of the address mapping unit 122 receives a remapping request, decodes the remapping request, and determines whether the remapping request has a Direct Memory Access (DMA) remapping request. In step S310, when the remapping request has the DMA remapping request, a remapping procedure is executed: translating a virtual address corresponding to the remapping request to a physical address.

[0057] Figure 4 This is a schematic diagram showing a context cache 400 according to an embodiment of the present disclosure.

[0058] The context cache 400 is used to cache context entries (or extended context entries) used to process translation requests and maps SIDs to SLPTPTR or PASIDPTR and DIDs. Each entry in the context cache is a separate context entry (or extended context entry).

[0059] For context cache 400, which does not include extended context entries, only context cache 410 is included, which includes the following information:

[0060] (1) FPD;

[0061] (2)T;

[0062] (3) SLPTPTR;

[0063] (4)AW;

[0064] (5) DID;

[0065] (6) SID;

[0066] (7) LRU; and

[0067] (8)INV.

[0068] For the context cache 400, which includes extended context input, in addition to the context cache 410, it also contains the following information 420:

[0069] (9) PRE;

[0070] (10)NESTE;

[0071] (11) PASIDE;

[0072] (12)PGE;

[0073] (13)NXE;

[0074] (14) WPE;

[0075] (15)SMEP;

[0076] (16)ERE;

[0077] (17)EAFE;

[0078] (18)SLEE;

[0079] (19) PTS; and

[0080] (20)PASIDPTR.

[0081] To simplify the process of mapping devices to domains and to streamline hardware implementation, the contents of both context entries and extended context entries are cached in a context cache. This disclosure adds a bit to an EXTEN field in the context cache to indicate whether the current context entry stored in the context cache is a context entry or an extended context entry. As shown, a bit of 1 in the EXTEN field indicates that the current context entry is an extended context entry, and a bit of 0 in the EXTEN field indicates that the current context entry is a context entry.

[0082] Figure 5This is a schematic diagram illustrating a fast cache search method 500 according to an embodiment of the present disclosure, and an apparatus for a fast cache search, wherein the apparatus may be an address remapping unit. In step S505, the apparatus adds a bit to a context cache to indicate that the current context entry stored in the context cache is a context entry or an extended context entry, wherein a bit of 1 indicates that the current context entry is the extended context entry and a bit of 0 indicates that the current context entry is the context entry.

[0083] Remapping hardware can cache page structure entries that reference other page structure entries (e.g., entries opposite to page frames). Three types of page structure caches are listed below:

[0084] (1) First-level page structure entries: Each entry is the physical address of the first-level page structure mapped from the upper part of the input address in the request with PASID to the corresponding area used to translate the input address space, as well as information about access permissions.

[0085] (2) Second-level page structure entries: Each entry is the physical address of the second-level page structure that maps from the upper part of the guest-physical address to the corresponding area used to translate the guest-physical address space, as well as information about access permissions.

[0086] (3) Nested paging structure entries: Each entry is the physical address of the first-level paging structure (after the second-level translation nesting) mapped from the upper part of the input address in the request with PASID to the corresponding region of the input address space, as well as information about access permissions.

[0087] Figure 6 This is a schematic diagram showing a page-structure cache 600 according to an embodiment of the present disclosure. In this embodiment, the page-structure cache 600 is a PML4E cache, which mainly includes the following information 610:

[0088] (1) DID;

[0089] (2) PASID;

[0090] (3) PASIDE;

[0091] (4) LRU;

[0092] (5) INV; and

[0093] (6)VA.

[0094] For first-level pagination structure entries, in addition to the information 610 mentioned above, the following information 620 may also be included:

[0095] (7) R / W;

[0096] (8) U / S;

[0097] (9)XD; and

[0098] (10)SRE.

[0099] For entries in the second-level pagination structure, in addition to the information 610 mentioned above, the following information 630 may also be included:

[0100] (7)R;

[0101] (8)W; and

[0102] (9)X.

[0103] For nested pagination structure entries, in addition to the information 610 mentioned above, the following information 640 may also be included:

[0104] (7) R / W;

[0105] (8) U / S;

[0106] (9)XD;

[0107] (10) SRE; and

[0108] (11)PTEPTSLW.

[0109] To simplify page traversal and hardware implementation, this disclosure caches the contents of all three types of PML4E entries in a PML4E cache. The address remapping unit adds a mapping type field to a page-structure cache to indicate whether the current page-structure entry stored in the page-structure cache is a first-level page-structure entry, a second-level page-structure entry, or a nested page-structure entry. As shown in the figure, the mapping type field consists of two bits: 00 indicates that the current page-structure entry is a first-level page-structure entry; 10 indicates that the current page-structure entry is a second-level page-structure entry; and 01 indicates that the current page-structure entry is a nested page-structure entry.

[0110] Figure 7This is a schematic diagram illustrating a fast cache search method 700 according to an embodiment of the present disclosure, and an apparatus for a fast cache search, wherein the apparatus may be an address remapping unit. In step S705, the apparatus adds a mapping type field to a page-structure cache to indicate that the current page-structure entry stored in the page-structure cache is a first-level page-structure entry, a second-level page-structure entry, or a nested page-structure entry, wherein the mapping type field consists of two bits. The two bits being 00 indicates that the current page-structure entry is the first-level page-structure entry, the two bits being 10 indicates that the current page-structure entry is the second-level page-structure entry, and the two bits being 01 indicates that the current page-structure entry is the nested page-structure entry.

[0111] When the page structure specifies the use of page translation larger than 4 kilobytes (KB), some hardware implementations may choose to cache multiple smaller page IOTLB entries for translation. Even if a portion of the page number is relative to the page offset specified by the page structure, each IOTLB entry will be associated with a page number corresponding to the smaller page size. The higher bits of the physical address in the IOTLB entry are derived from the physical address used to establish the translation PDE, while the lower bits come from the input address used to establish the translation access.

[0112] There is a drawback to implementing caching in this way. Taking a 2MB superpage as an example, when the first remapping request with virtual address VA[HAW-1:12] = 'h123456' is sent to the remapping processing unit, a cache search will miss. After retrieving the PDE from memory, it will be found to be a 2MB superpage, meaning that after translation, the translation result will be cached in the IOTLB according to the above format. When the second remapping request with virtual address VA[HAW-1:12] = 'h123457' is sent to the remapping processing unit, since the superpage information has not been stored in the cache, a cache search will still miss.

[0113] Therefore, the following explains how this disclosure solves the above-mentioned problem. When the PDE cache corresponding to the first remapping request is retrieved, the remapping processing unit will find that the PDE cache is a 2MB superpage. At this time, the remapping processing unit does not update the IOTLB, but updates the PDE cache instead. More specifically, the remapping processing unit adds a page size PS (pagesize) field to the page structure cache to indicate whether the current page structure entry stored in the page structure cache is a 2MB superpage structure entry or a 1GB superpage structure entry, wherein the PS field consists of one bit. A bit of 0 indicates that the current page structure entry is the 1GB superpage structure entry, and a bit of 1 indicates that the current page structure entry is the 2MB superpage structure entry.

[0114] Figure 8 This is a schematic diagram showing a page structure cache 800 according to an embodiment of the present disclosure. As shown in the figure, with Figure 6 The page structure is different from 610. Figure 8 The page structure 810 in the new configuration adds a PS field 850 to indicate whether the current page structure entry stored in the page structure cache is a 2MB superpage structure entry or a 1GB superpage structure entry. This allows the remapping processing unit to search the PDE cache and perform virtual address translation after the second remapping request is sent, improving translation efficiency.

[0115] Figure 9 This is a schematic diagram illustrating a fast cache search method 900 according to an embodiment of the present disclosure, and an apparatus for fast cache search, wherein the apparatus may be an address remapping unit. In step S905, the address remapping unit adds a PS field to the page structure cache to indicate that the current page structure entry stored in the page structure cache is a 2MB superpage structure entry or a 1GB superpage structure entry, wherein the PS field consists of one bit. A bit of 0 indicates that the current page structure entry is the 1GB superpage structure entry, and a bit of 1 indicates that the current page structure entry is the 2MB superpage structure entry.

[0116] In summary, the method and address mapping unit for remapping virtual addresses to physical addresses proposed in this disclosure provide each endpoint device with a separate remapping request interface, thereby reducing mutual interference between endpoint devices. Furthermore, since the remapping processing unit implements four layers of parallel processing units and the reordering control unit implements eight layers of miss queue processing units, the address mapping unit can process one remapping request in each consecutive cycle (T) when a cache hit occurs, improving the efficiency of address remapping. In addition, this disclosure also mentions a method and apparatus for fast cache searching, improving upon current cache structures. A bit is added to the context cache to indicate whether the current context entry is a context entry or an extended context entry. Furthermore, this disclosure implements a cache structure applicable to various page structure entries, and adds a bit to the page structure cache to indicate whether the current page structure entry is a 2MB superpage structure entry or a 1GB superpage structure entry, simplifying the search process and improving the cache hit rate.

[0117] For the embodiments described in this disclosure, the following describes exemplary operating environments in which embodiments of this disclosure can be implemented. See details. Figure 10 , Figure 10 The illustration shows an exemplary operating environment for implementing embodiments of the present disclosure, which can generally be considered as computing device 1000. Computing device 1000 is merely one example of a suitable computing environment and is not intended to imply any limitation on the use or scope of the present disclosure. Computing device 1000 should also not be construed as having any dependency or requirement in relation to any or all of the elements shown.

[0118] This disclosure can be executed using instructions on a computer or machine. These instructions can be computer-executable instructions for program modules, which are executed by a computer or other machine, such as a personal digital assistant or other portable device. Generally, program modules include routines, programs, objects, components, data structures, etc., and a program module refers to program code that performs a specific task or implements a specific abstract data type. This disclosure can be implemented in various system configurations, including portable devices, consumer electronics, general-purpose computers, and more specialized computing devices. This disclosure can also be implemented in distributed computing environments, processing devices connected by communication networks.

[0119] Please refer to Figure 10 The computing device 1000 includes a bus 1010, a memory 1012, one or more processors 1014, one or more display elements 1016, input / output (I / O) ports 1018, input / output (I / O) elements 1020, and a power supply 1022, which are directly or indirectly coupled to the following devices. The bus 1010 may be an element of one or more buses (e.g., an address bus, a data bus, or a combination thereof). Although Figure 10For simplicity, the various blocks are shown as lines. In reality, the boundaries between the various elements are not specific. For example, the presentation elements of the display device can be regarded as I / O elements; the processor may have memory.

[0120] The computing device 1000 generally includes various computer-readable media. Computer-readable media can be any available medium accessible to the computing device 1000, including volatile and non-volatile media, removable and non-removable media. For example, but not limited to, computer-readable media can include computer storage media and communication media. Computer-readable media also includes volatile and non-volatile media, removable and non-removable media implemented in any method or technique for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), electronically eraseable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical disc storage devices, magnetic disks, magnetic disks, magnetic storage devices or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to the computing device 1000. Computer storage media themselves do not contain signals.

[0121] Communication media generally contain computer-readable instructions, data structures, program modules, or other data in the form of modular data signals, such as carrier waves or other transmission mechanisms, and include any information transmission medium. The term "modular data signal" refers to a signal having one or more sets of features or modified in a manner that encodes information in the signal. For example, but not limited to, communication media include wired media such as wired networks or direct wired connections, and wireless media such as audio, radio frequency, infrared, and other wireless media. Combinations of the above media are included within the scope of computer-readable media.

[0122] Memory 1012 includes a computer storage medium in the form of volatile and non-volatile memory. The memory may be removable, non-removable, or a combination of both. Exemplary hardware devices include solid-state memory, hard disk drives, optical disk drives, etc. In the first embodiment, system management memory is located in memory 1012.

[0123] The computing device 1000 includes one or more processors 1014 that read data from entities such as memory 1012 or I / O elements 1020. A display element 1016 displays data instructions to a user or other device. Exemplary display elements include display devices, speakers, printing elements, vibrating elements, etc.

[0124] I / O port 1018 allows computing device 1000 to be logically connected to other devices including I / O element 1020, some of which are built-in. Exemplary elements include microphones, joysticks, game consoles, dish satellite receivers, scanners, printers, wireless devices, etc. I / O element 1020 provides a Natural User Interface (NUI) for processing user-generated gestures, voice, or other physiological inputs. In some examples, this input may be transmitted to a suitable network element for further processing. The NUI can implement any combination of speech recognition, touch and stylus recognition, facial recognition, biometrics, gesture recognition on and near the screen, air gestures, head and eye tracking, and touch recognition associated with the display on computing device 1000. Computing device 1000 may be equipped with a depth camera, such as a stereo camera system, an infrared camera system, an RGB camera system, and combinations thereof, to detect and recognize gestures. Additionally, computing device 1000 may be equipped with an accelerometer or gyroscope to detect motion. The output of the accelerometer or gyroscope can be provided to the computing device 1000 display to present immersive augmented reality or virtual reality.

[0125] Furthermore, the processor 1014 in the computing device 1000 can also execute programs and instructions in the memory 1012 to perform the actions and steps described in the above embodiments, or other content described in the specification.

[0126] Any specific order or hierarchical arrangement of steps in the procedures disclosed herein is merely illustrative. It should be understood, based on design preferences, that any specific order or hierarchical arrangement of steps in the procedures can be rearranged within the scope of this document. The accompanying method claims present elements of various steps in an exemplary order and should therefore not be limited to any particular order or hierarchy shown herein.

[0127] The use of ordinal numbers such as "first," "second," and "third" to modify elements in the claims does not imply any priority, order of precedence, sequence of elements, or order of steps performed by the method, but is merely used as an identifier to distinguish different elements with the same name (but different ordinal numbers).

[0128] Although this disclosure has been made above with examples of implementation, it is not intended to limit this application. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this application shall be determined by the scope defined in the appended claims.

Claims

1. A method for remapping a virtual address to a physical address in an address mapping unit, comprising: receiving, by a remap processing unit of the address mapping unit, a remap request, decoding the remap request, and determining whether the remap request is a direct memory access remap request; when the remap request is the direct memory access remap request, performing, by the remap processing unit, a remap procedure that translates a virtual address corresponding to the remap request to a physical address; when the remap processing unit determines that the remap request is invalid, transmitting, by the remap processing unit, an error message to an error message control unit to report that the remap request is invalid; and when the remap request is not the direct memory access remap request, transmitting, by the remap processing unit, an interrupt result to an output result unit to discard the remap request, when the remap request is the direct memory access remap request, the method further comprising: issuing, by the remap processing unit, a search command to a cache control logic unit; wherein when the cache control logic unit completes the search of the virtual address, issuing a cache hit signal of the virtual address to the output result unit and performing the remap procedure, or issuing a cache miss signal of the virtual address to a reordering control unit; when the reordering control unit receives the cache miss signal transmitted by the remap processing unit, issuing, by the reordering control unit, a read request to a memory; receiving, by the reordering control unit, data transmitted by the memory, and determining whether the data includes an error message; and when the data includes the error message, discarding, by the reordering control unit, the remap request, and transmitting the error message to the error message control unit to report that the remap request is invalid.

2. The method of claim 1, further comprising: receiving, by a remap request interface of the address mapping unit, the remap request transmitted by an endpoint device; and receiving, by an arbiter of the address mapping unit, the remap request transmitted by the remap request interface, and transmitting the remap request to the remap processing unit.

3. The method of claim 1, wherein when the error message control unit receives the error message, recording the error message to an error record register or a resident error log in a memory, and transmitting an interrupt signal to a processor.

4. The method of claim 1, further comprising: when the remap processing unit determines that the remap request is an interrupt request, interrupting, by the remap processing unit, the remap procedure.

5. The method of claim 1, further comprising: ​ ​ receiving, by an upstream stream arbiter of the address mapping unit, the remap request from the remap processing unit, the message signal interrupt from the error information control unit, the read request from the reordering control unit, and the page request or invalidation request from the page request and invalidation control logic unit; and sequentially transmitting, by the upstream stream arbiter, the remap request, the message signal interrupt, the read request, and the page request or invalidation request to the memory or processor via an upstream stream control interface.

6. The method of claim 1, wherein when the data does not include the error information, issuing, by the reordering control unit, an update command to update the cache control logic unit.

7. The method of claim 6, wherein the update command has a higher priority than the search command.

8. The method for remapping virtual addresses to physical addresses as recited in claim 1, wherein said cache control logic comprises: context cache, process address space identifier cache, input / output address translation translation lookaside buffer cache, level 5 page table walk cache, level 4 page table walk cache, page directory pointer table entry cache, page directory table entry cache, and interrupt remap table entry cache.

9. The method of claim 1, further comprising: receiving, by a physical address output interface of the address mapping unit, the physical address transmitted by the remap processing unit and transmitting a remap response including the physical address to an endpoint device.

10. The method of claim 1, further comprising: receiving, by a page request and invalidation control logic unit of the address mapping unit, a page request or invalidation request for a page via a page request and invalidation control interface; determining, by the page request and invalidation control logic unit, whether the page request or the invalidation request includes error information; and when the page request or the invalidation request includes the error information, transmitting, by the page request and invalidation control logic unit, the error information to an error information control unit to report that the page request or the invalidation request is erroneous.

11. The method of claim 10, further comprising: issuing, by the page request and invalidation control logic unit, a page search command to a cache control logic unit; wherein when the cache control logic unit completes the search for the page, issuing a cache hit signal or a cache miss signal for the page to the page request and invalidation control logic unit; and when the page request and invalidation control logic unit receives the cache miss signal, transmitting the page request carrying the cache miss signal to one of a plurality of miss queue processing units of a reordering control unit.

12. The method of claim 11, wherein when the reordering control unit receives the page request, the method further comprises: issuing, by the reordering control unit, a read request to a memory to perform a page walk; receiving, by the reordering control unit, data transmitted from the memory, and determining whether the data includes error information; and when the data includes the error information, discarding, by the reordering control unit, the page request and transmitting the error information to an error information control unit to report the page request as erroneous.

13. The method of claim 12, further comprising: when the data does not include the error information, issuing, by the reordering control unit, an update command to update the cache control logic unit.

14. An address remapping unit, comprising: a remapping processing unit including four layers of parallel processing units, wherein a first processing unit of the processing units receives a remapping request, decodes the remapping request, and determines whether the remapping request is a direct memory access remapping request; and when the remapping request is the direct memory access remapping request, performing a remapping procedure of translating a virtual address corresponding to the remapping request to a physical address; wherein when the remapping processing unit determines that the remapping request is erroneous, the remapping processing unit further performs: transmitting error information to an error information control unit to report the remapping request as erroneous; and transmitting an interrupt result to an output result unit to discard the remapping request, wherein when the first processing unit determines that the remapping request is the direct memory access remapping request, the first processing unit further performs: issuing a search command to a cache control logic unit; wherein when the cache control logic unit completes a search of the virtual address, the cache control logic unit issues a cache hit signal of the virtual address to the output result unit and performs the remapping procedure, or issues a cache miss signal of the virtual address to a reordering control unit; wherein the reordering control unit further comprises: a miss queue processing unit; wherein when the reordering control unit receives the cache miss signal transmitted from the remapping processing unit, the reordering control unit further performs: issuing a read request to a memory; receiving data transmitted from the memory, and determining whether the data includes error information; and when the data includes the error information, discarding the remapping request and transmitting the error information to the error information control unit to report the remapping request as erroneous.

15. The address remapping unit of claim 14, further comprising: a remapping request interface receiving the remapping request transmitted from an endpoint device; and an arbiter coupled to the remapping request interface and the remapping processing unit, receiving the remapping request transmitted from the remapping request interface, and transmitting the remapping request to the remapping processing unit.

16. The address remapping unit of claim 14, wherein when the error information control unit receives the error information, the error information control unit records the error information to an error record register or a resident error log in a memory, and transmits an interrupt signal to a processor.

17. The address remapping unit of claim 14, wherein said remapping processing unit interrupts said remapping procedure when said remapping processing unit determines that said remapping request is an interrupt request.

18. The address remapping unit of claim 14, further comprising: an upstream stream arbiter coupled to said remapping processing unit, said error information control unit, said reordering control unit, and said page request and invalidation control logic unit, performing: receiving said remapping request from said remapping processing unit, an error signal interrupt from said error information control unit, said read request from said reordering control unit, and a page request or an invalidation request from said page request and invalidation control logic unit; and sequentially transmitting said remapping request, said error signal interrupt, said read request, and said page request or said invalidation request to said memory or processor via an upstream stream control interface.

19. The address remapping unit of claim 14, wherein said reordering control unit further performs: issuing an update command to update said cache control logic unit when said data does not include said error information.

20. The address remapping unit of claim 19, wherein said update command has a higher priority than said search command. a context cache, a process address space identifier cache, an input / output address translation translation lookaside buffer cache, a level 5 page map cache, a level 4 page map cache, a page directory pointer table entry cache, a page directory table entry cache, and an interrupt remapping table entry cache.

21. The address remapping unit of claim 14, wherein said cache control logic unit comprises:

22. The address remapping unit of claim 14, further comprising: a physical address output interface coupled to said remapping processing unit, receiving said physical address transmitted by said remapping processing unit, and transmitting a remapping response including said physical address to an endpoint device.

23. The address remapping unit of claim 14, further comprising: a page request and invalidation control logic unit performing: receiving a page request or an invalidation request for a page via a page request and invalidation control interface; determining whether said page request or said invalidation request includes error information; and transmitting said error information to said error information control unit to report an error in said page request or said invalidation request when said page request or said invalidation request includes said error information.

24. The address remapping unit of claim 23, wherein said page request and invalidation control logic unit further performs: issuing a page search command to said cache control logic unit; wherein said cache control logic unit issues a cache hit signal or a cache miss signal to said page request and invalidation control logic unit when said cache control logic unit completes said page search; and transmitting said page request carrying said cache miss signal to one of said multi-level miss queue processing units of said reordering control unit when said page request and invalidation control logic unit receives said cache miss signal.

25. The address remapping unit of claim 24, wherein said reordering control unit further performs: ​ ​ issuing a read request to a memory for a page walk; receiving data transmitted from the memory and determining whether the data includes error information; and when the data includes the error information, discarding the page request and transmitting the error information to an error information control unit to report the error in the page request.

26. The address remapping unit of claim 25, wherein when the data does not include the error information, the reordering control unit further performs: issuing an update command to update the cache control logic unit.

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