Method for forming a semiconductor structure

Abstract

The present invention discloses a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region, each of the first and second regions having at least one opening within the substrate, the opening containing a coating, wherein the thickness of the coating in the first region is less than that of the coating in the second region; introducing an etching gas, a deposition gas, and a dilution gas into the surface of the coating to treat the coating; the dilution gas is used to promote a deposition rate of a polymer in the opening of the first region that is greater than the deposition rate on the substrate surface, thereby reducing the thickness difference between the coating in the first and second regions. The method can reduce the thickness difference between the coatings in the first and second regions.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a method for forming a semiconductor structure. Background Art

[0002] Driven by Moore's Law, semiconductor technology is rapidly advancing to nodes below 10nm. Plasma etching is a key technical constraint to this development. The bottom anti-reflective coating (BARC) layer (BARC) applied beneath the photoresist and the corresponding plasma etching process are crucial steps in achieving small dimensions, as it is a common approach for area-selective processes such as ion implantation. However, due to the transition from liquid to solid during the application process, variations in the BARC thickness after drying often occur due to varying pattern distribution or size.

[0003] This requires a coating planarization process to solve this problem. Traditional chemical mechanical polishing methods can only solve the problem of uneven surface coating thickness, but cannot address the different depths of recesses within small-sized structures.

[0004] In dry etching, thickness variation is often controlled by varying pattern size or opening ratios, using a combination of process parameters such as gas type, gas flow rate, pressure, and power. However, conventional process control methods have limited ability to address coating thickness variation and cannot completely eliminate it when the thickness variation is severe. Furthermore, their universality is limited, and even slight changes in pattern morphology or size can require readjustment of multiple parameters, or even lead to failure. Summary of the Invention

[0005] The purpose of the present invention is to solve the problem of thickness difference caused by coating during the formation of semiconductor structures, especially the problem of coating thickness difference caused by different surrounding environments when the pattern size and number are the same.

[0006] In order to achieve the above object, the present invention provides a method for forming a semiconductor structure, comprising:

[0007] Providing a substrate, the substrate comprising a first region and a second region, the first region and the second region respectively having at least one opening in the substrate, the opening having a coating therein, wherein the thickness of the coating in the first region is less than the thickness of the coating in the second region;

[0008] The coating is treated by introducing etching gas, deposition gas and dilution gas into the surface of the coating, wherein the etching gas is used to consume the coating, and the deposition gas is used to form a polymer deposition; the dilution gas is used to promote the deposition rate of the polymer in the first zone opening to be greater than the deposition rate on the substrate surface, so as to reduce the thickness difference between the first zone coating and the second zone coating.

[0009] Optionally, the width of the opening of the first region is no more than 30 nm.

[0010] Optionally, the etching rate of the etching gas on the coating on the substrate surface is greater than the etching rate of the coating in the opening, and the deposition rate of the deposition gas on the substrate surface is less than the deposition rate in the opening.

[0011] Optionally, after the coating is treated by introducing etching gas and deposition gas into the surface of the coating, the thickness of the coating in the first area is equal to the thickness of the coating in the second area.

[0012] Optionally, the opening size of the first area is larger than the opening size of the second area. The opening size refers to the width size.

[0013] Optionally, the opening size of the first zone is equal to the opening size of the second zone, and the number of openings in the first zone is greater than the number of openings in the second zone.

[0014] Optionally, the opening size of the first zone is equal to the opening size of the second zone, the number of openings in the first zone is equal to the number of openings in the second zone, and the environment around the openings in the first zone and the second zone makes the thickness of the coating in the first zone smaller than the thickness of the coating in the second zone.

[0015] Optionally, the coating is a bottom anti-reflection layer.

[0016] Optionally, the etching gas includes: NH3, or N2 and H2, or N2 and O2.

[0017] Optionally, the deposition gas includes at least one of the hydrocarbon small molecule gases of C1 to C5.

[0018] Optionally, the deposition gas is selected from at least one of CH4, C2H6, and C2H4.

[0019] Optionally, the volume ratio of the etching gas to the deposition gas is 1:1.5 to 1:3.

[0020] Optionally, the volume of the dilution gas is 35%-65% of the total volume of the etching gas and the deposition gas.

[0021] Optionally, the dilution gas includes: Ar and / or He.

[0022] Optionally, the flow rate of Ar is 100 sccm to 500 sccm.

[0023] Optionally, process conditions for treating the coating by introducing etching gas and deposition gas into the surface of the coating include: pressure of 60mT to 120mT, radio frequency (RF) of high frequency, and power of 200W to 600W.

[0024] Optionally, the coatings in the first and second zones do not fill the openings or both fill the openings; or the coating in the first zone fills the openings in the first zone, and the coating in the second zone does not fill the openings in the second zone; or the coating in the first zone does not fill the openings in the first zone, and the coating in the second zone fills the openings in the second zone.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the size of the opening of the substrate is relatively small, and there is a coating in the opening. Although the thickness of the first coating is less than the thickness of the coating in the second area, the ratio of the etching gas and the deposition gas can be adjusted, and the dilution gas can be used to cause the deposition rate of the polymer in the opening of the first area to be greater than the deposition rate on the substrate surface. Therefore, it is beneficial to reduce the thickness difference between the coatings in the first area and the second area. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The present invention is a flow chart of a method for forming a semiconductor structure.

[0028] Figure 2 The figure is a schematic diagram of the principle of a method for forming a semiconductor structure of the present invention.

[0029] Figure 3 Schematic diagram of the structure of a semiconductor structure before and after coating treatment according to an embodiment of the present invention.

[0030] Figure 4 Schematic diagram of the structure of a semiconductor structure before and after coating treatment according to another embodiment of the present invention.

[0031] Figure 5 This is a schematic structural diagram of a semiconductor structure before and after coating treatment according to another embodiment of the present invention.

[0032] Figure 6 This is a schematic structural diagram of a semiconductor structure before and after coating treatment according to another embodiment of the present invention.

[0033] Figure 7 Schematic diagram of the structure of a semiconductor structure before and after coating treatment due to different pattern sizes.

[0034] Figure 8 Schematic diagram of the structure of a semiconductor structure with the same opening size but different opening numbers before and after coating treatment.

[0035] Figure 9 Schematic diagram of the structure of a semiconductor structure with the same pattern size but different surrounding environments before and after coating treatment.

[0036] Reference numerals:

[0037] Base 10

[0038] District 11

[0039] District 2 12

[0040] First opening 111

[0041] Second opening 121

[0042] Coating 20

[0043] Depression 30. DETAILED DESCRIPTION

[0044] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0045] In the description of the present invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0046] like Figure 1 As shown, the planarization process for treating coating thickness differences of the present invention comprises the following steps:

[0047] S1, providing a substrate, the substrate comprising a first region and a second region, the first region and the second region each having at least one opening therein, the opening having a coating therein, wherein a thickness of the coating in the first region is less than a thickness of the coating in the second region;

[0048] S2, introducing etching gas, deposition gas and dilution gas into the surface of the coating to treat the coating, wherein the etching gas is used to consume the coating, the deposition gas is used to form a polymer deposition, and the dilution gas is used to promote the deposition rate of the polymer in the first zone opening to be greater than the deposition rate on the substrate surface, so as to reduce the thickness difference between the first zone coating and the second zone coating.

[0049] The method for forming a semiconductor structure provided by the present invention has a reaction mechanism as follows: Figure 2 As shown, a substrate 10 of a semiconductor structure to be etched is placed in an etching chamber and has a coating 20, such as a BARC coating, and a gas mixture (C x H y N z , x, y, and z are positive numbers) and a dilution gas. An etching gas, such as NH3, consumes the BARC coating; a deposition gas, such as CH4, serves as a polymer source to form polymer deposition. A dilution gas, such as Ar, acts as a dilution gas to ensure uniform polymer deposition and to generate positive Ar ions, which are directional and promote faster polymer deposition in small structures. The etchant NH* provided by the NH3 etching gas reacts with the BARC to form small hydrocarbon or carbon-nitrogen molecules, which are then extracted, achieving BARC etching. The deposition gas, CH4, provides hydrocarbon radicals or ions, which react with the BARC material to form larger molecular weight polymers that are deposited, achieving BARC deposition. These two processes (etching and deposition) gradually reach equilibrium. When the NH3 ratio in the etching gas is high, the BARC coating is consumed faster than the polymer deposition, resulting in BARC etching and reduced BARC coating thickness. When the CH4 ratio in the deposition gas is high, polymer deposition is faster than the BARC coating consumption, resulting in polymer deposition, ultimately leading to increasing polymer deposition and thicker BARC coatings.

[0050] Specifically, the present invention discovered that the equilibrium process of etching and deposition in small-scale structures differs from that of surface BARC. Due to steric hindrance, etching gas radicals are less likely to enter small-scale structures. However, when hydrocarbon radicals or ions reach a certain concentration in small-scale structures, they are less likely to form small gas molecules that are extracted and more likely to aggregate and deposit into large polymers. In other words, for the same ratio of mixed process gases, the deposition rate in small-scale structures, such as openings, is greater than that on the substrate surface, and the etching rate of the BARC coating is lower than that of the BARC coating on the substrate surface.

[0051] In this embodiment, the volume ratio of the etching gas to the deposition gas is 1:1.5 to 1:3. The significance of selecting the volume ratio is that if the etching gas is too little, the result of the balance between etching and deposition is faster deposition on the coating surface and in small-sized structures; if the etching gas is too much, the result of the balance between etching and deposition is faster etching on the coating surface and in small-sized structures.

[0052] By utilizing the above principles, the present invention can simultaneously achieve polymer deposition in small-sized structures and surface BARC etching by regulating the process (such as the ratio of etching gas to deposition gas); or, the top surface BARC etching is faster and the small-sized structure is slower; or the polymer deposition is faster in the small-sized structure and slower on the surface, so as to solve the problem of thickness difference between the first zone coating and the second zone coating.

[0053] The etching method of the present invention can also be used for etching other organic coatings of semiconductor structures containing small-scale structures.

[0054] The etching gas includes NH 3 , or N 2 and H 2 , or N 2 and O 2 . In particular, the etching gas is used to etch an organic BARC coating.

[0055] The deposition gas is used to form polymer macromolecules on the surface of the organic coating, and can be selected from at least one of the C1-C5 hydrocarbon small molecule gases; for example, at least one of CH4, C2H6, and C2H4.

[0056] In some embodiments, in order to achieve more uniform deposition of the polymer and promote faster deposition in small-sized structures, the volume of the dilution gas is 35%-65% of the total volume of the etching gas and the deposition gas.

[0057] In some embodiments, the dilution gas includes Ar and / or He, wherein the flow rate of the dilution gas is 100 sccm to 500 sccm.

[0058] The process conditions for treating the coating of the present invention include: a pressure of 60mT to 120mT, a radio frequency (RF) of high frequency (for example, 60Mhz may be selected), and a power of 200W to 600W.

[0059] The following describes in detail how to use the Figure 2 The reaction mechanism reduces the thickness difference between the first and second regions of the coating for different types of semiconductor structures:

[0060] Example 1

[0061] like Figure 3As shown, a semiconductor structure is provided in a plasma etching chamber: the substrate 10 in the first region 11 is not filled with a BARC coating, and the BARC coating in the first opening 111 is not fully filled, having a recess 30. The dimension H of the recess represents the distance from the coating surface in the opening to the surface of the opening top flush with the substrate, H = 60A; the surface of the substrate 10 in the second region 12 and the second opening 121 are fully filled with a BARC coating 20, and the thickness of the surface BARC coating is 770A.

[0062] Under conditions of 60 MHz RF frequency, 60 mT pressure, and 200 W power, treatment was performed using Mode I: 100 units of NH3, 200 units of CH4, and 250 units of Ar were introduced to treat the coating on the semiconductor structure. After 200 seconds, measurements showed that the thickness of the BARC coating on the substrate surface in the second region 12 had decreased to 170 Å, with a surface etch rate (ER) of 3.0 A / s. The BARC coating recess 30 within the first opening 111 of the first region 11 had a size of 70 Å, with an etch rate within the opening (ER) of 0.05 A / s.

[0063] It can be seen that under the process conditions of Example 1, after the etching and deposition processes reach a balance, both the substrate surface and the small-scale structure are etched, among which the BARC coating on the substrate surface is etched faster. At the same time, the BARC coating in the opening is etched very slowly, thereby reducing the thickness difference between the coatings in the first area 11 and the second area 12.

[0064] Example 2

[0065] like Figure 4 As shown, a semiconductor structure is provided in a plasma etching chamber: the BARC coating is not filled on the substrate 10 in the first region 11, and the BARC coating in the first opening 111 is not filled, having a recess 30, and the size H of the recess is 60A; the surface of the substrate 10 in the second region 12 and the second opening 121 are filled with the BARC coating 20, and the thickness of the BARC coating on the surface is 770A.

[0066] The semiconductor structure's coating was treated using Mode II at 60 MHz, 60 mT pressure, and 200 W power. The NH3 usage was reduced, and the process gas ratio was adjusted to 85 units of NH3, 200 units of CH4, and 250 units of Ar. After 360 seconds, the thickness of the BARC coating on the surface was reduced to 170 Å, with a surface etch rate (ER) of 1.7 A / s. The BARC coating recess within the first opening 111 was 30 Å, indicating that the BARC coating within the first opening 111 was not etched away but rather slowly deposited. The polymer deposition rate was 0.08 A / s.

[0067] It can be seen that under the process conditions of Example 2, the BARC coating on the substrate surface is undergoing BARC etching, and at the same time, the BARC coating in the first opening 111 is slowly depositing a macromolecular polymer.

[0068] Comparing the above-mentioned Example 1 with Example 2, it can be seen that the process can be controlled in two different modes (different equilibrium states) by adjusting the NH3 / CH4 gas ratio:

[0069] Mode I (eg, Example 1): The BARC coating on the substrate surface is etched faster, while the BARC coating inside and above the small-sized structures is etched slower. The height difference between the two gradually decreases, and after a certain period of time, the thickness difference is greatly reduced.

[0070] Mode II (e.g., Example 2): BARC etching is performed on the substrate surface, and at the same time, polymer deposition is performed in the small-sized structure. When the depression in the small-sized structure reaches the hole, the BARC etching and polymer deposition reach a balance at the hole, with almost no depression, so that the thickness difference between the first zone coating and the second zone coating is reduced to zero.

[0071] Therefore, for the case where one pattern is a surface BARC and the other is a BARC within a small scale structure, a significant reduction in thickness difference can be achieved using both Mode I and Mode II, with Mode II reducing the thickness difference of the coating to zero.

[0072] Example 3

[0073] like Figure 5 As shown, a semiconductor structure is provided in a plasma etching chamber: the BARC coating is not filled on the substrate 10 in the first region 11, the BARC coating in the first opening 111 is not fully filled, and a recess 30 is formed, and the size H1 of the recess is 330A; the BARC coating is not filled on the surface of the substrate 10 in the second region 12, the BARC coating in the second opening 121 is not fully filled, and a recess 30 is formed, and the size H2 of the recess is 140A.

[0074] Under conditions of 60 MHz RF frequency, 60 mT pressure, and 200 W power, Mode II treatment was performed: 66 units of NH3, 200 units of CH4, and 250 units of Ar were introduced to treat the coating on the semiconductor structure. After 360 seconds, inspection revealed that the size of the depressions in both the first and second openings had shrunk to 40 Å.

[0075] It can be seen that regardless of the depth of the BARC coating within the small-scale structure, under the process conditions of Example 3 (Mode II), the final polymer deposition and BARC etching reach a balance at the hole mouth, reducing the coating thickness difference between the two patterns to zero.

[0076] Therefore, when encountering a situation where two patterns of BARC coatings in a semiconductor structure with small-scale structures are encountered, but the coating thickness is different, that is, the BARC recess sizes of the two patterns are different, the NH3 / CH4 ratio must be adjusted to Mode II to solve the coating thickness difference.

[0077] Example 4

[0078] like Figure 6 As shown, a semiconductor structure is provided in a plasma etching chamber: a first region 11 of the substrate 10 and a first opening 111 are filled with a coating 20 having a thickness h1 of 570 Å; a second region 12 of the substrate 10 and a second opening 121 are filled with a coating 20 having a thickness h2 of 770 Å. The first region 11 has through holes (not shown) surrounding the substrate, while the second region 12 has no through holes surrounding the substrate.

[0079] Under conditions of 60 MHz RF frequency, 60 mT pressure, and 200 W power, treatment was performed using Mode I: 133 units of NH3, 200 units of CH4, and 200 units of Ar were introduced to treat the coating on the semiconductor structure. After 200 seconds, measurements showed that the thickness h1 of the substrate surface coating in the first region 11 had decreased to 170 Å, with an etch rate ER of 2.0 A / s. The thickness h2 of the substrate surface coating in the second region 12 had decreased to 170 Å, with an etch rate ER of 3.0 A / s.

[0080] It can be seen that under the process conditions of Example 4, after the etching and deposition processes reach equilibrium, both the first and second regions show etching, wherein the surface coating of the substrate in the first region is etched slower, while the surface coating of the substrate in the second region is etched faster. After a certain period of time, the surface thickness difference between the first and second regions is reduced to 0.

[0081] The sizes of the openings in the first and second zones are described in detail below:

[0082] Example 1

[0083] like Figure 7 As shown, a semiconductor structure includes a substrate 10, and the substrate includes a first area 11 and a second area 12. The first area 11 and the second area 12 each have at least one opening in the substrate. The size of the first opening 111 of the first area 11 is larger than the size of the second opening 121 of the second area 12, and the size refers to the opening width, which is a critical size. The width of the first opening 111 is not greater than 30nm. When the organic coating is applied to the semiconductor structure using conventional photolithography coating equipment, the thickness of the surface organic coating of the first area 11 is smaller than the thickness of the surface organic coating of the second area 12. Figure 2The reaction mechanism is used to regulate the mutual ratio of the etching gas, the deposition gas and the slow-release gas, and the planarization treatment is performed through the mode I of the present invention, that is, the etching rate of the surface organic coating of the first area 11 is lower than the etching rate of the surface organic coating of the second area 12. As time goes by, the coating thicknesses of the two gradually become consistent, solving the problem of uneven thickness.

[0084] Example 2

[0085] like Figure 8 As shown, a semiconductor structure comprises a substrate 10, which includes a first area 11 and a second area 12. The first area 11 and the second area 12 each have at least one opening in the substrate 10. The size of the first opening 111 of the first area 11 is the same as the size of the second opening 121 of the second area 12, but the number of the first openings 111 of the first area 11 is greater than the number of the second openings 121 of the second area 12. When the organic coating is applied to the semiconductor structure using conventional photolithography coating equipment, the thickness of the surface organic coating of the first area 11 is less than the thickness of the surface organic coating of the second area 12. The mutual ratio of the etching gas, the deposition gas and the slow-release gas is regulated, and a flattening treatment is performed through mode I of the present invention, that is, the etching rate of the surface organic coating of the first area 11 is lower than the etching rate of the surface organic coating of the second area 12. As time goes by, the thickness of the coatings of the two gradually becomes consistent, thereby solving the problem of uneven thickness.

[0086] Example 3

[0087] like Figure 9 As shown, a semiconductor structure includes a substrate 10, which includes a first region 11 and a second region 12. The first region 11 has at least one first opening 111, and the second region 12 has at least one second opening 121 in the substrate. The second opening 121 has the same opening size and number as the first opening 111, but the surrounding environment is different: for example, a through hole with a larger aperture than that around the second opening 121 is provided around the first opening 111 (not shown in the figure). An organic coating is applied within the opening and on the surface of the substrate using existing photolithography coating equipment. The thickness of the surface coating formed in the first region 11 is less than that of the surface coating in the second region 12. According to process requirements, a pattern layer (PR) may also be provided on the coating. The mutual ratio of etching gas, deposition gas and slow-release gas is regulated, and coating treatment is performed through mode I and mode II of the present invention: mode I is first adopted to make the etching rate of the surface organic coating of the first zone 11 lower than the etching rate of the surface organic coating of the second zone 12. As time goes by, the coating thickness of the two gradually becomes consistent and gradually decreases; when the coating thickness on the substrate surface is close to 100A, mode II is adopted to etch the coating on the substrate surface, and at the same time, slowly deposit it in the opening, and finally reach equilibrium at the hole mouth.

[0088] In summary, the process gas selected in the present invention for planarizing the surface of an organic coating achieves unexpected technical benefits by adjusting the ratio of etching gas to deposition gas and dilution gas. This allows the etching gas to etch the coating on the substrate surface at a higher rate than the coating within the opening, while the deposition gas to deposit at a lower rate within the opening. This minimizes the thickness difference between the first and second coating zones, reduces depressions within the opening, and completely resolves the thickness difference issue during semiconductor structure formation. This process is particularly suitable for planarizing small structures with opening widths of 30 nm or less.

[0089] Although the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description is not intended to limit the present invention. After reading the above description, various modifications and substitutions of the present invention will become apparent to those skilled in the art. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region, the first region and the second region respectively having at least one opening in the substrate, the opening having a coating therein, wherein the thickness of the coating in the first region is less than the thickness of the coating in the second region; Passing an etching gas, a deposition gas, and a dilution gas into the surface of the coating to treat the coating, wherein the etching gas is used to consume the coating, the deposition gas is used to form a polymer deposition, and the dilution gas is used to promote the deposition rate of the polymer in the first area opening to be greater than the deposition rate on the substrate surface, so as to reduce the thickness difference between the coating in the first area and the coating in the second area; The opening size of the first zone is equal to the opening size of the second zone, and the number of openings in the first zone is greater than or equal to the number of openings in the second zone.

2. The method for forming a semiconductor structure according to claim 1, wherein: The width of the opening of the first region is no greater than 30 nm.

3. The method for forming a semiconductor structure according to claim 1, wherein: The etching rate of the etching gas on the substrate surface coating is greater than the etching rate on the coating in the opening, and the deposition rate of the deposition gas on the substrate surface is less than the deposition rate in the opening.

4. The method for forming a semiconductor structure according to claim 1, wherein: After the coating is treated by introducing etching gas and deposition gas into the surface of the coating, the thickness of the coating in the first area is equal to the thickness of the coating in the second area.

5. The method for forming a semiconductor structure according to claim 1, wherein: The number of openings in the first zone is equal to the number of openings in the second zone, and the environment around the openings in the first zone and the second zone makes the thickness of the coating in the first zone smaller than the thickness of the coating in the second zone.

6. The method for forming a semiconductor structure according to claim 1, wherein: The coating is a bottom anti-reflective layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The etching gas includes: NH3, or N2 and H2, or N2 and O2.

8. The method for forming a semiconductor structure according to claim 6, wherein: The deposition gas includes at least one of C1-C5 hydrocarbon small molecule gases.

9. The method for forming a semiconductor structure according to claim 8, wherein: The deposition gas is selected from at least one of CH4, C2H6 and C2H4.

10. The method for forming a semiconductor structure according to claim 1, wherein: The volume ratio of the etching gas to the deposition gas is 1:1.5 to 1:

3.

11. The method for forming a semiconductor structure according to claim 1, wherein: The volume of the dilution gas is 35%-65% of the total volume of the etching gas and the deposition gas.

12. The method for forming a semiconductor structure according to claim 11, wherein: The dilution gas includes: Ar and / or He.

13. The method for forming a semiconductor structure according to claim 11, wherein: The flow rate of the dilution gas is 100 sccm to 500 sccm.

14. The method for forming a semiconductor structure according to claim 1, wherein: The process conditions for treating the coating by introducing etching gas and deposition gas into the surface of the coating include: pressure of 60mT to 120mT, radio frequency of high frequency, and power of 200W to 600W.

15. The method for forming a semiconductor structure according to claim 1, wherein: The coatings in the first and second zones do not fill the openings or both fill the openings; or the coating in the first zone fills the openings in the first zone, and the coating in the second zone does not fill the openings in the second zone; or the coating in the first zone does not fill the openings in the first zone, and the coating in the second zone fills the openings in the second zone.

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