Semiconductor device and method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device comprises forming a metal bump on the first surface side of a semiconductor chip having a first surface and a second surface opposite to the first surface, arranging the metal bump on a pad provided on a wiring substrate, irradiating the metal bump with a first light from the second surface side of the semiconductor chip to melt the metal bump, then stopping or weakening the irradiation of the first light to allow the melted metal bump to fall below the solidification point, and irradiating the metal bump with a second light from the second surface side of the semiconductor chip while pressurizing the semiconductor chip toward the wiring substrate, then stopping or weakening the irradiation of the second light to allow the melted metal bump to fall below the solidification point.

Description

[0001] This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2020-123839, filed on July 20, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0003] A semiconductor package using a NAND flash memory as a semiconductor device is known. As an example of such a semiconductor package, there is a semiconductor package in which an IC chip (semiconductor chip) is mounted on pads provided on a wiring substrate by flip-chip bonding. Summary of the Invention

[0004] One embodiment realizes a highly reliable semiconductor device. Alternatively, a method for mounting an IC chip is provided that enables high-precision positioning for flip-chip bonding without using expensive equipment requiring high positioning accuracy, and also suppresses the effects of IC chip warpage.

[0005] A method for manufacturing a semiconductor device according to one embodiment comprises forming a metal bump on the first surface side of a semiconductor chip having a first surface and a second surface opposite to the first surface, placing the metal bump on a pad provided on a wiring substrate, irradiating the second surface side of the semiconductor chip with a first light to melt the metal bump, then stopping or weakening the irradiation with the first light to allow the melted metal bump to fall below its solidification point, and irradiating the second surface side of the semiconductor chip with a second light to melt the metal bump while pressurizing the semiconductor chip toward the wiring substrate, then stopping or weakening the irradiation with the second light to allow the melted metal bump to fall below its solidification point.

[0006] A semiconductor device according to one embodiment comprises: a semiconductor chip having a first metal bump and a second metal bump arranged on the outside of the first metal bump when viewed from above; and a wiring substrate having a first solder pad connected to the first metal bump and a second solder pad connected to the second metal bump, wherein a first compound layer containing the material of the first metal bump and the material of the first solder pad exists between the first metal bump and the first solder pad, and a second compound layer containing the material of the second metal bump and the material of the second solder pad exists between the second metal bump and the second solder pad, and the thickness of the first compound layer and the thickness of the second compound layer are different.

[0007] The above structure can realize a highly reliable semiconductor device. Alternatively, a method for mounting an IC chip can be provided that can achieve high-precision positioning for flip-chip bonding without using expensive equipment requiring high positioning accuracy, and can also suppress the effects of IC chip warping. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a cross-sectional view showing the overall structure of a semiconductor device according to one embodiment.

[0009] Figure 2 It is a plan view showing the overall structure of a semiconductor device according to one embodiment.

[0010] Figure 3 This is a cross-sectional view showing the structure of a semiconductor chip and a wiring board of a semiconductor device according to one embodiment.

[0011] Figure 4 This is a partially enlarged cross-sectional view showing a connection structure between a semiconductor chip and a wiring substrate in a semiconductor device according to one embodiment.

[0012] Figure 5 This is a cross-sectional view showing a wiring board of a semiconductor device according to one embodiment.

[0013] Figure 6 This is a cross-sectional view showing a semiconductor chip of a semiconductor device according to one embodiment.

[0014] Figure 7 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment.

[0015] Figure 8 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment.

[0016] Figure 9 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment.

[0017] Figure 10 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment.

[0018] Figure 11 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment.

[0019] Figure 12 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment.

[0020] Figure 13 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment.

[0021] Figure 14 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment.

[0022] Figure 15 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment.

[0023] Figure 16 This is a timing chart showing a method of connecting a metal bump and a pad by light irradiation in a method of manufacturing a semiconductor device according to one embodiment.

[0024] Figure 17 This is a timing chart showing a method of connecting a metal bump and a pad by light irradiation in a method of manufacturing a semiconductor device according to one embodiment.

[0025] Figure 18 This is a timing chart showing a method of connecting a metal bump and a pad by light irradiation in a method of manufacturing a semiconductor device according to one embodiment.

[0026] Figure 19 This is a timing chart showing a method of connecting a metal bump and a pad by light irradiation in a method of manufacturing a semiconductor device according to one embodiment.

[0027] Figure 20 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment.

[0028] Figure 21 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment.

[0029] Figure 22 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. DETAILED DESCRIPTION

[0030] Hereinafter, the semiconductor device of the present embodiment will be described in detail with reference to the accompanying drawings. In the following description, elements having substantially the same function and structure are given the same reference numerals or reference numerals with letters appended after the same reference numerals, and repeated descriptions are made only when necessary. The embodiments shown below illustrate the apparatus and method for concretizing the technical idea of the embodiment. The technical idea of the embodiment does not limit the material, shape, structure, configuration, etc. of the constituent components to the following manner. The technical idea of the embodiment can also be subject to various changes within the scope of the claims.

[0031] In various embodiments of the present invention, the direction from the wiring substrate toward the semiconductor chip is referred to as "up." Conversely, the direction from the semiconductor chip toward the wiring substrate is referred to as "down." Thus, although the terms "up" and "down" are used for ease of explanation, the wiring substrate and semiconductor chip may be arranged such that the vertical relationship is reversed from that shown. Furthermore, in the following description, for example, the term "semiconductor chip on wiring substrate" merely illustrates the vertical relationship between the wiring substrate and semiconductor chip as described above; other components may be arranged between the wiring substrate and semiconductor chip.

[0032] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes multiple combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0033] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0034] <First embodiment>

[0035] [Structure of Semiconductor Device 10]

[0036] Figure 1 It is a cross-sectional view showing the overall structure of a semiconductor device according to one embodiment. Figure 2 This is a top view showing the overall structure of a semiconductor device according to one embodiment. As semiconductor device 10 of this embodiment, an example of a semiconductor package using NAND flash memory is described, but the present invention is not limited to this structure. This embodiment can be applied to a device in which a semiconductor chip is mounted on a wiring substrate using flip-chip connection. Semiconductor device 10 includes a semiconductor chip 100, a wiring substrate 200, a spacer 300, a stacked memory chip 400, bonding wires 500, and a resin layer 600. The specific structures of semiconductor chip 100 and wiring substrate 200 will be described later.

[0037] The spacer 300 is bonded to the wiring substrate 200 via the insulating layer 301. Figure 2 As shown, the spacer 300 is provided on the periphery of the semiconductor chip 100 in a manner of surrounding the semiconductor chip 100. Figure 1As shown, the upper surface of the spacer 300 is located at approximately the same height as the upper surface of the semiconductor chip 100. Materials such as silicon, glass, ceramics, insulating substrates, and metal plates are used for the spacer 300. For example, DAF (die attach film) is used as the insulating layer 301. An organic film may be formed on the spacer 300 to improve the adhesion between the spacer 300 and the stacked memory chip 400. For the organic film and the insulating layer 301, a monomeric, composite, or laminated organic film such as polyimide resin, polyamide resin, epoxy resin, acrylic resin, phenolic resin, silicone resin, PBO (polybenzoxazole) resin, or benzocyclobutene resin may be used.

[0038] The stacked memory chip 400 is fixed to the semiconductor chip 100 and the spacer 300, respectively. The stacked memory chip 400 includes insulating layers 410 and 430 and memory cells 420. The insulating layer 410 is provided on the semiconductor chip 100 and the spacer 300, and the memory cells 420 and insulating layers 430 are alternately stacked on the insulating layer 410. In other words, the stacked memory chip 400 forms a three-dimensional memory cell array with a plurality of memory cells 420 arranged three-dimensionally. Furthermore, the memory cells 420 are stacked while being staggered, with the upper memory cell 420 partially exposing the lower memory cell 420. The insulating layers 410 and 430 are made of a single, composite, or stacked organic film such as polyimide resin, polyamide resin, epoxy resin, acrylic resin, phenolic resin, silicone resin, PBO (Poly Benz Oxazole) resin, or benzocyclobutene resin. The stacked memory chip 400 may vertically stack a plurality of memory cells 420 having through-silicon vias (TSVs) and interposers.

[0039] The bonding wires 500 electrically connect the connection pads (not shown) provided on the upper surface of the stacked memory chip 400 and the connection pads 201 of the wiring substrate 200, and connect the connection pads provided on the upper surface of the stacked memory chip 400 to each other. The resin layer 600 covers and protects the structure provided on the wiring substrate 200, including the semiconductor chip 100, the stacked memory chip 400, and the bonding wires 500. As the resin layer 600, a monomer, composite, or stacked organic material such as polyimide resin, polyamide resin, epoxy resin, acrylic resin, phenolic resin, silicone resin, PBO (Poly Benz Oxazole) resin, or benzocyclobutene resin is used. Figure 1The example shows a structure in which the stacked memory chip 400 is mounted on the wiring substrate 200 via a gasket, but the semiconductor device 10 can also be a structure in which the memory unit 420 is stacked on an FOD (Film on Device) structure using a flip-chip chip covered with resin.

[0040] Figure 3 This is a cross-sectional view showing the structure of a semiconductor chip and a wiring board of a semiconductor device according to one embodiment. Figure 4 This is a partially enlarged cross-sectional view showing a connection structure between a semiconductor chip and a wiring substrate in a semiconductor device according to one embodiment.

[0041] like Figure 3 and Figure 4 As shown, the semiconductor chip 100 has a first surface 101 and a second surface 102. The semiconductor chip 100 has a semiconductor substrate 110, a pad 120, and a metal bump 130. The pad 120 and the metal bump 130 are arranged on the first surface 101 side of the semiconductor chip 100. Functional components such as transistors, capacitors, and resistors are arranged on the first surface 101 side of the semiconductor chip 100. These functional components are interconnected by wiring. The wiring includes multiple conductive layers and multiple insulating layers, and the conductive layers adjacent to each other in the thickness direction of each layer are isolated by the insulating layer therebetween. Openings are provided in the insulating layer, and the conductive layers adjacent to each other in the thickness direction are connected at the openings.

[0042] An example of the thickness of semiconductor substrate 110 is 10 μm to 100 μm, or 20 μm to 70 μm. A bonding pad 120 is provided on the wiring exposed on the first surface 101 side of semiconductor chip 100. A metal bump 130 is provided on bonding pad 120. Bonding pad 120 is connected to bonding pad 240, described later, via metal bump 130. Metal bump 130 ensures electrical connection between the two bonding pads and a relative positional relationship between the two bonding pads.

[0043] As the semiconductor substrate 110, a silicon substrate, a gallium arsenide (GaAs) substrate, and a silicon carbide (SiC) substrate are used. As the pad 120, conductive materials such as copper (Cu), nickel (Ni), gold (Au), tin (Sn), silver (Ag), aluminum (Al), titanium (Ti), chromium (Cr), titanium nitride (TiN), chromium nitride (CrN), palladium (Pd), tungsten (W), tantalum (Ta), and molybdenum (Mo) are used. The pad 120 is a single layer, a stacked layer, or an alloy layer of the above materials. As the metal bump 130, a conductive material such as solder (an alloy with tin as the main component) is used. For example, it is a single layer, a stacked layer, or an alloy of Sn, Ag, Cu, Ni, Au, Pd, bismuth (Bi), indium (In), antimony (Sb), germanium (Ge), and cobalt (Co). However, these materials are just examples and are not limited to the above materials.

[0044] The wiring substrate 200 includes a core material 210, a wiring layer 220, an insulating layer 230, and a solder pad 240. An example of the thickness of the wiring substrate 200 is 30 μm to 1000 μm or 50 μm to 200 μm. The wiring layer 220 is provided above and below the core material 210. The insulating layer 230 is provided above the wiring layer 220. The wiring layer 220 includes a plurality of conductive layers 221 and a plurality of insulating layers 223. Adjacent conductive layers 221 in the thickness direction of each layer are isolated by the insulating layer 223 therebetween. The insulating layer 223 is provided with an opening 225, at which the adjacent conductive layers 221 in the thickness direction are connected. The solder pad 240 is connected to the conductive layer 221 closest to the semiconductor chip 100 among the plurality of conductive layers 221 included in the wiring layer 220. In addition, an underfill 250 is provided between the semiconductor chip 100 and the wiring substrate 200. An insulating layer 230 may be formed below the wiring substrate 200 , but is not shown. A pad 240 may also be formed below the wiring substrate 200 .

[0045] As the core material 210, insulating materials such as glass epoxy resin or ceramics (alumina type, AlN type) are used. As the conductive layer 221, conductive materials such as Cu, Al, Ti, W, Ta, Ag, Au, Mo, etc. are used. The conductive layer 221 is a single layer, a stacked layer, or an alloy layer of the above materials. As the insulating layers 223 and 230, inorganic insulating layers such as silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), aluminum nitride (AlN), or organic insulating layers such as polyimide resin, polyamide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, siloxane resin, phenolic resin, PBO (Poly Benz Oxazole) resin, benzocyclobutene resin are used. The insulating layers 223 and 230 are a single layer, a composite layer, or a stacked layer of the above materials. In addition, the insulating layer 230 is sometimes referred to as a solder resist. Conductive materials such as Cu, Ni, Au, Sn, Ag, Pd, Ti, Cr, Mo, TiN, and CrN can be used as pads 240. Pads 240 can be made of a single layer, a stacked layer, or an alloy layer of these materials. However, these materials are merely examples and are not limited to the above materials. Alternatively, a substrate based on silicon or glass can be used as the core material 210, as in the interposer.

[0046] [Method of Manufacturing Semiconductor Device 10]

[0047] use Figures 5 to 15 The manufacturing method of the semiconductor device 10 is described. In the following description, the conductive layer 221 and the insulating layer 223 of the wiring substrate 200 are omitted for convenience of description. Figure 5 As shown in FIG. 2 , a wiring substrate 200 is prepared. A pad 240 and an insulating layer 230 are provided above the core material 210. Figure 6 As shown, a semiconductor chip 100 is prepared. A solder pad 120 and a metal bump 130 are provided on the lower surface (first surface 101) of the semiconductor chip 100. Flux 140 is formed on the front end (lower end) of the metal bump 130. Semiconductor chip 100 is fixed to a handling member 700 of a mounting device. Flux 140 may also be formed on the solder pad 240.

[0048] like Figure 7 As shown, the semiconductor chip 100 is placed on the wiring substrate 200 in such a manner that the metal bumps 130 are in contact with the pads 240 or the solder 140 on the metal bumps 130 are in contact with the pads 240. Figure 7 In the embodiment, at least the pad 240 is in contact with the metal bump 130 or the pad 240 is in contact with the flux 140 on the metal bump 130 , so when the semiconductor chip 100 is arranged on the wiring substrate 200 , a calibration device and calibration method with relatively low accuracy can be used.

[0049] like Figure 8 As shown, first light 150 for melting metal bumps 130 is irradiated from the upper surface side (second surface 102 side) of semiconductor chip 100. Note that there are cases where first light 150 (or second light 160, described later) transmits through semiconductor substrate 110 and irradiates both pads 120 and metal bumps 130, and cases where first light 150 (or second light 160, described later) irradiates pads 120 but is mainly absorbed by pads 120 and does not irradiate metal bumps 130. For convenience of description, it is described as irradiating pads 120 and metal bumps 130 with first light 150 (or second light 160).

[0050] The irradiation conditions of the first light 150 are such that the temperature of the metal bump 130 exceeds the melting point of the metal bump 130 due to the heating based on the irradiation of the first light 150. When irradiating the first light 150, no other component that restricts the movement of the semiconductor chip 100 is provided on the second surface 102 side of the semiconductor chip 100. In this embodiment, a laser is used as the first light 150. The wavelength of the laser is greater than 600nm and less than 1300nm, greater than 750nm and less than 1200nm, or greater than 850nm and less than 1100nm. When the wavelength is less than 600nm, the absorption of light in the semiconductor chip increases, which may cause damage to the semiconductor chip. When the wavelength exceeds 1300nm, the actual energy decreases, so the temperature of the connection portion becomes less likely to rise. In addition, the irradiation time of the laser is greater than 0.1 seconds and less than 60 seconds, greater than 0.5 seconds and less than 30 seconds, or greater than 1 second and less than 15 seconds. If the time is less than 0.1 seconds, the temperature does not rise easily. If the time exceeds 60 seconds, there is a problem of increased throughput. By using the laser of the above wavelength as the first light 150, the energy of the laser can be suppressed from being absorbed by the semiconductor substrate 110, and the energy of the laser can be effectively used to heat the metal bump 130.

[0051] Furthermore, as long as the metal bump 130 is melted by the irradiation of the first light 150, light other than the aforementioned laser light can be used as the first light 150. For example, lamp light can also be used as the first light 150. Furthermore, the wavelength of the laser light used as the first light 150 is not limited to the wavelengths described above.

[0052] As described above, if the metal bumps 130 are melted by the first light 150, the metal bumps 130 exhibit fluidity, so the surface tension of the melted metal bumps 130 causes the semiconductor chip 100 to move to the appropriate position. Specifically, the semiconductor chip 100 moves to a position where the pads 120 of the semiconductor chip 100 face the pads 240 of the wiring substrate 200. In this way, the metal bumps 130 are melted by the first light 150, thereby performing self-adjusting positioning (self-calibration). In addition, it is not necessary for all of the multiple metal bumps 130 provided on the semiconductor chip 100 to be melted by the irradiation of the first light 150; it is sufficient that at least two or more of the multiple metal bumps 130 are melted. In addition, a portion of the flux 140 is volatilized by the irradiation of the first light 150.

[0053] After the above self-calibration is performed, Figure 9 As shown, the irradiation of the first light 150 is stopped or weakened. As the irradiation of the first light 150 is stopped or weakened, the metal bump 130 dissipates heat, which continues until the temperature of the molten metal bump 130 reaches or falls below the freezing point of the metal bump 130. As the temperature of the metal bump 130 falls below the freezing point, the molten metal bump 130 solidifies, and the position of the semiconductor chip 100 is fixed to the position moved to by the self-calibration described above. Furthermore, when the irradiation of the first light 150 is stopped or weakened, the output of the light source can be adjusted, and a shielding plate or attenuator can be placed in the optical path of the first light 150.

[0054] like Figure 10 As shown, a support member 310 is arranged on the second surface 102 side of the semiconductor chip 100. The support member 310 is a light-transmitting member. Specifically, the support member 310 is a member that allows at least the second light 160 described later to pass through. For example, glass, quartz, heat-resistant plastic, etc. can be used as the support member 310. In addition, the transmittance of the support member 310 for the wavelength of the second light 160 is greater than 80%, greater than 90%, or greater than 95%. If it is less than 80%, the temperature cannot be increased efficiently. The support member 310 contacts the second surface 102 of the semiconductor chip 100 and presses the semiconductor chip 100 toward the wiring substrate 200.

[0055] like Figure 11As shown, while the semiconductor chip 100 is pressurized by the support member 310, second light 160 is irradiated from the upper surface side (second surface 102 side) of the semiconductor chip 100, i.e., above the support member 310, to melt the metal bump 130. The irradiation conditions of the second light 160 are such that the temperature of the metal bump 130 exceeds the melting point of the metal bump 130 due to heating by the irradiation of the second light 160. In this embodiment, a laser is used as the second light 160. The wavelength of the laser is 600 nm to 1300 nm, 750 nm to 1200 nm, or 850 nm to 1100 nm. When the wavelength is less than 600 nm, the absorption of light within the semiconductor chip increases, which may cause damage to the semiconductor chip. When the wavelength exceeds 1300 nm, the actual energy decreases, so the temperature of the connection portion becomes less likely to rise. In addition, the irradiation time of the laser is 0.1 second to 60 seconds, 0.5 second to 30 seconds, or 1 second to 15 seconds. If the time is less than 0.1 seconds, the temperature does not rise easily. If the time exceeds 60 seconds, the throughput becomes slow. By using laser light of the above wavelength as the second light 160, it is possible to suppress the absorption of the laser energy by the semiconductor substrate 110, and the laser energy can be effectively used to heat the metal bump 130. In addition, the irradiation energy (intensity) of the second light 160 can be greater than the irradiation energy (intensity) of the first light 150.

[0056] Furthermore, as long as the metal bump 130 is melted by the irradiation of the second light 160, light other than the aforementioned laser light can be used as the second light 160. For example, lamp light can also be used as the second light 160. Furthermore, the wavelength of the laser light used as the second light 160 is not limited to the wavelengths described above.

[0057] like Figure 8 and Figure 9 As shown, when the first light 150 is irradiated to the pad 120 and the metal bump 130 for the purpose of self-alignment, if the semiconductor substrate 110 is thin as described above, the semiconductor chip 100 may be warped. Figure 8 When the first light 150 is irradiated by the method of irradiating the first light 150, if there is a portion where the pad 240 is not in contact with the metal bump 130 (or the flux 140), even if the metal bump 130 is melted by the first light 150, the metal bump 130 is not connected to the pad 240. Figure 11As shown, by applying downward pressure to semiconductor chip 100 from the second surface 102 side of semiconductor chip 100 via support member 310, warping of semiconductor chip 100 can be corrected. Consequently, pads 240 and metal bumps 130 can be forcibly brought into contact. Since second light 160 is irradiated in this state, even if there are areas where metal bumps 130 are not connected to pads 240 during irradiation with first light 150, irradiation with second light 160 can still connect metal bumps 130 and pads 240.

[0058] Furthermore, the above example illustrates a structure in which the semiconductor chip 100 is pressurized while the support member 310 is in contact with the second surface 102 of the semiconductor chip 100. However, the present invention is not limited to this structure. For example, other components may be provided between the semiconductor chip 100 and the support member 310. For example, to prevent structural damage on the second surface 102 side of the semiconductor chip 100, a buffer component may be provided between the semiconductor chip 100 and the support member 310. As this buffer component, a component that is softer (has a lower Young's modulus) than both the semiconductor substrate 110 and the support member 310 can be used.

[0059] In the above example, the method of irradiating the first light 150 and the second light 160 only through the supporting member 310 is illustrated, but the present invention is not limited to this method. Figure 12 As shown, second light 160A is irradiated with a mask 320A having an opening 321A disposed on a support member 310A. Mask 320A is a member that does not transmit second light 160A. Alternatively, mask 320A attenuates second light 160A to such an extent that second light 160A does not affect wiring substrate 200A.

[0060] The mask 320A blocks the second light 160A that is located outside the semiconductor chip 100A when viewed from above. That is, when viewed from above, the opening 321A formed in the mask 320A overlaps with the semiconductor chip 100A. Similarly, when viewed from above, the mask 320A covers the area of the wiring substrate 200A that does not overlap with the semiconductor chip 100A. It is sufficient for the opening 321A to at least overlap with the metal bump 130A when viewed from above. With the above-described structure, it is possible to prevent the wiring substrate 200A exposed from the semiconductor chip 100A when viewed from above from being heated by the second light 160A. Furthermore, the mask 320A covers at least that part of the wiring substrate 200A that is affected by the second light 160A and has its characteristics changed. That is, a portion of the wiring substrate 200A can be exposed from both the semiconductor chip 100A and the mask 320A.

[0061] The mask 320A described above is used not only in the step of irradiating the second light 160A but also in the step of irradiating the first light.

[0062] In the above example, the mask 320A is arranged on the semiconductor chip 100A side (the second surface 102A side of the semiconductor chip 100A), but it may also be arranged on the second surface 102A side of the semiconductor chip 100A. Figure 13 As shown, the mask 320A is arranged on the wiring substrate 200A side (closer to the wiring substrate 200A side than the second surface 102A of the semiconductor chip 100A). Alternatively, it may be as follows Figure 12 As shown on the semiconductor chip 100A side, and as Figure 13 As shown, masks are arranged on both sides of the wiring substrate 200A.

[0063] exist Figure 11 In the example, the second surface 102 of the semiconductor chip 100 is in contact with the supporting member 310 as a whole, but the present invention is not limited to this structure. Figure 14 As shown, the semiconductor chip 100B is pressurized using a support component 310B provided with an opening 311B. When viewed from above, the opening 311B overlaps with the metal bump 130B. A plurality of openings 311B may be provided for each of the plurality of metal bumps 130B, or a single opening 311B may be provided to uniformly open the plurality of metal bumps 130B. In the latter case, only the outer periphery of the semiconductor chip 100B contacts the support component 310B. In the case of the above-mentioned structure, a component that does not transmit the second light 160 may be used as the support component 310B. For example, Figure 12 As shown in the mask 320A, the support member 310B is a member that attenuates the second light 160B to such an extent that the second light 160B does not affect the wiring substrate 200B.

[0064] The above-mentioned supporting member 310B is used not only in the step of irradiating the second light 160B but also in the step of irradiating the first light.

[0065] After the metal bump 130 is melted by the irradiation of the second light 160 as described above, the irradiation of the second light 160 is stopped or weakened. As the irradiation of the second light 160 is stopped or weakened, the metal bump 130 dissipates heat and continues to dissipate heat until the temperature of the melted metal bump 130 reaches below the solidification point of the metal bump 130. As the temperature of the metal bump 130 reaches below the solidification point, the melted metal bump 130 solidifies, and a solidified metal bump 130 can be obtained. Figure 15 The metal bump 130 is connected to the pad 240. In addition, when the second light 160 is stopped or weakened, the output of the light source can be adjusted, and a shielding plate or attenuator can be provided on the optical path of the second light 160.

[0066] After metal bumps 130 and pads 240 are connected by irradiation with second light 160, a cleaning process is performed to remove residual flux 140, and underfill 250 is formed between semiconductor chip 100 and wiring substrate 200. Underfill 250 can be made from single, composite, or laminated organic materials such as polyimide resin, polyamide resin, epoxy resin, acrylic resin, phenolic resin, silicone resin, PBO (PolyBenz Oxazole) resin, and benzocyclobutene resin. Furthermore, a resin layer 600 is formed to cover wiring substrate 200, semiconductor chip 100, and underfill 250.

[0067] In the above-described manufacturing method, a method is described in which, when irradiating the first light 150 onto the pads 120 and metal bumps 130, the first light 150 does not pass through the support member 310 to irradiate the pads 120 and metal bumps 130. However, the present invention is not limited to this method. For example, the support member 310 may be positioned above the semiconductor chip 100 without contacting the semiconductor chip 100, and the first light 150 may pass through the support member 310 to irradiate the pads 120 and metal bumps 130. Alternatively, when a buffer member is placed between the semiconductor chip 100 and the support member 310 as described above, the first light 150 may pass through the support member 310 and the buffer member to irradiate the pads 120 and metal bumps 130.

[0068] [Irradiation Method of First Light 150 and Second Light 160]

[0069] use Figure 16 The irradiation method of the first light 150 and the second light 160 will be described. Figure 16 This is a timing chart showing a method of connecting a metal bump and a pad by light irradiation in a method of manufacturing a semiconductor device according to one embodiment. Figure 16 The horizontal axis represents time, and the vertical axis represents light intensity, load or temperature. Figure 16 , a first curve 810 indicating the intensity of the first light 150 and the second light 160 , a second curve 820 indicating the pressure of the semiconductor chip 100 pressed against the wiring substrate 200 by the support member 310 , and a third curve 830 indicating the temperature of the metal bump 130 are shown.

[0070] like Figure 16As shown, at time T11, first light 150 is irradiated onto pad 120 and metal bump 130. Metal bump 130 absorbs the energy of first light 150, causing its temperature to rise. If this temperature exceeds the melting point of metal bump 130, metal bump 130 melts. This melting of metal bump 130 allows for self-alignment of semiconductor chip 100. After this self-alignment, irradiation with first light 150 is stopped or reduced at time T12. When irradiation with first light 150 is stopped or reduced, the temperature of metal bump 130 gradually decreases due to heat dissipation from metal bump 130. Furthermore, when the temperature of metal bump 130 falls below its freezing point, the melted metal bump 130 solidifies, securing semiconductor chip 100 in the position determined by the self-alignment.

[0071] Then, at time T13, semiconductor chip 100 is pressed toward wiring substrate 200 using support member 310. This pressure forces metal bump 130 and pad 240 into contact. Furthermore, at time T14, second light 160 is irradiated onto pad 120 and metal bump 130. Metal bump 130 absorbs the energy of second light 160, causing its temperature to rise. When this temperature exceeds its melting point, metal bump 130 melts again. Then, at time T15, the irradiation with second light 160 is stopped or reduced. When the irradiation with second light 160 is stopped or reduced, the temperature of metal bump 130 gradually decreases due to heat dissipation from metal bump 130, and the melted metal bump 130 solidifies. In this embodiment, the pressure applied to semiconductor chip 100 by support member 310 is also stopped at time T15, simultaneously with the irradiation with second light 160. In addition, the intensity of the second light 160 is greater than the intensity of the first light 150 .

[0072] As described above, even if the semiconductor substrate 110 of the semiconductor chip 100 is warped and there are areas where the metal bumps 130 and pads 240 are not connected by the first light 150, the semiconductor chip 100 is pressed by the support member 310 during the irradiation with the second light 160. Therefore, the metal bumps 130 in these areas are melted by the irradiation with the second light 160 while in contact with the pads 240. As a result, even in these areas, the metal bumps 130 and pads 240 can be connected. Before the irradiation with the second light 160, the flux 140 can be applied again between the semiconductor chip 100 and the wiring substrate 200.

[0073] [Modification of the Irradiation Method of the First Light 150 and the Second Light 160]

[0074] In the above example, the semiconductor chip 100 is pressed by the support member 310 and then irradiated with the second light 160. However, the semiconductor chip 100 may be irradiated with the second light 160. Figure 17 As shown, the timing (T13) of pressurizing the semiconductor chip 100 is the same as the timing (T14) of irradiating the second light 160. Figure 17 By performing pressurization and irradiation with the second light 160 at the timing shown, the processing time can be shortened.

[0075] Alternatively, you can Figure 18 As shown, after the semiconductor chip 100 is pressurized (T13), the irradiation of the second light 160 is started (T14), and after the irradiation of the second light 160 is stopped (T15) or weakened, the pressurization of the semiconductor chip 100 is completed (T16). Figure 18 By performing the pressurization and the irradiation with the second light 160 at the timing shown, the metal bump 130 and the pad 240 can be connected more reliably.

[0076] exist Figures 16 to 18 In the example of FIG, a structure for controlling the magnitude of the force for pressing the support member 310 is illustrated, but the present invention is not limited to this structure. Figure 19 As shown, control is performed to maintain the positions (heights) of the support member 310 and the semiconductor chip 100 that move with the pressurization. Figure 19 The fourth curve 840 shown represents the position (height) of the support member 310 and the semiconductor chip 100. Figure 19 As shown, at time T13, the semiconductor chip 100 is pressed by the support member 310 and moved toward the wiring substrate 200 ( Figure 19 The second light 160 is then irradiated to maintain the position (height) of the support member 310 and the semiconductor chip 100 until time T16. During this period, the second light 160 is irradiated, achieving the same effect as described above. Since the position (height) of the semiconductor chip 100 is maintained along with the support member 310, the gap between the semiconductor chip 100 and the wiring substrate 200 can be maintained constant.

[0077] As described above, according to the semiconductor device manufacturing method related to the first embodiment, a method for mounting an IC chip can be provided, which can perform high-precision positioning of flip-chip bonding without using expensive equipment with high positioning accuracy, and can also suppress the influence of warping of the IC chip.

[0078] <Second embodiment>

[0079] use Figures 20 to 22A semiconductor device 10C according to a second embodiment and a method for manufacturing the same will now be described. While similar to the semiconductor device 10 according to the first embodiment, the semiconductor device 10C according to the second embodiment differs from the semiconductor device 10 in that the bonding pads 120C, metal bumps 130C, and bonding pads 240C are located both inside and outside the semiconductor chip 100C when viewed from above. In the following description, descriptions of the same structures as those in the first embodiment will be omitted, and the description will focus on the structures that differ from the first embodiment. Figures 20 to 22 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment.

[0080] like Figure 20 As shown, pad 120C includes a first pad 121C and a second pad 123C. Metal bump 130C includes a first metal bump 131C and a second metal bump 133C. Pad 240C includes a first pad 241C and a second pad 243C. First metal bump 131C is disposed on first pad 121C. Second metal bump 133C is disposed on second pad 123C. First metal bump 131C is connected to first pad 241C. Second metal bump 133C is connected to second pad 243C. In a top view of semiconductor chip 100C, first pad 121C, first metal bump 131C, and first pad 241C are disposed inwardly relative to second pad 123C, second metal bump 133C, and second pad 243C. In other words, the second pads 123C, the second metal bumps 133C, and the second pads 243C are disposed near the periphery of the semiconductor chip 100C. For example, if the semiconductor chip 100C is rectangular, the second pads 123C, the second metal bumps 133C, and the second pads 243C are disposed at corners of the semiconductor chip 100C.

[0081] Figure 20 The process is the same as that of the first embodiment. Figure 8 The same process as shown in the figure. However, Figure 20 In, with Figure 8Differently, the first light 150C is irradiated to the pad 120C and the metal bump 130C through the supporting part 310C away from the semiconductor chip 100C (not in contact with the semiconductor chip 100C). The semiconductor chip 100C is a stacked structure in which an insulating layer and a conductive layer are stacked on a semiconductor substrate 110C. As described above, if the thickness of the semiconductor substrate 110C is thin, the rigidity of the semiconductor substrate 110C is reduced, so there is a case where the semiconductor chip 100C warps due to the combined stress of the insulating layer and the conductive layer stacked on the semiconductor substrate 110C. In this embodiment, an example is shown in which the thickness of the semiconductor substrate 110C is greater than 10μm and less than 100μm, or greater than 20μm and less than 70μm, and the semiconductor chip 100C warps due to the above-mentioned combined stress. Figure 20 In the example shown, the above-mentioned combined stress is a compressive stress, and the semiconductor chip 100C is bent in a convex shape toward the bottom.

[0082] like Figure 20 As shown, in this embodiment, when irradiated with first light 150C, due to the warping of semiconductor chip 100C, although first metal bump 131C contacts first pad 241C, second metal bump 133C does not contact second pad 243C. If irradiated with first light 150C in this state, first metal bump 131C and second metal bump 133C melt due to the irradiation energy of first light 150C, and self-alignment is performed based on the contact between first metal bump 131C and first pad 241C. After this self-alignment, irradiation with first light 150C is stopped or reduced, causing first metal bump 131C to solidify at the position where self-alignment was performed, thereby fixing the position of semiconductor chip 100C relative to wiring substrate 200C.

[0083] exist Figure 20 The lower part of the diagram shows a partially enlarged view of the first pad 121C, the first metal bump 131C, and the first pad 241C. This partially enlarged view shows a state where the first metal bump 131C is melted and connected to the first pad 241C due to the irradiation of the first light 150C. Figure 20 As shown in the partially enlarged view of FIG1 , a first compound layer 251C is formed between the first metal bump 131C and the first pad 241C. The first compound layer 251C is formed by alloying the first metal bump 131C and the first pad 241C due to the heat generated by irradiation with the first light 150C. Specifically, the first compound layer 251C is a layer containing the material of the first metal bump 131C and the material of the first pad 241C. Specifically, the first compound layer 251C is, for example, an alloy containing Ni and Sn, or an alloy containing Cu and Sn.

[0084] Figure 21The process is the same as that of the first embodiment. Figure 10 The semiconductor chip 100C is pressed toward the wiring substrate 200C by the support member 310C, thereby correcting the warpage of the semiconductor chip 100C. That is, the outer periphery of the semiconductor chip 100C is pressed toward the wiring substrate 200C by the support member 310C. As a result, the second solder pad 123C and the second metal bump 133C are pressed toward the second solder pad 243C, as shown in FIG. Figure 21 As shown, the second metal bump 133C is in contact with the second pad 243C.

[0085] Then, if Figure 22 As shown, in Figure 21 The second light 160C is irradiated on the pad 120C and the metal bump 130C in a state where the semiconductor chip 100C is pressurized by the support part 310C. The first metal bump 131C is already connected (fixed) to the first pad 241C, and the second metal bump 133C is in contact with the second pad 243C due to the pressure of the support part 310C. Therefore, due to the irradiation of the second light 160C, the first metal bump 131C and the second metal bump 133C are melted respectively and connected to the first pad 241C and the second pad 243C respectively. Then, by stopping or weakening the irradiation of the second light 160C, the first metal bump 131C and the second metal bump 133C are solidified respectively. As a result, the first metal bump 131C is connected to the first pad 241C, and the second metal bump 133C is connected to the second pad 243C.

[0086] exist Figure 22 The lower part of the figure shows a first partial enlarged view of the first pad 121C, the first metal bump 131C and the first pad 241C, and a second partial enlarged view of the second pad 123C, the second metal bump 133C and the second pad 243C. Figure 20 The partially enlarged view shown is similar to that shown in FIG. 1 , but due to the irradiation of the second light 160C, the reaction of the first compound layer 251C further proceeds, so Figure 20The thickness of the second compound layer 251C is greater than that of the first compound layer 251C. The second partial enlarged view shows the state in which the second metal bump 133C is melted and connected to the second pad 243C due to irradiation with the second light 160C. As shown in the second partial enlarged view, a second compound layer 253C is formed between the second metal bump 133C and the second pad 243C. The second compound layer 253C is formed by alloying the second metal bump 133C and the second pad 243C due to the heat generated by irradiation with the second light 160C. In other words, the second compound layer 253C is a layer containing the material of the second metal bump 133C and the material of the second pad 243C. Specifically, the second compound layer 253C is similar to the first compound layer 251C, for example, an alloy containing Ni and Sn, or an alloy containing Cu and Sn.

[0087] like Figure 22 As shown in the first and second enlarged views of the semiconductor chip 100C, the thickness of the first compound layer 251C is greater than that of the second compound layer 253C. This is because the first compound layer 251C is formed by two light irradiations: the first light 150C and the second light 160C. Furthermore, the compound layer may be more fragile than the metal bumps and pads. In such cases, by making the compound layer thinner on the outside than on the inside of the semiconductor chip 100C, cracks caused by the compound layer can be suppressed.

[0088] In the above example, the semiconductor chip 100C is curved downward in a convex shape, so the thickness of the first compound layer 251C is greater than the thickness of the second compound layer 253C, but the present invention is not limited to this structure.

[0089] The present invention has been described above with reference to the accompanying drawings. However, the present invention is not limited to the above-described embodiments and can be appropriately modified without departing from the scope of the invention. For example, a semiconductor device obtained by adding, deleting, or modifying the design of components based on the semiconductor device of this embodiment is included in the scope of the present invention as long as it meets the scope of the present invention. In addition, the above-described embodiments can be appropriately combined as long as there is no contradiction between them. Technical matters common to the various embodiments are included in the scope of the present invention even if they are not explicitly described.

[0090] Even if the effects are different from the effects produced by the forms of the above-mentioned embodiments, the effects that have been clearly described in this specification or the effects that can be easily thought of by those skilled in the art should of course be understood as the effects produced according to the present invention.

Claims

1. A method for manufacturing a semiconductor device, wherein: forming metal bumps on the first surface side of a semiconductor chip having a first surface and a second surface opposite to the first surface; The metal bumps are arranged on pads provided on a wiring substrate. irradiating the semiconductor chip with a first light for melting the metal bump from the second surface side without pressing the semiconductor chip against the wiring substrate; Then, the irradiation of the first light is stopped or weakened to make the melted metal bump reach below the solidification point. while pressing the semiconductor chip toward the wiring substrate, irradiating the second surface side of the semiconductor chip with a second light for melting the metal bumps. Then, the irradiation of the second light is stopped or weakened to make the melted metal bump reach below the solidification point.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The second light is irradiated after the pressurization, and the irradiation of the second light is stopped or weakened simultaneously with the cessation of the pressurization.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The second light is irradiated while the pressurization is being performed, and the irradiation of the second light is stopped or weakened while the pressurization is stopped.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The second light is irradiated after the pressurization, and the pressurization is stopped after the irradiation of the second light is stopped or weakened.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein: Before the metal bump is disposed on the pad, flux is formed on at least one of the pad and the metal bump.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein: The wavelength of the first light is greater than or equal to 850 nm and less than or equal to 1100 nm. The wavelength of the second light is not less than 850 nm and not more than 1100 nm.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein: The intensity of the second light is greater than the intensity of the first light.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein: a first mask is arranged on the semiconductor chip side of the wiring substrate, the first light is irradiated through the first mask, and the first mask covers at least a portion of the wiring substrate in a region that does not overlap with the semiconductor chip when viewed from above; A second mask is arranged on the semiconductor chip side of the wiring substrate, and the second light is irradiated through the second mask, the second mask covering at least a portion of a region of the wiring substrate that does not overlap with the semiconductor chip in a plan view.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The first mask and the second mask are arranged on the second surface side of the semiconductor chip.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: The first mask and the second mask are arranged on the wiring substrate side relative to the second surface of the semiconductor chip.

11. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein: When the semiconductor chip is pressed toward the wiring substrate, the position of the semiconductor chip that moves with the pressing is maintained.

12. A method for manufacturing a semiconductor device, wherein: forming metal bumps on the first surface side of a semiconductor chip having a first surface and a second surface opposite to the first surface; The metal bumps are arranged on pads provided on a wiring substrate. irradiating the second surface side of the semiconductor chip with a first light for melting the metal bump; Then, the irradiation of the first light is stopped or weakened to make the melted metal bump reach below the solidification point. while pressing the semiconductor chip toward the wiring substrate, irradiating the second surface side of the semiconductor chip with a second light for melting the metal bumps. Then, stopping or reducing the irradiation of the second light to make the melted metal bump reach below the solidification point; Furthermore, the second light is irradiated after the pressurization, and the pressurization is stopped after the irradiation of the second light is stopped or weakened.

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