Embedded wafer-level ball array package antenna structure based on embedded Z-line

Abstract

The present invention discloses an embedded wafer-level ball array package antenna structure based on embedded Z-line, comprising: a mold object, a chip, a first RDL layer, a second RDL layer, an antenna, an EZL vertical interconnection line and a solder ball pin; wherein the first RDL layer and the second RDL layer are respectively arranged at the bottom and the top of the mold object and are in close contact with the mold object; the chip is packaged inside the mold object in a manner that its I / O pin faces the first RDL layer, and the I / O pin is located at the interface between the mold object and the first RDL layer, and extends to the entire first RDL layer through the interconnection line in the first RDL layer; the antenna is integrated in the second RDL layer and connected to the chip through the EZL vertical interconnection line; the solder ball pin is located below the first RDL layer and connected to the interconnection line in the first RDL layer to serve as the pin of the entire package antenna. The package antenna structure provided by the present invention can reduce the overall size of the package antenna, improve the integration, and improve the radio frequency performance of the package antenna.

Description

Technical Field

[0001] The present invention belongs to the technical field of antenna wafer-level packaging, and in particular relates to an embedded wafer-level ball array packaging antenna structure based on embedded Z-lines. Background Art

[0002] With the development of wafer level packaging (WLP) technology, WLP technology can be used to effectively embed heterogeneous devices, including baseband processors, RF transceivers, and power management ICs. According to the different structures and manufacturing processes, WLP technology can be roughly divided into two categories: fan-in WLP and fan-out WLP. The characteristic of Fan-in WLP is that the pins are confined within the size outline of the chip. Due to the small chip area, in order to ensure the reliability of the bumps after flip-chip mounting and facilitate the wiring design of the PCB, the size of the bumps must meet certain requirements. Therefore, in Fan-in WLP technology, the number of bumps that can be made on the chip is greatly limited, which also makes Fan-in WLP technology only applicable to chips with a small number of I / 0. Later, in order to adapt to chip structures with more I / 0 numbers and improve the reliability of packaging, Fan-out WLP technology was derived and developed on the basis of Fan-in WLP. As a representative of Fan-out WLP technology, embedded Wafer Level Ball Grid Array (eWLB) has been widely studied and used in wafer-level packaging processes.

[0003] At present, the main technologies commonly used in embedded wafer-level ball grid array (eWLB) are mostly based on the two vertical interconnection schemes of high-frequency system-level packaging (SiP) integration proposed by Infineon: through encapsulant via (TEV) technology and through silicon via (TSV) technology. This makes the existing eWLB package antenna structure mainly have two forms: one is that the antenna element is in the bottom RDL layer; the other is to use through silicon via (TSV) to vertically interconnect to the top RDL layer.

[0004] However, the above two forms of interconnection lines have large line widths and line spacings, occupying large space in small-size eWLB packages and not suitable for high-density interconnection applications. In addition, for millimeter-wave applications, packaging antenna elements and chips at the same level will also produce large parasitic effects, increase the RF loss between the chip and the antenna, and thus affect the RF performance of the packaged antenna. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides an embedded wafer-level ball array package antenna structure based on embedded Z-line. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] An embedded wafer-level ball array package antenna structure based on embedded Z-line includes: a mold, a chip, a first RDL layer, a second RDL layer, an antenna, an EZL vertical interconnection line and a solder ball pin; wherein,

[0007] The first RDL layer and the second RDL layer are respectively disposed at the bottom and the top of the mold object and are in close contact with the mold object;

[0008] The chip is packaged inside the mold object in a manner that its I / O pins face the first RDL layer, and the I / O pins are located at the interface between the mold object and the first RDL layer, and extend to the entire first RDL layer through interconnection lines in the first RDL layer;

[0009] The antenna is integrated in the second RDL layer and connected to the chip through the EZL vertical interconnection line;

[0010] The solder ball pins are located below the first RDL layer and are connected to the interconnection lines in the first RDL layer to serve as pins of the entire packaged antenna.

[0011] In one embodiment of the present invention, the mold object is formed of epoxy resin material, the dielectric constant of which is in the range of 3.0-3.4, and the loss tangent value is in the range of 0.004-0.006.

[0012] In one embodiment of the present invention, the dielectric constant of the dielectric material of the first RDL layer and the second RDL layer is in the range of 3.2-3.6, and the loss tangent value is in the range of 0.004-0.007.

[0013] In one embodiment of the present invention, the first RDL layer and the second RDL layer each include at least one redistribution layer.

[0014] In one embodiment of the present invention, the antenna adopts a folded dipole structure made of metal material, and its feeding structure adopts a quarter-wavelength tapered transmission line impedance matching transformer.

[0015] In one embodiment of the present invention, the differential feeding line of the antenna is connected to the chip through the EZL vertical interconnection line and the interconnection line of the first RDL layer.

[0016] In one embodiment of the present invention, the line width and spacing of the EZL vertical interconnection lines are less than 10 μm.

[0017] In one embodiment of the present invention, the pitch of the EZL vertical interconnect lines is the same as the pitch of the differential feed lines (51).

[0018] In one embodiment of the present invention, the EZL vertical interconnection lines have the same thickness and width as the interconnection lines in the first RDL layer.

[0019] Beneficial effects of the present invention:

[0020] 1. The present invention uses an embedded EZL line vertical interconnection method to integrate the chip and the antenna in two different levels in the form of a three-dimensional package. Since the line width and line spacing of the EZL line vertical interconnection are both small, it has extremely high wiring resolution and wiring flexibility, thereby reducing the package size and improving the integration, and is suitable for high-density interconnection applications; at the same time, the three-dimensional packaging structure can also reduce the coupling parasitic effect between the antenna and the chip, and improve the radio frequency performance of the packaged antenna;

[0021] 2. The present invention integrates the chip and the antenna at two different levels and eliminates the position constraint of the antenna in the package, thereby improving the design flexibility of the packaged antenna and facilitating further reduction of the overall size of the packaged antenna;

[0022] 3. The present invention integrates the antenna in the top RDL layer, and there is no other mold object or dielectric layer covering the antenna. Compared with the existing method of integrating the antenna in the bottom RDL layer, this form of the present invention enables the antenna to have better radiation performance, as well as higher gain and bandwidth.

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the structure of an embedded wafer-level ball array package antenna based on embedded Z-line provided by an embodiment of the present invention;

[0025] Figure 2 1 is a top view of an embedded wafer-level ball array package antenna structure based on embedded Z-line provided by an embodiment of the present invention;

[0026] Figure 3 Schematic diagram of the EZL vertical interconnection structure provided by an embodiment of the present invention.

[0027] Explanation of the reference numerals: 1-mold, 2-chip, 3-first RDL layer, 31-interconnection line, 4-second RDL layer, 5-antenna, 51-differential feed line, 6-EZL vertical interconnection line, 7-solder ball pin. DETAILED DESCRIPTION

[0028] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0029] Embodiment 1

[0030] See also Figure 1 , Figure 1 1 is a schematic diagram of an embedded wafer-level ball array package antenna structure based on embedded Z-line provided by an embodiment of the present invention, which includes:

[0031] Mold object 1, chip 2, first RDL layer 3, second RDL layer 4, antenna 5, EZL vertical interconnection line 6 and solder ball pin 7; wherein,

[0032] The first RDL layer 3 and the second RDL layer 4 are respectively disposed at the bottom and the top of the mold object 1 and are closely attached to the mold object 1;

[0033] The chip 2 is packaged inside the mold object 1 in such a way that its I / O pins face the first RDL layer 3, and the I / O pins are located at the interface between the mold object 1 and the first RDL layer 3, and extend to the entire first RDL layer 3 through the interconnection lines in the first RDL layer 3;

[0034] The antenna 5 is integrated in the second RDL layer 4 and connected to the chip 2 via the EZL vertical interconnect line 6;

[0035] The solder ball pins 7 are located below the first RDL layer 3 and connected to the interconnection lines in the first RDL layer 3 to serve as pins of the entire package antenna.

[0036] The overall package size of the packaged antenna provided in this embodiment does not exceed 10 mm*10 mm, and the overall thickness of the structure is between 500 μm and 750 μm.

[0037] Specifically, in this embodiment, for the material selection of the mold object 1, an epoxy resin material with a dielectric constant of 3.0-3.4 and a loss tangent value of 0.004-0.006 is usually selected, such as cresol novolac or biphenyl, and a silica filler, etc., and its thickness is between 200μm and 400μm. Preferably, in this embodiment, an epoxy resin material with a dielectric constant of 3.2 and a loss tangent value of 0.004 is used to prepare the mold object.

[0038] As for the chip 2, this embodiment uses an analog chip made of a silicon wafer, and its size is generally 2mm*3mm.

[0039] For the materials of the first RDL layer 3 and the second RDL layer 4, dielectric materials with a dielectric constant of 3.2-3.6 and a loss tangent of 0.004-0.007 are generally selected, such as polyimide (PI), polybenzoxazole (PBO) or benzocyclobutene (BCB), etc. Preferably, the present embodiment uses a dielectric material with a dielectric constant of 3.4 and a loss tangent of 0.005 to form the RDL layer.

[0040] Furthermore, the first RDL layer 3 and the second RDL layer 4 each include at least one redistribution layer, which can be specifically configured according to actual conditions. In this embodiment, a single RDL layer is preferably used, such as Figure 1 shown.

[0041] In addition, for the design of the solder ball pin 7, that is, the solder ball, its height is generally set to 100 μm-200 μm, and the standard ball spacing is 500 μm.

[0042] In this embodiment, according to Figure 1 As shown, a mold with a thickness of 0.27 mm, a bottom first RDL layer 3 with a thickness of 0.1 mm, a top second RDL layer 4 with a thickness of 0.08 mm, a silicon wafer with a size of 2 mm*3 mm, and solder ball pins 7 with a solder ball diameter of 0.15 mm and a spacing of 0.5 mm are used to form a packaged antenna structure with an overall package size of 8 mm*8 mm and a total thickness of 0.54 mm.

[0043] Furthermore, the antenna 5 in this embodiment adopts a folded dipole structure made of metal material, a dielectric coating is placed on the radiating part of the antenna, the feeding method is differential feeding, and the feeding structure adopts a quarter-wavelength gradient transmission line impedance matching transformer.

[0044] Specifically, see Figure 2 , Figure 2 It is a top view of an embedded wafer-level ball array package antenna structure based on an embedded Z-line provided by an embodiment of the present invention, wherein the antenna 5 is an antenna array composed of two folded dipole antennas, the center frequency of which is 77GHz, the radiation part of the antenna unit is 1.18mm long, the width is 0.035mm, and the spacing between the two differential feed lines is 0.02mm. The distance between the two folded dipole antenna units is between half a wavelength and one wavelength, and a quarter-wavelength impedance transformer is used between the radiation part and the feeding part of the antenna element for impedance matching. The feeding method of the folded dipole is differential feeding, and the feed line is a pair of differential feed lines, one end of the feed line is connected to two quarter-wavelength impedance transformers, and the other end is connected to two EZL vertical interconnect lines 6.

[0045] In this embodiment, the antenna is integrated into the top RDL layer, and there is no other mold object or dielectric layer covering the antenna. Compared with the existing method of integrating the antenna into the bottom RDL layer, this form of the present invention enables the antenna to have better radiation performance, as well as higher gain and bandwidth.

[0046] For further information, see Figure 3 , Figure 3 is a schematic diagram of an EZL vertical interconnection structure provided by an embodiment of the present invention, wherein the differential feed line 51 of the antenna 5 is connected to the chip 2 through the EZL vertical interconnection line 6 and the interconnection line 31 of the first RDL layer 3 .

[0047] Specifically, the line width and spacing of the EZL vertical interconnection line 6 are less than 10 micrometers. For example, the width of the EZL vertical interconnection line can be set to 0.02 mm, the thickness to 0.01 mm, and the height to 0.37 mm.

[0048] Furthermore, the pitch of the EZL vertical interconnection lines 6 is the same as the pitch of the differential feed lines 51, so that the EZL vertical interconnection lines 6 and the differential feed lines 51 can be directly connected. Meanwhile, the thickness and width of the EZL vertical interconnection lines 6 are the same as the thickness and width of the interconnection lines 31 in the first RDL layer 3.

[0049] It should be noted that, at the connection between the EZL vertical interconnection line 6 and the differential feed line 51 and the interconnection line 31 of the first RDL layer 3 , its width is slightly larger than that of the differential line, so as to achieve impedance matching.

[0050] The EZL vertical interconnection lines used in this embodiment have very small line width and spacing, so that they have extremely high wiring resolution and wiring flexibility, overcoming the shortcomings of existing interconnection methods such as large line width and line spacing, large space occupation in small-size eWLB packaging, and limited high-density interconnection applications.

[0051] This embodiment uses an embedded EZL line vertical interconnection method to integrate the chip and the antenna in two different levels in the form of a three-dimensional package, reducing the coupling parasitic effect between the antenna and the chip and improving the RF performance of the packaged antenna. At the same time, integrating the chip and the antenna at two different levels also eliminates the position constraint of the antenna in the package, improves the design flexibility of the packaged antenna, and is conducive to further reducing the overall size of the packaged antenna.

[0052] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0054] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. An embedded wafer-level ball array package antenna structure based on embedded Z-line, characterized in that: include: A mold object (1), a chip (2), a first RDL layer (3), a second RDL layer (4), an antenna (5), an EZL vertical interconnection line (6) and a solder ball pin (7); wherein, The first RDL layer (3) and the second RDL layer (4) are respectively arranged at the bottom and the top of the mold object (1) and are in close contact with the mold object (1); The chip (2) is packaged inside the mold object (1) in a manner such that its I / O pins face the first RDL layer (3), and the I / O pins are located at the interface between the mold object (1) and the first RDL layer (3), and extend to the entire first RDL layer (3) through interconnection lines in the first RDL layer (3); The antenna (5) is integrated in the second RDL layer (4) and connected to the chip (2) via the EZL vertical interconnection line (6); The solder ball pin (7) is located below the first RDL layer (3) and is connected to the interconnection line in the first RDL layer (3) to serve as a pin of the entire package antenna; Wherein, the line width and spacing of the EZL vertical interconnection lines (6) are less than 10 μm.

2. The embedded wafer-level ball array package antenna structure based on embedded Z-line according to claim 1, characterized in that: The mold object (1) is made of epoxy resin material, the dielectric constant of which is in the range of 3.0-3.4, and the loss tangent value is in the range of 0.004-0.

006.

3. The embedded wafer-level ball array package antenna structure based on embedded Z-line according to claim 1, characterized in that: The dielectric constant of the dielectric material of the first RDL layer (3) and the second RDL layer (4) is in the range of 3.2-3.6, and the loss tangent value is in the range of 0.004-0.

007.

4. The embedded wafer-level ball array package antenna structure based on embedded Z-line according to claim 1, characterized in that: The first RDL layer (3) and the second RDL layer (4) each include at least one redistribution layer.

5. The embedded wafer-level ball array package antenna structure based on embedded Z-line according to claim 1, characterized in that: The antenna (5) adopts a folded dipole structure made of metal material, and its feeding structure adopts a quarter-wavelength gradient transmission line impedance matching transformer.

6. The embedded wafer-level ball array package antenna structure based on embedded Z-line according to claim 5, characterized in that: The differential feed line (51) of the antenna (5) is connected to the chip (2) via the EZL vertical interconnection line (6) and the interconnection line (31) of the first RDL layer (3).

7. The embedded wafer-level ball array package antenna structure based on embedded Z-line according to claim 6, characterized in that: The pitch of the EZL vertical interconnection lines (6) is the same as the pitch of the differential feed lines (51).

8. The embedded wafer-level ball array package antenna structure based on embedded Z-line according to claim 1, characterized in that: The EZL vertical interconnection line (6) has the same thickness and width as the interconnection line (31) in the first RDL layer (3).

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