A chip interconnect structure

Abstract

The present invention belongs to the technical field of chip interconnection, and particularly relates to a chip interconnection structure. The chip interconnection structure includes at least one chip module combination. Each chip module combination includes two relatively arranged chip modules. Each chip module electrically leads out towards its geometric center. The chip modules of each chip module combination are electrically connected through conductive lines. The conductive lines of each chip module combination are electrically connected to each other. A dielectric layer is filled between each chip module combination. The conductive lines of the present chip interconnection structure can be flexibly adjusted in length according to the distance between the relatively arranged chip modules by growing the dielectric layer layer by layer, which is beneficial to reducing the overall volume of the packaging structure and has better adaptability. The process of this interconnection structure is simpler. The depth of the holes is not limited and fixed by the thickness of a single layer of chips, but is determined by the single growth height of the dielectric layer. The conductive lines are more completely deposited in the holes and are not prone to process defects.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip interconnection, and particularly relates to a chip interconnection structure. Background Art

[0002] In three-dimensional packaging, TSV is a key technology for realizing vertical interconnection between multiple chips. The TSV technology realizes vertical electrical interconnection of silicon vias through filling with conductive materials such as copper, tungsten, and polysilicon, achieving high density, high electrical performance, low cost, and low power consumption, conforming to the development trend of integrated circuits. The silicon via technology is gradually replacing the currently relatively mature wire bonding technology and is considered the fourth-generation packaging technology.

[0003] The conductivity of silicon vias is mainly achieved by filling conductive materials in the vias. The filling of conductive materials is considered the most challenging link in the preparation process of silicon vias. The current filling method is to grow a uniform seed layer on the sidewalls of the holes through physical vapor deposition or chemical vapor deposition, and then fill the hole cores with electroplated copper. The conformality, density, and uniformity of the seed layer directly affect the filling effect and the overall reliability of the silicon vias. Depositing a high-quality metal seed layer on the sidewalls of the silicon vias is a difficult task, and as the aperture decreases and the aspect ratio increases, the difficulty is further exacerbated. It is also extremely difficult to ensure the same growth rate at the top, middle, and bottom of the holes during electroplating copper.

[0004] Therefore, the existing technology needs to be improved and developed. Summary of the Invention

[0005] The purpose of the present invention is to provide a chip interconnection structure that can make the interconnection between chip modules more reliable.

[0006] To solve the above technical problems, a chip interconnection structure provided by the present application includes at least one chip module combination. Each chip module combination includes two relatively arranged chip modules. Each chip module electrically leads out to its geometric center respectively. The chip modules of each chip module combination are electrically connected through conductive lines. The conductive lines of each chip module combination are electrically connected to each other. A dielectric layer is filled between each chip module combination. The occupied area of the conductive lines is reduced, the integration density is higher, and it is easier to manufacture and less likely to have process defects.

[0007] Further, the conductive circuit includes a horizontally conductive circuit and a vertically conductive circuit that are connected to each other. The horizontally conductive circuit points from the pads of the chip module to the geometric center of the chip module, and the vertically conductive circuit is parallel to the axis passing through the geometric center of the chip module. The horizontally conductive circuit concentrates the pads of the chips on the same carrier board to the geometric center, facilitating electrical connection with the vertically conductive circuit. The vertically conductive circuit is used to electrically connect the ports of the geometric centers on different carrier boards.

[0008] Further, the conductive circuits are arranged in a multi-layer concentric circle pattern evenly. The conductive circuits arranged in a multi-layer concentric circle pattern are arranged more closely under the condition of the same pitch, and have a higher integration density.

[0009] Further, the geometric centers of the chip modules in each chip module combination are axially aligned.

[0010] Further, the chip module is a pre-packaged system-level packaging structure.

[0011] Further, the chip module has one chip or multiple chips mounted on the same carrier board.

[0012] Further, the diameter of the conductive circuit is 15 - 500 microns.

[0013] Further, the pitch between two adjacent conductive circuits is 2 - 1000 microns.

[0014] Further, the dielectric layer is any one of ABF, liquid crystal polymer, polyimide, and high polymer polypropylene.

[0015] Further, the conductive circuit is any one of copper, silver, gold, and tin.

[0016] As can be seen from the above, for the conductive circuits of the present chip interconnection structure, by growing the dielectric layer layer by layer, the length can be flexibly adjusted according to the distance between the relatively arranged chip modules, which is beneficial to reducing the overall volume of the packaging structure, has better adaptability, and can adapt to the interconnection of chips with different specifications and different processes. Compared with the TSV interconnection structure, this interconnection structure has a simpler process. The depth of the hole is not limited and fixed by the thickness of a single-layer chip, but is determined by the single growth height of the dielectric layer. The conductive circuit is more completely deposited in the hole, and process defects are not likely to occur. The area occupied by the conductive circuit is reduced, the integration density is higher, and a higher data transmission rate and bandwidth are provided.

[0017] Other features and advantages of the present application will be described in the subsequent specification, and, in part, will become apparent from the specification or can be understood by implementing the present application. The objectives and other advantages of the present application can be achieved and obtained through the structures specifically pointed out in the written specification, claims, and drawings. Brief Description of the Drawings

[0018] Figure 1 A cross-sectional view showing the chip interconnect structure in the first embodiment of the present application is shown.

[0019] Figure 2 A cross-sectional view showing the chip interconnect structure in the second embodiment of the present application is shown.

[0020] Figure 3 A flowchart showing the steps of the manufacturing method of the chip interconnect structure in the first embodiment of the present application is shown.

[0021] Reference Numeral Description: 1, the first chip module; 10, the first carrier board; 11, the first chip; 12, the second chip; 13, the pad; 2, the second chip module; 20, the second carrier board; 21, the third chip; 22, the fourth chip; 3, the third chip module; 4, the fourth chip module; 5, the conductive line; 51, the horizontal conductive line; 52, the vertical conductive line; 6, the dielectric layer. Detailed Description of the Embodiments

[0022] The embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0023] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0024] In the description of the present invention, it should be noted that, unless otherwise clearly specified and defined, the terms "mounted", "connected" and "coupled" should be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, an electrical connection, or a connection capable of mutual communication; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0025] In the present invention, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or simply means that the horizontal height of the first feature is lower than that of the second feature.

[0026] The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and / or the use of other materials.

[0027] First Embodiment

[0028] Figure 1The cross-sectional view of the chip interconnection structure in the first embodiment of the present application is shown. The chip interconnection structure includes at least one chip module combination, and each chip module combination includes two relatively arranged chip modules. In this embodiment, there are two chip modules, including the first chip module 1 and the second chip module 2, and the above two chip modules form a chip module combination. The chip module can be a system-level packaging structure pre-packaged with a packaging layer, or a structure in which one chip, two chips or multiple chips are mounted on the same carrier board. The first chip module 1 is a packaging structure in which the first chip 11 and the second chip 12 are mounted on the first carrier board 10, and the second chip module 2 is a packaging structure in which the third chip 21 and the fourth chip 22 are mounted on the second carrier board 20. The chip module electrically leads out to its geometric center. Assuming that the shapes of the first carrier board 10 and the second carrier board 20 are square, the chips mounted on them are mounted on the carrier board with the face up, and its geometric center is the intersection of the diagonals of the square. The total path from this intersection to the outer contour of the carrier board is the smallest, which can provide the smallest transmission distance.

[0029] The conductive line 5 includes a horizontal conductive line 51 and a vertical conductive line 52. The horizontal conductive line 51 points from the pad 13 of the chip module to the geometric center of the chip module. The horizontal conductive line 51 concentrates the pads 13 of the chips on the same carrier board to the geometric center, facilitating the electrical connection of the vertical guiding lines to each other. The vertical guiding lines are parallel to the axis passing through the geometric center and are used to electrically connect the ports of the geometric centers on different carrier boards. In this embodiment, in order to form a vertical conductive line 52 with higher linear accuracy, the geometric centers of the chip modules in each chip module combination need to be axially aligned. For example, the geometric centers of the first chip module 1 and the second chip module 2 should be on the same straight line.

[0030] The material of the conductive line 5 can be any one of copper, silver, gold, and tin. Copper has good electrical conductivity, a relatively high melting point, and good electromigration resistance, and is a commonly used material for metal interconnection. In this embodiment, the electroplating process in electrochemical deposition is used to form a conductive line 5 with a diameter of 15 - 500 microns in the dielectric layer 6. By providing the dielectric layer 6, on the one hand, the gap between the relatively arranged chip modules is filled, so that the chip modules are fixed to each other to form a stable structure, and on the other hand, it prevents short circuits between the conductive lines 5 and increases the reliability of chip interconnection.

[0031] It should be noted that the material of the dielectric layer 6 can be one of ABF (Ajinomoto Build-up Film), liquid crystal polymer (LCP), polyimide (PI), and high polymer polypropylene.

[0032] Two adjacent parallel traces form a routing capacitance. Such a capacitance can cause a current signal on one trace when there is a rapid voltage change on another trace. A large amount of coupled noise and crosstalk between channels in the conductive line 5 cause serious signal quality problems during the signal transmission process. The smaller the spacing between the conductive lines 5, the greater the coupling and the stronger the crosstalk. To improve the signal transmission quality inside a three-dimensional high-speed information system, by reasonably controlling the spacing between the conductive lines 5, the spacing between two adjacent conductive lines 5 is 2 - 1000 micrometers, preferably 60 micrometers, which is beneficial to improving the problem that the signal crosstalk caused by the electromagnetic coupling between adjacent conductive lines 5 affects the transmission performance.

[0033] Second Embodiment

[0034] Figure 2 A cross-sectional view of the chip interconnect structure in the second embodiment of the present application is shown. The difference from the first embodiment is that a second chip module combination is added. The second chip module combination includes a third chip module 3 and a fourth chip module 4. A chip is mounted on each of the third chip module 3 and the fourth chip module 4. The third chip module 3 and the fourth chip module 4 are respectively fixed on both sides of the relatively arranged first chip module 1 and second chip module 2 to form a three-dimensional packaging structure. To interconnect the above four chip modules, the third chip module 3 and the fourth chip module 4 are respectively electrically led out towards their geometric centers and connected to the vertical conductive lines 52 of the first chip module 1 and the second chip module 2 to form a three-dimensional packaging structure.

[0035] Figure 3 A step flowchart of the manufacturing method of the chip interconnect structure in the first embodiment of the present application is shown. It specifically includes the following steps:

[0036] Step 1: Provide a first carrier 10. The first chip 11 and the second chip 12 are mounted on the upper surface of the first carrier 10 with their faces upward.

[0037] Step 2: Grow a dielectric layer 6 layer by layer on the first carrier 10 so that the dielectric layer 6 completely covers the sides and the upper surface of the first chip 11 and the second chip 12. Multiple horizontal grooves are etched on the upper surface of the dielectric layer 6, which lead from the pads 13 of the chips towards the geometric center of the carrier. Copper is formed in the grooves through an electroplating process to form horizontal conductive lines 51.

[0038] Step 3: The dielectric layer 6 continues to grow layer by layer. Starting from the end position near the geometric center of the lateral conductive line 51, blind holes are etched. For each certain height of growth of the dielectric layer 6, a layer of copper with an equal thickness is deposited in the blind holes, and the blind holes gradually extend in the vertical direction, thereby forming the vertical conductive lines 52. The growth height of the dielectric layer 6 is controlled within the range of one to two times the diameter of the conductive lines, so as to ensure that the electroplating solution can smoothly enter the blind holes and avoid the phenomenon of insufficient copper content deposited at the bottom of the blind holes, which may cause voids.

[0039] Step 4: Provide a second carrier plate 20, and the third chip 21 and the fourth chip 22 are mounted on the upper surface of the second carrier plate 20 with their faces upward.

[0040] Step 5: The dielectric layer 6 is grown layer by layer on the second carrier plate 20, so that the dielectric layer 6 completely covers the sides and the upper surface of the third chip 21 and the fourth chip 22. Multiple lateral grooves leading from the pads 13 of the chips to the geometric center of the carrier plate are etched on the upper surface of the dielectric layer 6, and copper is formed in the grooves through the electroplating process to form the lateral conductive lines 51.

[0041] Step 6: Invert the second carrier plate 20 so that the lateral conductive lines 51 on the second carrier plate 20 are aligned one by one with the vertical conductive lines 52 on the first carrier plate 10. Finally, the dielectric layer 6 is joined through an adhesive, thereby obtaining a chip interconnection structure. To make the bonding surface more firmly bonded, a polishing machine can be used to grind the two bonding surfaces to increase the flatness of the bonding surface.

[0042] For the conductive lines 5 of the present chip interconnection structure, by growing the dielectric layer 6 layer by layer, according to the distance between the relatively arranged chip modules, their lengths can be flexibly adjusted, which is beneficial to reducing the overall volume of the packaging structure, has better adaptability, and can adapt to the interconnection of chips with different specifications and different manufacturing processes. Compared with the TSV interconnection structure, the process of this interconnection structure is simpler. The depth of the holes is not limited and fixed by the thickness of a single layer of chips, but is determined by the single - growth height of the dielectric layer 6. The conductive lines 5 are more completely deposited in the holes, and process defects are not likely to occur. The occupied area of the conductive lines 5 is reduced, the integration density is higher, and higher data transmission rates and bandwidths are provided.

[0043] In the description of this specification, the descriptions referring to terms such as "one embodiment", "certain embodiments", "schematic embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above - mentioned terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0044] The above are only some embodiments of the present invention. For those of ordinary skill in the art, without departing from the inventive concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention.

Claims

1. A chip interconnect structure includes at least one chip module combination, characterized in that, Each of the chip module combinations includes two relatively arranged chip modules. Each of the chip modules electrically leads out towards its geometric center. The chip modules of each chip module combination are electrically connected through a conductive line (5). The conductive lines (5) of each chip module combination are electrically connected to each other. A dielectric layer (6) is filled between each chip module combination; The conductive line (5) includes a horizontally conductive line (51) and a vertically conductive line (52) which are connected to each other. The horizontally conductive line (51) points from the pad (13) of the chip module towards the geometric center of the chip module. The vertically conductive line (52) is parallel to the axis passing through the geometric center of the chip module; The conductive lines (5) are arranged in a multi-layer concentric circle pattern evenly.

2. The chip interconnect structure according to claim 1, wherein, The geometric centers of the chip modules of each chip module combination are axially aligned.

3. The chip interconnect structure according to claim 1, characterized in that, The chip module is a pre-packaged system-level packaging structure.

4. The chip interconnect structure according to claim 1, wherein The chip module is one chip or multiple chips mounted on the same carrier board.

5. A chip interconnect structure according to claim 1, wherein, The diameter of the conductive line (5) is 15 - 500 microns.

6. The chip interconnect structure according to claim 1, characterized in that, The spacing between two adjacent conductive lines (5) is 2 - 1000 microns.

7. The chip interconnect structure according to claim 1, wherein The dielectric layer (6) is any one of ABF, liquid crystal polymer, polyimide, and high polymer polypropylene.

8. The chip interconnect structure according to claim 1, wherein, The conductive line (5) is any one of copper, silver, gold, and tin.

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