Nanomagnetic logic majority logic gate circuit based on magnetoelectric effect clock control method

Abstract

The present invention discloses a nanomagnetic logic majority logic gate circuit based on a magnetoelectric effect clock control method, comprising: a first input terminal, a second input terminal, a third input terminal, an intermediate operation circuit, a first output terminal, a second inverter and a second output terminal; the intermediate operation circuit comprises a plurality of first inverters, a first two-input AND gate, a second two-input AND gate, a third two-input AND gate, and a three-input OR gate. The intermediate operation circuit is connected to the input terminal, and its output terminal is connected to a three-input OR gate, which is connected in series with a second inverter, and the output terminal of the second inverter serves as a second output terminal. The present invention designs a clock control scheme based on the magnetoelectric effect based on the majority logic gate circuit. Compared with other known clock control schemes, the clock control scheme can further reduce circuit power consumption and improve circuit speed, and the circuit structure is simple and easy to prepare. At the same time, the clock control scheme is not only applicable to the majority logic gate circuit, but also can be applied to other NML circuits.

Description

Technical Field

[0001] The present invention relates to the field of electronic devices and circuit technology, and in particular to a nanomagnetic logic majority logic gate circuit based on a magnetoelectric effect clock control method. Background Art

[0002] Nanomagnetic logic (NML) uses single-domain nanomagnets with two stable states to represent logic '0' and '1' respectively. It has the advantages of ultra-low power consumption, high integration and non-volatility, and will be an important candidate in the post-CMOS era. In NML circuits, majority logic gates are the basic logic units, and clock control schemes are an important part of NML circuits.

[0003] There are three mainstream clock control schemes for NML circuits, namely, the clock control scheme based on current induction to generate an external magnetic field, the clock control scheme based on spin transfer torque, and the clock control scheme based on magnetoelastic properties. Among them, the clock control scheme based on current induction to generate an external magnetic field is to bury a copper wire under the nanomagnet, and generate an external magnetic field by passing current through the copper wire to control the direction of the magnetic moment of the nanomagnet. Due to the high power dissipation caused by Joule heat, NML no longer has the low power consumption advantage compared to CMOS devices; the clock control scheme based on spin transfer torque uses a magnetic tunnel junction structure to control the direction of the magnetic moment of the nanomagnet. Compared with the current induction scheme, this scheme has improved power consumption, but its operating frequency is relatively low; the clock control scheme based on magnetoelastic properties uses a piezoelectric multiferroic structure with magnetoelastic properties to control the direction of the magnetic moment of the magnet. Theoretically, this scheme has improved power consumption and operating frequency compared to the first two schemes. However, this scheme requires a very low aspect ratio of the nanomagnet, and many characteristics of NML depend on the aspect ratio of the nanomagnet, which will affect the performance and reliability of the NML circuit. In addition, this clock control solution has very high requirements on the manufacturing process and is difficult to implement under current process conditions. Summary of the invention

[0004] The present invention provides a nanomagnetic logic majority logic gate circuit based on a magnetoelectric effect clock control method to overcome the above technical problems.

[0005] A nanomagnetic logic majority logic gate circuit based on a magnetoelectric effect clock control method, the nanomagnetic logic majority logic gate circuit comprising: a first input terminal A, a second input terminal B, a third input terminal C, an input interface circuit, an intermediate operation circuit M, a first output terminal F, a second inverter a4 and a second output terminal F ′ ;

[0006] The intermediate operation circuit M includes a plurality of first inverters a1, a first two-input AND gate a21, a second two-input AND gate a22, a third two-input AND gate a23, and a three-input OR gate a3;

[0007] The first input end of the first two-input AND gate a21 is connected to the second input end B; the second input end of the first two-input AND gate a21 is connected in series with the first inverter a1 and connected to the first input end A; the output end of the first two-input AND gate a21 serves as the first input end of the three-input OR gate a3;

[0008] The first input end of the second two-input AND gate a22 is connected in series with the first inverter a1 and connected to the third input end C; the second input end of the second two-input AND gate a22 is connected to the second input end B; the output end of the second two-input AND gate a22 serves as the second input end of the three-input OR gate a3;

[0009] The first input end of the third two-input AND gate a23 is connected in series with the first inverter a1 and connected to the third input end C; the second input end of the third two-input AND gate a23 is connected in series with the inverter a1 and connected to the first input end A; the output end of the third two-input AND gate a23 serves as the third input end of the three-input OR gate a3;

[0010] The output end of the three-input OR gate a3 is the first output end F;

[0011] The three-input OR gate a3 is connected in series with the second inverter a4, with the first output terminal F serving as the input terminal of the second inverter a4 and the output terminal of the second inverter a4 serving as the second output terminal F. ′ .

[0012] Furthermore, the nanomagnetic logic majority logic gate circuit structure includes: an input layer, a free layer, a magnetoelectric layer, a metal wire and a substrate;

[0013] The input layer includes a first input terminal A layer, a second input terminal B layer and a third input terminal C layer; the free layer includes an intermediate operation circuit M layer of a majority logic gate, a first output terminal F layer and a second output terminal F layer. ′ layer;

[0014] The first input terminal A layer, the second input terminal B layer, the third input terminal C layer, the intermediate operation circuit M layer, the first output terminal F layer and the second output terminal F layer ′ The layers are all deposited on the substrate;

[0015] The first input terminal A layer and the third input terminal C layer are arranged on two opposite sides of the intermediate operation circuit M layer; the second input terminal B layer is arranged on one side of the intermediate operation circuit M layer adjacent to the first input terminal A layer; the first output terminal F layer is arranged on the other side of the intermediate operation circuit M layer opposite to the second input terminal B layer; the second output terminal F ′ The layer is arranged at the side of the first output terminal F layer away from the intermediate operation circuit M layer;

[0016] The magnetoelectric layer includes a plurality of magnetoelectric material blocks;

[0017] The intermediate operation circuit M layer, the first output terminal F layer and the second output terminal F ′ A layer is disposed between the substrate and the block of magneto-electric material;

[0018] The metal wires include a plurality of first metal wires and a second metal wire;

[0019] One end of the first metal wire is connected to the magneto-electric material block, and the other end is connected to the second metal wire;

[0020] The second metal line is connected to the clock control signal terminal CLK.

[0021] Furthermore, the clock signal of the clock control signal terminal CLK cycles alternately in the order of Reset, Switch, Hold, and Reset.

[0022] Furthermore, the first input terminal A layer, the second input terminal B layer, the third input terminal C layer, the intermediate operation circuit M layer, the first output terminal F layer and the second output terminal F layer are ′ The layers are nanomagnets including but not limited to rectangular or elliptical shapes.

[0023] Furthermore, the logic function of the nanomagnetic logic majority logic gate circuit is as follows:

[0024]

[0025]

[0026] Beneficial effects: The present invention is a nanomagnetic logic majority logic gate circuit based on the magnetoelectric effect clock control method. Based on the majority logic gate circuit, a clock control scheme based on the magnetoelectric effect is designed. Compared with other known clock control schemes, the clock control scheme can further reduce circuit power consumption and increase circuit speed, and the circuit structure is simple and easy to prepare. At the same time, the clock control scheme is not only applicable to majority logic gate circuits, but also can be applied to other NML circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0028] Figure 1 This is a circuit structure diagram of the nanomagnetic logic majority logic gate of the present invention;

[0029] Figure 2 It is a clock control signal waveform diagram of the nanomagnetic logic majority logic gate circuit of the present invention;

[0030] Figure 3 It is a schematic diagram of the basic structure of the NML of the nanomagnetic logic majority logic gate circuit of the present invention;

[0031] Figure 4 It is a schematic diagram of the NML majority logic gate of the nanomagnetic logic majority logic gate circuit of the present invention;

[0032] Figure 5 It is a schematic diagram of the working mechanism of the nanomagnetic logic majority logic gate circuit based on magnetoelectric effect of the present invention;

[0033] Figure 6 It is a schematic diagram of the magnetic moment conversion of the majority logic gate of the nanomagnetic logic majority logic gate circuit of the present invention;

[0034] Figure 7 This is the circuit diagram of the nanomagnetic logic majority logic gate of the present invention.

[0035] Among them: 1. input layer; 2. free layer; 3. magnetoelectric layer; 31. magnetoelectric material block; 4. metal wire; 41. first metal wire; 42. second metal wire; 5. substrate. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] This embodiment provides a nanomagnetic logic majority logic gate circuit based on a magnetoelectric effect clock control method, as shown in the attached Figure 7As shown, the nanomagnetic logic majority logic gate circuit includes: a first input terminal A, a second input terminal B, a third input terminal C, an input interface circuit, an intermediate operation circuit M, a first output terminal F, a second inverter a4 and a second output terminal F′;

[0038] The intermediate operation circuit M includes a plurality of first inverters a1, a first two-input AND gate a21, a second two-input AND gate a22, a third two-input AND gate a23, and a three-input OR gate a3;

[0039] The first input end of the first two-input AND gate a21 is connected to the second input end B; the second input end of the first two-input AND gate a21 is connected in series with the first inverter a1 and connected to the first input end A; the output end of the first two-input AND gate a21 serves as the first input end of the three-input OR gate a3;

[0040] The first path of the second two-input AND gate a22 is connected in series with the first inverter a1 and connected to the third input terminal C; the second input terminal of the second two-input AND gate a22 is connected to the second input terminal B; the output terminal of the second two-input AND gate a22 serves as the second input terminal of the three-input OR gate a3;

[0041] The first input end of the third two-input AND gate a23 is connected in series with the first inverter a1, with the third input end C as the input end; the second input end of the third two-input AND gate a23 is connected in series with the inverter a1, with the first input end A connected; the output end of the third two-input AND gate a23 serves as the third input end of the three-input OR gate a3;

[0042] The output end of the three-input OR gate a3 is the first output end F;

[0043] The three-input OR gate a3 is connected in series with the second inverter a4, and the first output terminal F thereof serves as the input terminal of the second inverter a4, and the output terminal of the second inverter a4 serves as the second output terminal F. ′ .

[0044] The nanomagnetic logic majority logic gate circuit structure comprises: an input layer 1, a free layer 2, a magnetoelectric layer 3, a metal wire 4 and a substrate 5, as shown in the attached Figure 1 As shown;

[0045] The input layer 1 includes a first input terminal A layer, a second input terminal B layer and a third input terminal C layer;

[0046] The free layer 2 includes an intermediate operation circuit M layer of a majority logic gate, a first output terminal F layer and a second output terminal F layer. ′ layer;

[0047] The first input terminal A layer, the second input terminal B layer, the third input terminal C layer, the intermediate operation circuit M layer, the first output terminal F layer and the second output terminal F ′ The layers are all deposited on a substrate 5;

[0048] Wherein, the first input terminal A layer and the third input terminal C layer are arranged on two opposite sides of the intermediate operation circuit M layer; the second input terminal B layer is arranged on one side of the intermediate operation circuit M layer adjacent to the first input terminal A layer; the first output terminal F layer is arranged on the other side of the intermediate operation circuit M layer opposite to the second input terminal B layer; the second output terminal F′ layer is arranged on the side of the first output terminal F layer away from the intermediate operation circuit M layer;

[0049] The magneto-electric layer 3 includes a plurality of magneto-electric material blocks 31;

[0050] The intermediate operation circuit M layer, the first output terminal F layer and the second output terminal F ′ The layers are all stacked on the substrate 5; and are arranged between the substrate 5 and the magneto-electric material block 31;

[0051] The metal wire 4 includes a plurality of first metal wires 41 and second metal wires 42;

[0052] One end of the first metal wire 41 is connected to the magneto-electric material block 31 , and the other end is connected to the second metal wire 42 ;

[0053] The second metal line 42 is connected to the clock control signal terminal CLK.

[0054] The waveform of the clock control signal CLK is as follows: Figure 2 As shown, it can be divided into three stages, namely Reset, Switch and Hold, and the clock signal appears alternately in the order of Reset→Switch→Hold→Reset.

[0055] Preferably, the time for the free layer magnetic moment to switch from a metastable state to a stable state under the action of the adjacent nanomagnet dipole field is generally in the nanosecond order. In addition, the operating voltage of the magnetoelectric layer is generally less than 1V. Therefore, it is assumed that the voltage amplitude applied to the magnetoelectric layer is 0.1V, and the duration of the three stages of the clock signal is 2ns. In an actual circuit, the operating voltage and signal cycle change accordingly depending on the material and size of the circuit. In addition, the time for the magnetoelectric effect to flip the magnetic moment is much smaller than the time for the nanomagnet dipole field to flip the magnetic moment, generally only in the picosecond order. Therefore, this embodiment reduces the duration of the Reset stage to the picosecond order, which can further increase the clock frequency.

[0056] like Figure 2 As shown, the majority logic gates are Figure 2The schematic diagram of the conversion of the magnetic moment direction under the action of the clock signal is shown in Figure 6 As shown, assuming that all three input layers are logical '1', then

[0057] Reset stage: At this time, the voltage applied to the magnetoelectric layer is at a high level. Due to the magnetoelectric effect, the direction of the magnetic moment of the nanomagnet is turned from the long axis (y-axis direction) to the short axis (x-axis direction), and the free layers of most logic gates are in the 'Null' state.

[0058] Switch stage: At this time, the voltage applied to the magnetoelectric layer gradually decreases from a high level to zero. The magnetoelectric effect gradually weakens. Since the magnetic moment of the input layer remains unchanged, the magnetic moment of the free layer gradually changes from the 'Null' state to the '0' state or the '1' state under the action of the dipole field of the adjacent nanomagnet. This stage can be divided into three sub-stages, namely, Figure 6 The first is the Switch1 stage. At this time, since the free layer M is closest to the three input layers, it is most affected by the dipole field and first changes from the 'Null' state to the '1' state; in the Switch2 stage, the free layer F changes from the 'Null' state to the '0' state under the action of the dipole field of the input layer and the leftmost free layer; in the Switch3 stage, the free layer F' changes from the 'Null' state to the '1' state under the action of the dipole field of the input layer and other free layers, and finally realizes the majority logic function.

[0059] Hold stage: At this time, the voltage on the magnetoelectric layer is zero, and the input signal is converted from the original logic '1' to logic '0'. The magnetic moment of the free layer remains unchanged in the state of the Switch3 stage.

[0060] The first input terminal layer A, the second input terminal layer B, the third input terminal layer C, the intermediate operation level layer M, the first output terminal layer F and the second output terminal layer F ′ The nanomagnets include but are not limited to rectangular or elliptical nanomagnets.

[0061] Preferably, since the elongated nanomagnet has obvious shape anisotropy, it is easy to achieve bistability, so it can be used to construct basic logic devices. The nanomagnetic logic (Nanomagnet Logic, NML) structure in this embodiment is usually composed of rectangular or elliptical nanomagnets. The basic NML structure is as follows: Figure 3 As shown in the attached Figure 3 In the coordinate system, the y-axis is the easy magnetization axis, the x-axis is the hard magnetization axis, and the arrow indicates the direction of the magnetic moment. The positive and negative directions of the easy magnetization axis are the two stable states of the nanomagnet, which can be used to represent logic '0' and '1' respectively, while the direction of the hard magnetization axis is the metastable state of the magnet, defined as the 'Null' state.

[0062] In the NML circuit of the present invention, the basic logic gate is a majority logic gate, such as Figure 4 shown.

[0063] Among them, the first input end layer A, the second input end layer B, and the third input end layer C of the rectangular parallelepiped magnet as the input layer have their magnetic moment directions fixed; the middle operation level layer M, the first output end layer F, and the second output end layer F of the rectangular parallelepiped magnet majority logic gate as the free layer ′ , the direction of its magnetic moment changes accordingly with the change of the surrounding magnetic field. The nanomagnetic logic majority logic gate circuit can realize the majority logic function, and its logic function is as follows:

[0064]

[0065]

[0066] If the second input layer B is fixed to logic '0', then It can realize the "NOR" and "OR" logical relationship. If the second input terminal layer B is fixed to the logic and '1', then Then the logical relationship of "AND NOT" and "AND" can be realized.

[0067] Specifically, in order to allow the free layer magnet to flip from one stable state to another, the magnetoelectric effect has extremely low power consumption and extremely high speed in terms of magnetic moment flipping, and its power consumption can be as low as 10 -18 Joules, and the switching speed can reach 50 picoseconds, so this embodiment uses the magnetoelectric effect to assist the magnetic moment reversal, as follows:

[0068] First, a magnetoelectric layer is superimposed on the free layer. When a voltage is applied to the magnetoelectric layer, due to the magnetoelectric effect, the magnetic moment of the free layer will flip from the original y-axis direction to the x-axis direction, that is, from the '0' state or '1' state to the 'Null' state. When the voltage on the magnetoelectric layer is removed, the magnetic moment of the free layer will flip to the '0' state or '1' state according to the state of the surrounding magnets, thereby realizing the corresponding logical function. Figure 5 A schematic diagram of the working mechanism of the magnetoelectric effect is given, in which the arrows indicate the direction of the magnetic moment of the magnet.

[0069] The nanomagnetic logic majority logic gate circuit based on the magnetoelectric effect clock control scheme proposed by the present invention, that is, the NML circuit clock control scheme based on the magnetoelectric effect, has great improvements in power consumption and speed in terms of flipping magnetic moment. At the same time, due to the high efficiency of the magnetoelectric effect in flipping magnetic moment, it has no strict requirements on the aspect ratio of the nanomagnet, and the magnetoelectric effect clock control scheme is also feasible from the manufacturing process. Therefore, the magnetoelectric effect NML circuit clock control scheme of the present invention can greatly improve the performance of the NML circuit, making the NML circuit more competitive as a candidate in the post-CMOS era.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A nanomagnetic logic majority logic gate circuit based on a magnetoelectric effect clock control method, characterized in that: The nanomagnetic logic majority logic gate circuit comprises: a first input terminal A, a second input terminal B, a third input terminal C, an input interface circuit, an intermediate operation circuit M, a first output terminal F, a second inverter a4 and a second output terminal F ′ ; The intermediate operation circuit M includes a plurality of first inverters a1, a first two-input AND gate a21, a second two-input AND gate a22, a third two-input AND gate a23, and a three-input OR gate a3; The first input end of the first two-input AND gate a21 is connected to the second input end B; the second input end of the first two-input AND gate a21 is connected in series with the first inverter a1 and connected to the first input end A; the output end of the first two-input AND gate a21 serves as the first input end of the three-input OR gate a3; The first input end of the second two-input AND gate a22 is connected in series with the first inverter a1 and connected to the third input end C; the second input end of the second two-input AND gate a22 is connected to the second input end B; the output end of the second two-input AND gate a22 serves as the second input end of the three-input OR gate a3; The first input end of the third two-input AND gate a23 is connected in series with the first inverter a1 and connected to the third input end C; the second input end of the third two-input AND gate a23 is connected in series with the inverter a1 and connected to the first input end A; the output end of the third two-input AND gate a23 serves as the third input end of the three-input OR gate a3; The output end of the three-input OR gate a3 is the first output end F; The three-input OR gate a3 is connected in series with the second inverter a4, with the first output terminal F serving as the input terminal of the second inverter a4 and the output terminal of the second inverter a4 serving as the second output terminal F. ′ picture; The structure of the nanomagnetic logic majority logic gate circuit comprises: an input layer (1), a free layer (2), a magnetoelectric layer (3), a metal wire (4) and a substrate (5); The input layer (1) includes a first input terminal A layer, a second input terminal B layer and a third input terminal C layer; the free layer (2) includes an intermediate operation circuit M layer of a majority logic gate, a first output terminal F layer and a second output terminal F layer. ′ layer; The first input terminal A layer, the second input terminal B layer, the third input terminal C layer, the intermediate operation circuit M layer, the first output terminal F layer and the second output terminal F layer ′ The layers are deposited on a substrate (5); The first input terminal A layer and the third input terminal C layer are arranged on two opposite sides of the intermediate operation circuit M layer; the second input terminal B layer is arranged on one side of the intermediate operation circuit M layer adjacent to the first input terminal A layer; the first output terminal F layer is arranged on the other side of the intermediate operation circuit M layer opposite to the second input terminal B layer; the second output terminal F ′ The layer is arranged at the side of the first output terminal F layer away from the intermediate operation circuit M layer; The magnetoelectric layer (3) comprises a plurality of magnetoelectric material blocks (31); The intermediate operation circuit M layer, the first output terminal F layer and the second output terminal F ′ The layer is arranged between the substrate (5) and the magneto-electric material block (31); The metal wire (4) comprises a plurality of first metal wires (41) and second metal wires (42); One end of the first metal wire (41) is connected to the magneto-electric material block (31), and the other end is connected to the second metal wire (42); The second metal line (42) is connected to the clock control signal terminal CLK.

2. The nanomagnetic logic majority logic gate circuit based on the magnetoelectric effect clock control method according to claim 1, characterized in that: The clock signal of the clock control signal terminal CLK cycles alternately in the order of Reset, Switch, Hold, and Reset.

3. The nanomagnetic logic majority logic gate circuit based on the magnetoelectric effect clock control method according to claim 1, characterized in that: The first input terminal A layer, the second input terminal B layer, the third input terminal C layer, the intermediate operation circuit M layer, the first output terminal F layer and the second output terminal F layer ′ The layers are nanomagnets including but not limited to rectangular or elliptical shapes.

4. The nanomagnetic logic majority logic gate circuit based on the magnetoelectric effect clock control method according to claim 1, characterized in that: The logic function of the nanomagnetic logic majority logic gate circuit is as follows:

Images