Improved data reliability in data storage for extreme temperature usage conditions

Abstract

The present application relates to improved data reliability for extreme temperature usage conditions in data storage. Systems, methods, and apparatus are related to memory devices, such as solid-state drives. In one method, data (e.g., data to be written to an SSD) is received from a host system. The received data is encoded using a first error correction code to generate first parity data. A temperature at which a memory cell of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in a memory storage device that is prone to errors at a predicted higher temperature determined based on output from an artificial neural network using sensor inputs). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cell of the storage device.

Description

Technical Field

[0001] At least some embodiments disclosed herein relate generally to memory devices, and more particularly, but not limited to, improved data reliability for data storage at high temperatures. Background Art

[0002] Various types of non-volatile storage devices can be used to store data. Non-volatile storage devices can include NAND flash memory devices. NAND flash is a type of flash memory constructed using NAND logic gates.

[0003] Solid-state drives are an example of non-volatile data storage devices that use solid-state memory to store data, such as non-volatile NAND-based flash memory chips. NAND-based flash memory is generally reliable, but does not store data error-free. In some cases, error correction codes are used to correct raw bit errors in the stored data.

[0004] Errors in data storage can occur for a variety of reasons. For example, errors can be caused by noise on the power rails, voltage threshold disturbances during reading or writing of adjacent cells, or retention loss due to leakage within the cell.

[0005] If an error is detected, error correction codes are typically used in flash memory to recover the stored data. In one example, the error correction code supplements the user data with parity bits that store additional information, making it possible to recover the data if one or more data bits are damaged. Generally speaking, the number of data bit errors that can be corrected in the stored data increases as the number of erroneous bits in the error correction code increases.

[0006] In a memory device, user data is stored in a memory location of the memory device along with an error correction code for the data. This allows the data and error correction code to be written to the memory location in a single write operation, or read from the memory location in a single read operation. Typically, the error correction code is implemented in the flash memory controller.

[0007] In one example, the error correction code generates parity bits that are stored with the user data. In various examples, the error correction code is based on a Hamming coding scheme, a Reed-Solomon coding scheme, a Turbo coding scheme, or a Low Density Parity Check (LDPC) coding scheme. Summary of the Invention

[0008] In one aspect, the present application provides a method comprising: receiving data from a host system; encoding the received data using a first error correction code to generate first parity data; determining a temperature at which a memory unit will store the received data; identifying at least a first portion of the received data based on the determined temperature; encoding the first portion of the received data using a second error correction code to generate second parity data, wherein the second error correction code has a higher error correction capability than the first error correction code; and storing the first portion, the first parity data, and the second parity data in the memory unit.

[0009] On the other hand, the present application provides a system comprising: a storage device configured to store data from a host system; and at least one processing device configured to: receive first data from the host system; encode the first data using a first error correction code to generate first parity data; determine at least one of a temperature at which the storage device will store the first data or a storage time for which the storage device will store the first data; identify at least a first portion of the first data based on at least one of the temperature or the storage time; encode the first portion of the first data using a second error correction code to generate second parity data, wherein the second error correction code has a higher error correction capability than the first error correction code; and store the first portion, the first parity data, and the second parity data in the storage device.

[0010] On the other hand, the present application provides a non-transitory computer-readable medium storing instructions that, when executed in a memory subsystem, cause the memory subsystem to perform a method comprising: receiving first data from a host system; encoding the first data using a first error correction code to generate first parity data; determining that a storage device configured to store data received from the host system will stop receiving power from a power supply; in response to determining that the storage device will stop receiving power from the power supply, identifying at least a first portion of the first data; encoding the first portion using a second error correction code to generate second parity data, wherein the second error correction code has a higher error correction capability than the first error correction code; and storing the first portion, the first parity data, and the second parity data in the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like reference numerals indicate similar elements.

[0012] Figure 1A storage device that encodes stored data using two levels of parity data is described in accordance with some embodiments.

[0013] Figure 2 A vehicle is described that uses two layers of error correction coding to store data for a control system of the vehicle, according to some embodiments.

[0014] Figure 3 A storage device that encodes stored data based on monitoring a power supply according to some embodiments is described.

[0015] Figure 4 A method for encoding data received from a host system using two different error correction codes is presented in accordance with some embodiments.

[0016] Figure 5 A method is presented for identifying data to be stored using two layers of encoding / decoding based on determining the temperature at which the data is stored in a storage device, according to some embodiments.

[0017] Figure 6 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0018] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0019] The following disclosure describes various embodiments for improving data reliability for data storage at high temperatures. At least some embodiments herein relate to data stored in a flash memory device based on encoding the data using two levels of parity protection. The memory device may, for example, store data for use by a host device (e.g., a computing device in an autonomous vehicle, or another computing device that accesses data stored in the memory device). In one example, the memory device is a solid-state drive installed in an electric vehicle.

[0020] In some cases, data may be stored at high temperatures. In other cases, data may be stored for long periods of time without power. In either case, the risk of data loss increases (e.g., due to bit corruption). In one example, data is stored in a device that will undergo high-temperature reflow (e.g., for an automobile). In another example, data may be stored in a device that will be placed in a storage facility or location for a long period of time, such as a vehicle parked in storage for a long period of time (e.g., in a parking lot), or after a product is manufactured and in storage awaiting physical transportation or other further use in manufacturing. These different situations present a technical problem in that the stored data is prone to errors, which may undermine the usefulness of the data.

[0021] Various embodiments of the present disclosure provide technical solutions to the above technical problems by using two-level parity protection for stored data. In one embodiment, higher error correction code (ECC) protection is achieved by creating second-level parity data (e.g., a second set of parity bits) among several codewords that have been parity protected (e.g., by first-level parity data, such as a first set of parity bits). One advantage is that the second-level parity protection provides better error correctability than the first-level parity protection. When two-level parity protection is used (e.g., when the device is operating in the field), the use of two-level parity protection provides the advantage of a higher level of protection against data corruption than provided by ordinary ECC.

[0022] More robust error correction typically requires more processing power to correct errors. In many cases, the first level of parity correction is implemented in hardware, optionally assisted by firmware. In many cases, the second level of parity protection can be implemented in software, possibly assisted by another computing system (e.g., a host server) that has significantly more processing power than the storage device (e.g., an SSD) storing the data for the computing system.

[0023] In one embodiment, a method includes: receiving data from a host system; encoding the received data using a first error correction code to generate first parity data; determining a temperature at which a memory cell will store the received data; identifying at least a first portion of the received data based on the determined temperature; encoding the first portion of the received data using a second error correction code to generate second parity data, wherein the second error correction code has a higher error correction capability than the first error correction code; and storing the first portion, the first parity data, and the second parity data in the memory cell.

[0024] For example, the temperature determined above may be a predicted temperature at which data will be stored at a future time. In one example, the future time is a predetermined time (e.g., a time at which future high temperature exposure will occur during operation of the system or during product manufacturing). In one example, the prediction is made using an artificial neural network or other machine learning model.

[0025] In some embodiments, alternative and / or additional determinations can be made that the data will be stored for an extended period of time without power. In one example, a determination is made that the data will be stored for a predetermined period of time (e.g., for a period of time exceeding 5 to 60 days or for a period of time exceeding 24 hours). In some embodiments, a determination is made that the storage device will be exposed to high temperatures and stored without power for a predetermined period of time. In response to all such situations, the data can be stored using the second level parity protection described herein.

[0026] In some cases, data to be stored at the second level of parity protection is specifically identified. For example, the identified data may be critical data necessary for the operation of a computing system or machine, or data that cannot be easily replaced or obtained from other sources if lost. In one example, the identified data may be sent from the storage device to a host system with more processing resources for additional processing to implement the second level of parity protection on the storage device before high temperatures or extended storage times occur.

[0027] Data that is not specifically identified, such as less critical data (e.g., music media for an entertainment system), need not be stored at the second level of parity protection. However, less critical data may be stored at the second level of parity protection when needed, such as when sufficient energy or processing resources are available and / or sufficient time is available to perform processing for the second level of parity protection before entering a high temperature or extended storage time scenario.

[0028] In some embodiments, errors occur between storing data in a memory cell (e.g., a memory cell used as a storage medium in a non-volatile memory chip of an SSD) and retrieving the data from the memory cell. To facilitate retrieval of error-free data, a memory subsystem (e.g., as used in an SSD) may encode data received from a host system using an error correction code (ECC) such as a low-density parity check (LDPC) code and store the encoded data in the memory cell. Decoding the encoded data retrieved from the memory cell may remove or reduce errors.

[0029] In one example, the error rate distribution is uneven across multiple memory pages in different programming modes and / or across word lines in flash memory. For example, a memory subsystem may include pages programmed in single-level cell (SLC) mode, multi-level cell (MLC) mode, triple-level cell (TLC) mode, quad-level cell (QLC) mode, and the like. When configured in SLC mode, each memory cell in a page stores one bit of data. When configured in MLC mode, each memory cell in a page stores two bits of data. When configured in TLC mode, each memory cell in a page stores three bits of data. When configured in QLC mode, each memory cell in a page stores four bits of data. As the number of bits stored in a cell increases, the likelihood of errors in the data retrieved from the cell increases.

[0030] In one example, a block of a memory device may have most of its memory cells in QLC mode and some memory cells in SLC mode and / or TLC mode. When programming memory cells in QLC mode using LP, MP, UP, and XP pages using a multi-pass programming technique, decoding of the LP page is similar to decoding of the page in SLC mode with the highest signal-to-noise ratio (S / N) and the lowest bit error rate (BER). Decoding of the MP and UP pages is similar to decoding of the page in TLC mode with a medium S / N ratio and a medium BER. Decoding of the XP page is similar to decoding of the page in QLC mode with the lowest S / N ratio and the highest BER.

[0031] In some embodiments, two layers of encoding can be used to handle non-uniform error rate distributions across pages with different programming modes. For example, the two layers of encoding can include a first layer of LDPC codes configured according to a nominal bit error rate (e.g., 0.005) rather than a worst-case bit error rate (e.g., 0.01). The second layer of erasure codes is configured to span codewords in pages with different programming modes (e.g., SLC, MLC, TLC, QLC). For example, the symbol size of the erasure code used in the second layer can be 16 bytes. In one example, the first layer can use 4K LDPC with a code rate of 0.9, such that the ratio between the LDPC payload size and the LDPC codeword size is 0.9.

[0032] Figure 1 A storage device 101 (e.g., an SSD or NAND-based flash memory chip or module) is illustrated that uses two levels of parity data to encode stored data according to some embodiments. Storage device 101 receives data to be stored from host system 127 (e.g., via a serial communication interface or a wireless communication interface). Storage device 101 stores the received data in memory unit 103. In one example, memory unit 103 can be provided by one or more non-volatile memory chips. In one example, the memory chip is a NAND-based flash memory.

[0033] Storage device 101 implements error correction using error correction code 123 and error correction code 125. Error correction code 125 has a higher error correction capability than error correction code 123. When receiving data from host system 127, the received data is encoded using error correction code 123 to provide parity data 115. Some or all of the received data is also encoded using error correction code 125 to provide parity data 117 and / or parity data 119. Processing device 121 may be configured to implement the error correction codes in hardware and / or software.

[0034] In some cases, only a portion of the received data is encoded using both error correction codes. In one example, encoding using the second error correction code is limited when processing resources are limited. In one example, processing resources may be limited due to reduced central processing power, reduced working memory availability, and / or a limited power supply.

[0035] Where only a portion of the received data is encoded using the second error correction code, the portion of the received data to be encoded using both error correction codes is identified. In one example, the portion of the data is identified based on the temperature at which the received data is to be stored and the criticality of the data.

[0036] In one embodiment, if it is determined that the storage device 101 will be exposed to high temperatures, then the identified portion of data to be encoded using the second error correction code 125 is determined based on identifying the data most susceptible to high temperatures. In one example, this data is data stored using one or more programming modes in which more than one data bit is stored in each memory cell. In one example, such data is stored using MLC, TLC, and / or QLC modes.

[0037] In one example, the determined temperature is at least 35 degrees Celsius. In one example, the determined temperature is 50 degrees Celsius or higher.

[0038] In one embodiment, data 109 is received from a host system 127. Data 109 includes a portion 111 stored in cell 105 in SLC mode and a portion 113 stored in cell 107 (e.g., in MLC, TLC, and / or QLC mode). Upon receipt, data 109 is encoded using an error correction code 123 to generate parity data 115. Parity data 115 may be stored in memory cell 103 along with the corresponding data portion.

[0039] In one embodiment, portion 113 of data 109 is identified as being more prone to errors when stored at a high temperature. In response to a prediction of a future high temperature (e.g., a temperature above a predetermined threshold), portion 113 is encoded using a second error correction code 125 to generate parity data 119. Parity data 119 may be stored in unit 107 along with the corresponding encoded data.

[0040] In some embodiments, portion 111 may also be encoded using error correction code 125 to produce parity data 117. Parity data 117 may be stored with the corresponding encoded data in unit 105. For example, portion 111 may be encoded using error correction code 125 based on a determination that processing resources and / or power resources are above a predetermined threshold, and / or other factors indicative of the sufficiency or increased availability of such resources.

[0041] In one embodiment, data is read from memory unit 103 after it has been stored. When reading the data (e.g., in response to receiving a read command), the processing capabilities of host system 127 are determined by processing device 121. For example, processing device 121 may determine that host system 127 has processing resources that exceed a predetermined threshold. In response to this determination, processing device 121 sends portion 113 and parity data 119 to host system 127 for decoding using error correction code 125 (which has higher error correction capabilities but requires more processing resources than ECC 123).

[0042] In one embodiment, host system 127 itself is capable of storing data using two levels of parity protection. Specifically, host system 127 implements error correction code 141 and error correction code 143. Error correction code 143 has a higher error correction capability than error correction code 141. In one example, error correction code 141 is the same as error correction code 123, and error correction code 143 is the same as error correction code 125.

[0043] In one example, system 127 stores data 129, which includes portions 131 and 133, each of which is encoded using error correction code 141 to provide parity data 135. In response to a prediction of high temperatures in future operation of host system 127, portion 133 is identified as critical data (e.g., a basic software program for controlling vehicle navigation or braking). Portion 133 is encoded using error correction code 143 to provide parity data 139. Optionally, portion 131 can be encoded using error correction code 143 to provide parity data 137.

[0044] In one embodiment, in response to determining a temperature at which data associated with increased data storage errors is to be stored, host system 127 sends identified portion 133 to storage device 101 for storage in memory unit 103 .

[0045] In one example, portion 133 is sent to storage device 101 along with parity data 135, 139. Upon receipt, processing device 121 encodes portion 133 using error correction code 125 to provide parity data 119. Received portion 133 and parity data 119, 135, and / or 139 are stored in memory unit 105 or memory unit 107.

[0046] Figure 2 A vehicle 245 is illustrated using two levels or layers of error correction coding according to some embodiments to store data for a control system 227 of the vehicle 245. A first layer of error correction coding is provided by ECC 123, and a second layer of error correction coding is provided by ECC 125.

[0047] The control system 227 controls various vehicle functions 251 of the vehicle 245. In one example, the vehicle functions 251 include motor control, navigation control, and / or control of other hardware of the vehicle 245 that operates functions when the vehicle 245 is used by an operator (e.g., a driver or a passenger). The control system 227 stores data 129 used to control the vehicle functions 251.

[0048] Control system 227 can send at least a portion of data 129 to storage device 101 for storage. For example, a portion of data 129 is sent as data 109, which is received by controller 221 from control system 227 and stored in memory unit 103. Data 109 is encoded using ECC 123 and ECC 125 to provide parity data 115, 117, 119.

[0049] In one embodiment, controller 221 uses sensor 247 to determine the temperature of storage device 101. The signaling provided by sensor 247 is used by controller 221 as input to a machine learning model 249 (e.g., an artificial neural network). The output from machine learning model 249 is used to predict the temperature at which storage device 101 will operate in the future. Based on this prediction, controller 221 identifies data stored in memory unit 103 that is additionally encoded using error correction code 125.

[0050] In some cases, the identified data may be sent to the control system 227 for processing using the error correction code 125 (e.g., for either or both of encoding and decoding by the control system 227). The identified data processed at the control system 227 may be stored locally and / or sent to the storage device 101 for storage along with its corresponding parity data (e.g., portion 113 and parity data 119).

[0051] Figure 3A storage device 305 is illustrated that encodes stored data based on monitoring a power supply 303 in accordance with some embodiments. The storage device 305 is an example of the storage device 101. The storage device 305 includes a storage medium 307 (e.g., a memory cell in an integrated circuit die) that stores data 323 received by a processing device 325 from a host system 301. The host system 301 is an example of the host system 127 or the control system 227.

[0052] Data 323 is received from host system 301 and encoded using error correction code 319 to provide parity data 313. In one example, all data received from host system 301 is encoded using error correction code 319.

[0053] In one embodiment, processing device 325 monitors the availability of power from power supply 303. Processing device 325 determines, based on signaling from power supply 303 and / or host system 301, that the available power from power supply 303 will fall below a predetermined threshold. In one example, the determination is made that the supply voltage from power supply 303 will fall below a predetermined voltage. In one example, this determination is made by host system 301, which monitors power supply 303 and sends signaling to processing device 325. Power supply 303 supplies power to storage device 305 and / or host system 301.

[0054] In response to a determination made based on monitoring power supply 303, as described above, portion 311 of data 323 is identified as critical data. Portion 311 is encoded using error correction code 321 having a higher error correction capability than error correction code 319 to provide parity data 317. Portion 311 and parity data 317 are stored in storage medium 307.

[0055] Optionally, portion 309 may also be encoded using an error correction code 321 to provide parity data 315. Portion 309 and parity data 315 are stored in storage medium 307 (eg, in a QLC memory cell).

[0056] Figure 4 Methods for encoding data received from a host system using two different error correction codes to implement two levels of parity protection are presented according to some embodiments. For example, Figure 4 The method can be found in Figure 1 In one example, the error correction codes are ECC 123 and ECC 125. In one example, the host system is host system 127 or control system 227.

[0057] Figure 4The method may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, Figure 4 The method is at least partially performed by one or more processing devices (eg, processing device 121 or controller 221).

[0058] Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0059] At block 401 , data is received from a host system. In one example, the received data is data 109 or data 323 .

[0060] At block 403, the received data is encoded using a first error correction code to generate first parity data. In one example, the data 109 is encoded using ECC 123 or ECC 319.

[0061] At block 405, a temperature is determined at which a memory unit will store the received data. In one example, the temperature is determined using sensor 247 based on a predicted temperature provided as an output from machine learning model 249. In one example, the memory unit is memory unit 103 or a memory unit of storage media 307.

[0062] At block 407, a portion of the received data is identified based on the determined temperature. In one example, portion 113 or portion 311 is identified.

[0063] At block 409, the identified portion of the data is encoded using a second error correction code to generate second parity data. In one example, portion 113 or portion 311 is encoded using ECC 125 or ECC 321.

[0064] At block 411 , the identified portion of data is stored in a memory cell along with first and second parity data. In one example, the first parity data is parity data 115 and the second parity data is parity data 119 .

[0065] Figure 5 A method for identifying data to be stored using two layers of encoding / decoding based on determining the temperature at which the data is stored in a storage device according to some embodiments is presented. For example, Figure 5 The method can be found in Figure 2 In one example, the temperature is the ambient temperature of the memory device 101, or the temperature of the memory unit 103 inside the memory device 101 (eg, the surface temperature of a memory die or a printed circuit board).

[0066] Figure 5 The method may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, Figure 5 The method is at least partially performed by one or more processing devices (e.g., controller 221).

[0067] Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0068] At block 501 , temperature data is received from a sensor of the vehicle and used as input to a machine learning model. In one example, the sensor is sensor 247 and the machine learning model is machine learning model 249 .

[0069] At block 503 , a temperature at which a memory cell will store data is determined based on output from the machine learning model. In one example, the memory cell is memory cell 103 or a memory cell of storage media 307 .

[0070] At block 505 , data is received from a control system of the vehicle. The received data is encoded using a first error correction code to generate first parity data. In one example, the control system is the control system 227 or the host system 301 .

[0071] At block 507, a portion of the received data is identified based on the determined temperature. The identified portion is encoded using a second error correction code to generate second parity data. In one example, portion 311 is identified and encoded using error correction code 321 to provide parity data 317.

[0072] At block 509, the identified portion of the data is stored in the memory cell along with the first parity data and the second parity data. In one example, the first parity data is parity data 115 and the second parity data is parity data 119 (and / or parity data 117).

[0073] At block 511 , at least one function of the vehicle is controlled based on the data stored in the memory unit. In one example, the function is vehicle function 251 , the operation of which is configured by control system 227 using data from portion 113 or portion 111 .

[0074] In one embodiment, a method for a memory device includes: receiving data from a host system (e.g., host system 127, control system 227, or host system 301); encoding the received data using a first error correction code (e.g., ECC 123) to generate first parity data; determining a temperature at which a memory cell will store the received data; identifying at least a first portion of the received data based on the determined temperature; encoding the first portion of the received data using a second error correction code (e.g., ECC 125) to generate second parity data, wherein the second error correction code has a higher error correction capability than the first error correction code; and storing the first portion, the first parity data, and the second parity data in a memory cell.

[0075] In one embodiment, encoding the received data using the first error correction code includes: splitting the received data into data units according to a predetermined size of the payload; and encoding each corresponding data unit of the payload size using the first error correction code to generate first parity data.

[0076] In one embodiment, the memory cells include a first cell (e.g., cell 105) programmed in a single-level cell (SLC) mode and a second cell (e.g., cell 107) programmed in at least one of a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, or a quad-level cell (QLC) mode.

[0077] In one embodiment, the first portion of the received data is stored in the second unit.

[0078] In one embodiment, encoding the first portion of the received data using the second error correction code is performed by the host system.

[0079] In one embodiment, the host system is a control system of a vehicle (eg, vehicle 245 ), and the control system is configured to control at least one function of the vehicle based on the data stored in the memory unit.

[0080] In one embodiment, the method further includes selecting an error correction capability of the second error correction code based on the determined temperature.

[0081] In one embodiment, the determined temperature is a current temperature associated with the storage device, and the method further includes selecting a type of the second error correction code based on the current temperature.

[0082] In one embodiment, identifying the first portion of the received data is further based on a programming mode used by the memory cell.

[0083] In one embodiment, a system includes: a storage device (e.g., storage device 101, storage device 305) configured to store data from a host system; and at least one processing device configured to: receive first data from the host system; encode the first data using a first error correction code to generate first parity data; determine at least one of a temperature at which the storage device will store the first data or a storage time for which the storage device will store the first data; identify at least a first portion of the first data based on at least one of the temperature or the storage time; encode the first portion of the first data using a second error correction code to generate second parity data, wherein the second error correction code has a higher error correction capability than the first error correction code; and store the first portion, the first parity data, and the second parity data in the storage device.

[0084] In one embodiment, the at least one processing device is further configured to: retrieve a first portion of the first data from a storage device; decode the first portion using a first error correction code; determine that the decoding was unsuccessful; and in response to determining that the decoding was unsuccessful, decode the first portion using a second error correction code.

[0085] In one embodiment, the at least one processing device is further configured to: determine that a processing capability of the host system is above a predetermined threshold; and in response to determining that the processing capability is above the predetermined threshold, send the first portion to the host system, wherein the first portion is decoded by the host system using a second error correction code.

[0086] In one embodiment, a storage device includes a controller configured to encode first data using a first error correction code.

[0087] In one embodiment, the system further includes at least one sensor (e.g., sensor 247). The temperature is determined based on output from a machine learning model (e.g., machine learning model 249), and the data collected by the sensor is input to the machine learning model. The determined temperature is a predicted temperature, and the first portion of the first data is identified based on the determined temperature.

[0088] In one embodiment, at least one sensor determines at least one of an ambient temperature of the storage device or an internal temperature of the storage device.

[0089] In one embodiment, the at least one processing device is further configured to send second parity data (e.g., parity data 119) to the host system for storage in a memory (e.g., a non-volatile memory device) of the host system; and the first portion of the first data is decoded by the host system using the second error correction code and the second parity data.

[0090] In one embodiment, a non-transitory computer storage medium stores instructions that, when executed in a memory subsystem, cause the memory subsystem to perform a method comprising: receiving first data from a host system; encoding the first data using a first error correction code to generate first parity data; determining that a storage device configured to store the data received from the host system will stop receiving power from a power supply (e.g., power supply 303); in response to determining that the storage device will stop receiving power from the power supply, identifying at least a first portion of the first data; encoding the first portion using a second error correction code to generate second parity data, wherein the second error correction code has a higher error correction capability than the first error correction code; and storing the first portion, the first parity data, and the second parity data in the storage device.

[0091] In one embodiment, the method further includes: determining that power from a power supply is available to the storage device; in response to determining that power from the power supply is available, determining that data loss has occurred in the first portion; and in response to determining that data loss has occurred in the first portion, sending the first portion to a host system. The first portion is decoded by the host system using a second error correction code.

[0092] In one embodiment, determining that data loss in the first portion has occurred includes: retrieving the first portion from a storage device; decoding the first portion using a first error correction code; and determining that the decoding was unsuccessful.

[0093] In one embodiment, the method further includes: encoding a second portion of the first data, wherein the data size of the second portion is larger than the first portion; storing the second portion in a storage device; determining a first result of decoding the first portion using a first error correction code; determining a second result of decoding the first portion using a second error correction code; comparing the first result and the second result; determining that decoding of the first portion failed based on comparing the first result and the second result; and in response to determining that decoding of the first portion failed, sending the second portion to a host system to be decoded using the second error correction code.

[0094] In one embodiment, the software error correction code is located in the cloud network. In one example, the storage device 101 sends the parity data 119 to the cloud network for decoding using one of the software error correction codes (e.g., ECC 125). In one example, the error correction code to be used for encoding and / or decoding is selected based on a temperature predicted by the storage device 101 or a temperature determined by the storage device 101. In one example, the storage device 101 communicates with the cloud network via wireless communication (e.g., 5G wireless communication via an SSD in the vehicle and an edge server located within 100 to 1,000 meters of the vehicle or within 50 to 3,000 meters of the road the vehicle is traveling).

[0095] In some embodiments, two layers of encoding are used to encode data for storage in a memory subsystem. For example, the memory subsystem may be a storage device (e.g., storage device 101), a memory module, or a mixture of a storage device and a memory module. Figure 6 Examples of storage devices and memory modules are described. Generally speaking, a host system can utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0096] Figure 6 An example computing system 700 including a memory subsystem 710 according to some embodiments of the present disclosure is illustrated. Memory subsystem 710 may include media such as one or more volatile memory devices (e.g., memory device 702), one or more non-volatile memory devices (e.g., memory device 704), or a combination thereof. Memory device 101 is an example of memory subsystem 710, and host system 127 is an example of host system 720.

[0097] The memory subsystem 710 can be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0098] The computing system 700 may be, for example, a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0099] Computing system 700 may include a host system 720 coupled to one or more memory subsystems 710 . Figure 6 An example of a host system 720 coupled to a memory subsystem 710 is illustrated.

[0100] The host system 720 may include a processor chipset (e.g., processing device 718) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., controller 716) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 720 uses the memory subsystem 710, for example, to write data to the memory subsystem 710 and read data from the memory subsystem 710.

[0101] The host system 720 can be coupled to the memory subsystem 710 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 720 and the memory subsystem 710. When the memory subsystem 710 is coupled to the host system 720 via a PCIe interface, the host system 720 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 704). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 710 and the host system 720 . Figure 1 Memory subsystem 710 is illustrated as an example. In general, host system 720 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0102] The processing device 718 of the host system 720 may be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some cases, the controller 716 may be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 716 controls communications via a bus coupled between the host system 720 and the memory subsystem 710. Generally speaking, the controller 716 may send commands or requests to the memory subsystem 710 for desired access to the memory devices 702, 704. The controller 716 may further include interface circuitry for communicating with the memory subsystem 710. The interface circuitry may convert responses received from the memory subsystem 710 into information for the host system 720.

[0103] The controller 716 of the host system 720 can communicate with the controller 715 of the memory subsystem 710 to perform operations such as reading, writing, or erasing data at the memory devices 702 and 704, and other such operations. In some cases, the controller 716 is integrated into the same package as the processing device 718. In other cases, the controller 716 is separate from the package of the processing device 718. The controller 716 and / or the processing device 718 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or a combination thereof. The controller 716 and / or the processing device 718 may be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0104] Memory devices 702 and 704 may include any combination of different types of non-volatile memory components and / or volatile memory components. Volatile memory devices (e.g., memory device 702) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0105] Some examples of non-volatile memory components include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point memory. A cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to store bits based on changes in bulk resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0106] Each of the memory devices 704 may include one or more memory cell arrays (e.g., memory cell 103). One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 704 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of memory cells, and an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory devices 704 may be grouped into pages, which may refer to logical units of the memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0107] Although non-volatile memory devices such as 3D cross-point and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, the memory device 704 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), selectable memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0108] The memory subsystem controller 715 (or simply controller 715) can communicate with the memory device 704 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 704 (e.g., in response to commands dispatched by the controller 716 on a command bus). The controller 715 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuits with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller 715 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0109] The controller 715 may include a processing device 717 (processor) configured to execute instructions stored in a local memory 719. In the illustrated example, the local memory 719 of the controller 715 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 710, including handling communications between the memory subsystem 710 and the host system 720.

[0110] In some embodiments, local memory 719 may include memory registers that store memory pointers, fetched data, etc. Local memory 719 may also include read-only memory (ROM) for storing microcode. Figure 6 The example memory subsystem 710 in FIG. 7 has been illustrated as including a controller 715, but in another embodiment of the present disclosure, the memory subsystem 710 does not include a controller 715, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0111] In general, the controller 715 may receive commands or operations from the host system 720 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 704. The controller 715 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 704.

[0112] Controller 715 may further include host interface circuitry to communicate with host system 720 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access memory device 704, and convert responses associated with memory device 704 into information for host system 720.

[0113] The memory subsystem 710 may also include additional circuits or components not illustrated. In some embodiments, the memory subsystem 710 may include a cache or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that receive addresses from the controller 715 and decode the addresses to access the memory device 704.

[0114] In some embodiments, memory device 704 includes a local media controller 705 that operates in conjunction with a memory subsystem controller 715 to perform operations on one or more memory cells of memory device 704. An external controller (e.g., memory subsystem controller 715) can externally manage memory device 704 (e.g., perform media management operations on memory device 704). In some embodiments, memory device 704 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 705) within the same memory device package that performs media management. An example of a managed memory device is a managed NAND (MNAND) device.

[0115] In one embodiment, computing system 700 includes a two-layer encoder / decoder 714 in memory subsystem 710 that uses at least two error correction codes (e.g., ECC 123, 125) to convert data and / or generate corresponding parity data for storage in media units of memory devices 702-704. In some embodiments, controller 715 in memory subsystem 710 includes at least a portion of two-layer encoder / decoder 714. In other embodiments, or in combination, controller 716 and / or processing device 718 in host system 720 include at least a portion of two-layer encoder / decoder 714. For example, controller 715, controller 716, and / or processing device 718 may include logic circuitry that implements two-layer encoder / decoder 714. For example, controller 715 or processing device 718 (processor) of host system 720 may be configured to execute instructions stored in memory for performing the operation of two-layer encoder / decoder 714.

[0116] In some embodiments, the two-layer encoder / decoder 714 is implemented in an integrated circuit chip disposed in the memory subsystem 710. In other embodiments, the two-layer encoder / decoder 714 is part of the host system 720's operating system, device driver, or application.

[0117] In some embodiments, the communication channel between the processing device 718 and the memory subsystem 710 includes a computer network, such as a local area network, a wireless local area network, a wireless personal area network, a cellular communication network, a broadband high-speed always-connected wireless communication connection (e.g., a current or future generation mobile network link); and the processing device 718 and the memory subsystem can be configured to communicate with each other using data storage management and usage commands similar to those in the NVMe protocol.

[0118] The memory subsystem 710 may typically include non-volatile storage media. Examples of non-volatile storage media include memory cells formed in integrated circuits and magnetic materials coated on rigid magnetic disks. Non-volatile storage media can maintain the data / information stored therein without consuming power. Memory cells can be implemented using various memory / storage technologies, such as NAND logic gates, NOR logic gates, phase change memory (PCM), magnetic random access memory (MRAM), resistive random access memory, cross-point memory, and memory devices. Cross-point memory devices use transistor-free memory elements, each of which has memory cells and selectors stacked together in columns. The columns of memory elements are connected via two perpendicular layers of wires, one above the columns of memory elements and the other below them. Each memory element can be individually selected at the intersection of a wire on each of the two layers. Cross-point memory devices are fast and non-volatile and can be used as a unified memory pool for processing and storage.

[0119] A controller (eg, 715) of a memory subsystem (eg, 710) may execute firmware to operate in response to communications from processing device 718. Generally speaking, firmware is a type of computer program that provides control, monitoring, and data manipulation for an engineered computing device.

[0120] Some embodiments involving the operation of controller 715 may be implemented using computer instructions executed by controller 715, such as firmware for controller 715. In some cases, hardware circuitry may be used to implement at least some of the functionality. The firmware may be initially stored in a non-volatile storage medium or another non-volatile device and loaded into volatile DRAM and / or intra-processor cache memory for execution by controller 715.

[0121] Non-transitory computer-readable media may be used to store instructions for firmware of a memory subsystem (eg, 710). When the instructions are executed by the controller 715 and / or the processing device 717, the instructions cause the controller 715 and / or the processing device 717 to perform the methods discussed herein.

[0122] In one embodiment, a method (eg, implemented in memory subsystem 710) is used to encode a data structure that has previously been encoded using two layers (eg, using a method such as that for Figure 1 The method may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method is performed at least in part by Figure 6 The method may be performed by the two-layer encoder / decoder 714. For example, after storing the encoded data in the memory cells 103 using a multi-pass programming technique in one or more media units (e.g., an integrated circuit die) and then retrieving the encoded data from the memory cells 103 in the event that an error may have occurred when reading the memory cells 103, the method may be performed to recover the encoded data.

[0123] In one embodiment, the two-layer encoder / decoder 714 decodes data retrieved from the memory cell based on a first error correction code (e.g., a low-density parity-check code). The two-layer encoder / decoder 714 determines whether decoding according to the first error correction code (e.g., ECC 123) is successful. When all codewords generated using the first error correction code (e.g., ECC 123) can be successfully decoded and / or recovered via parity data (e.g., parity data 115), the original data based on which the encoded data was generated, stored in the memory cell, and then retrieved from the memory cell is successfully recovered.

[0124] If some of the codewords cannot be successfully decoded according to the first error correction code (e.g., ECC 123), the two-layer encoder / decoder 714 identifies the symbols that could not be successfully decoded via the first error correction code. In one example, unsatisfied parity checks in the LDPC code can be used to identify bits in the LDPC codeword that cannot be reliably decoded. The identified symbols can be considered lost / erased. A second error correction code (e.g., ECC 125) can then be used to decode those few ambiguous symbols (e.g., using parity data 119). Decoding according to the second error correction code can be performed to recover the lost / erased symbols.

[0125] The two-layer encoder / decoder 714 recovers the identified symbols based on the second error correction code. In one example, the recovered symbols can be used to replace the corresponding symbols retrieved from the memory cell and further decoded via the first error correction code (e.g., a low-density parity check code) for data recovery.

[0126] In one example, the two-layer encoder / decoder 714 determines whether to perform another iteration. For example, if fewer than a threshold number of iterations (e.g., 4) have been performed, the two-layer encoder / decoder 714 may repeat the above decoding operation for another iteration to recover the data. After the threshold number of iterations (e.g., 4) has been performed and decoding is still unsuccessful, the two-layer encoder / decoder 714 may report a data recovery / decoding failure.

[0127] Figure 7An example machine illustrating a computer system 600 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 6 720) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 6 memory subsystem 710) or can be used to perform the operation of the two-layer encoder / decoder 714 (e.g., execute instructions to perform operations corresponding to the reference Figure 6 In one example, computer system 600 corresponds to storage device 101 or 305, and / or host system 127 or 301.

[0128] In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud-based computing infrastructure or environment.

[0129] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0130] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630 (which may include multiple buses).

[0131] In various embodiments, processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communicating via a network 620.

[0132] The data storage system 618 may include a machine-readable storage medium 624 (also referred to herein as a computer-readable medium) on which is stored a set of one or more instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, with the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 6 In one embodiment, the instructions 626 include instructions for implementing a two-layer encoder / decoder (e.g., Figure 6 The functional instructions of the two levels of parity protection supported by the two-layer encoder / decoder 714) are described.

[0133] The present disclosure includes various apparatuses that perform the methods and implement the systems described above, including data processing systems that perform the methods, and computer-readable media containing instructions that, when executed on the data processing systems, cause the systems to perform the methods.

[0134] The description and drawings are illustrative and should not be construed as limiting. Numerous specific details are described to provide a thorough understanding. However, in some cases, well-known or conventional details are not described to avoid obscuring the description. References to one or more embodiments in this disclosure are not necessarily references to the same embodiment; such references mean at least one embodiment.

[0135] As used herein, “coupled to” or “coupled with…” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0136] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. The appearance of the phrase "in one embodiment" in various places in this specification does not necessarily refer to the same embodiment, nor does it necessarily refer to separate or alternative embodiments that are mutually exclusive of other embodiments. In addition, various features may be described that may be exhibited by some embodiments but not by others. Similarly, various requirements may be described that may be requirements for some embodiments but not for others.

[0137] In this specification, various functions and / or operations may be described as being performed by software code or caused by software code to simplify the description. However, those skilled in the art will recognize that this expression means that the functions and / or operations are caused by one or more processing devices executing the code, such as a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit, and / or a field programmable gate array (FPGA). Alternatively or in combination, dedicated circuits (e.g., logic circuits) may be used to implement functions and operations with or without software instructions. Embodiments may be implemented using hard-wired circuits or in combination with software instructions without software instructions. Therefore, the technology is neither limited to any particular combination of hardware circuits and software, nor to any particular source of instructions executed by a computing device.

[0138] While some embodiments may be implemented in fully functional computers and computer systems, various embodiments are capable of being distributed as computing products in various forms and are applicable regardless of the specific type of computer-readable media that actually implements the distribution.

[0139] At least some aspects of the disclosure may be embodied, at least in part, in software. That is, the techniques may be performed on a computing device or another system in response to a processing device (e.g., a microprocessor) thereof executing sequences of instructions contained in a memory (e.g., ROM, volatile RAM, non-volatile memory, cache, or remote storage device).

[0140] The routines executed to implement the embodiments may be implemented as part of an operating system, middleware, a service delivery platform, a software development kit (SDK) component, a network service, or other specific application, component, program, object, module, or sequence of instructions (sometimes referred to as a computer program). The calling interface for these routines may be exposed to the software development community as an application programming interface (API). A computer program typically includes one or more sets of instructions stored in various memories and storage devices in a computer at various times, and when the set of instructions is read and executed by one or more processors in the computer, causes the computer to perform the necessary operations to perform the elements involved in various aspects.

[0141] Computer-readable media can be used to store software and data that, when executed by a processing device or computing device, causes the device to perform various methods. Executable software and data can be stored in various locations, including, for example, ROM, volatile RAM, non-volatile memory, and / or cache. Portions of this software and / or data can be stored in any of these storage devices. In addition, data and instructions can be obtained from a centralized server or peer-to-peer network. Different portions of data and instructions can be obtained from different centralized servers and / or peer-to-peer networks at different times and in different communication sessions or within the same communication session. All data and instructions can be obtained before executing the application. Alternatively, portions of data and instructions can be obtained dynamically and in a timely manner as needed for execution. Therefore, it is not required that all data and instructions be on computer-readable media at a particular moment in time.

[0142] As used herein, the term "computer-readable medium" and the like includes a single medium or multiple media that store one or more sets of instructions. Examples of computer-readable media include, but are not limited to, recordable and non-recordable types of media, such as volatile and non-volatile memory devices, read-only memory (ROM), random access memory (RAM), flash memory devices, solid-state drive storage media, removable disks, magnetic disk storage media, optical storage media (e.g., compact disk read-only memory (CD ROM), digital versatile disks (DVD), etc.), and others. Computer-readable media can store instructions. Other examples of computer-readable media include, but are not limited to, non-volatile embedded devices using NOR flash or NAND flash architectures. Media used in these architectures can include unmanaged NAND devices and / or managed NAND devices, including, for example, eMMC, SD, CF, UFS, and SSD.

[0143] Generally speaking, non-transitory computer-readable media includes any mechanism that provides (e.g., stores) information in a form accessible by a computing device (e.g., a computer, a mobile device, a network device, a personal digital assistant, a manufacturing tool with a controller, any device with a set of one or more processors, etc.).

[0144] In various embodiments, hard-wired circuitry may be used in combination with software and firmware instructions to implement the technology. Thus, the technology is not limited to any specific combination of hardware circuitry and software, nor to any specific source for the instructions executed by the computing device.

[0145] The various embodiments described herein may be implemented using a wide variety of different types of computing devices. As used herein, examples of a "computing device" include, but are not limited to, a server, a centralized computing platform, a system of multiple computing processors and / or components, a mobile device, a user terminal, a vehicle, a personal communication device, a wearable digital device, an electronic self-service kiosk, a general-purpose computer, an electronic document reader, a tablet computer, a laptop computer, a smartphone, a digital camera, a residential home appliance, a television, or a digital music player.

[0146] Additional examples of computing devices include those that are part of what is known as the "Internet of Things" (IoT). Such "things" may occasionally interact with their owners or administrators, who may monitor them or modify settings related to them. In some cases, such owners or administrators act as users with respect to the "thing" devices. In some examples, a user's primary mobile device (e.g., an Apple iPhone) may be an administrator server with respect to a paired "thing" device (e.g., an Apple Watch) worn by the user.

[0147] In some embodiments, the computing device can be a computer or host system, which is implemented as, for example, a desktop computer, a laptop computer, a network server, a mobile device, or other computing device that includes a memory and a processing device. The host system can include or be coupled to a memory subsystem so that the host system can read data from the memory subsystem or write data to the memory subsystem. The host system can be coupled to the memory subsystem via a physical host interface. Generally speaking, the host system can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0148] In some embodiments, the computing device is a system including one or more processing devices. Examples of a processing device may include a microcontroller, a central processing unit (CPU), a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), a system on a chip (SoC), or another suitable processor.

[0149] In one example, the computing device is a controller of a memory system. The controller includes a processing device and a memory containing instructions that are executed by the processing device to control various operations of the memory system.

[0150] Although some of the figures illustrate multiple operations in a particular order, non-sequence dependent operations may be reordered and other operations may be combined or decomposed. While some reordering or other groupings are specifically mentioned, other reorderings or groupings will be apparent to those skilled in the art, and thus, no exhaustive list of alternatives is provided. Furthermore, it should be appreciated that the stages may be implemented in hardware, firmware, software, or any combination thereof.

[0151] In the foregoing description, the present disclosure has been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope as set forth in the appended claims. The description and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method for a memory device, comprising: Receive data from the host system; encoding the received data using a first error correction code to generate first parity data; determining a temperature at which a memory unit will store the received data; identifying at least a first portion of the received data based on the determined temperature; encoding the first portion of the received data using a second error correction code to generate second parity data, wherein the second error correction code has a higher error correction capability than the first error correction code; as well as The first portion, the first parity data, and the second parity data are stored in the memory unit.

2. The method of claim 1 , wherein encoding the received data using the first error correction code comprises: splitting the received data into data units according to a predetermined payload size; as well as Each corresponding data unit of the payload size is encoded using the first error correction code to generate the first parity data.

3. The method of claim 1, wherein the memory cells include first cells programmed in a single-level cell (SLC) mode, and second cells programmed in at least one of a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, and a quad-level cell (QLC) mode. The method of claim 3 , wherein the first portion of the received data is stored in the second unit.

5. The method of claim 1, wherein encoding the first portion of the received data using the second error correction code is performed by the host system. 6 . The method of claim 1 , wherein the host system is a control system of a vehicle, and the control system is configured to control at least one function of the vehicle based on the data stored in the memory unit.

7. The method of claim 1, further comprising selecting the error correction capability of the second error correction code based on the determined temperature.

8. The method of claim 1, wherein the determined temperature is a current temperature associated with a storage device, the method further comprising selecting a type of the second error correction code based on the current temperature.

9. The method of claim 1, wherein identifying the first portion of the received data is further based on a programming mode used by the memory cell.

10. A data processing system comprising: a storage device configured to store data from a host system; as well as at least one processing device configured to: receiving first data from the host system; encoding the first data using a first error correction code to generate first parity data; determining at least one of a temperature at which the storage device will store the first data and a storage time at which the storage device will store the first data; identifying at least a first portion of the first data based on the at least one of the temperature and the storage time; encoding the first portion of the first data using a second error correction code to generate second parity data, wherein the second error correction code has a higher error correction capability than the first error correction code; as well as The first portion, the first parity data, and the second parity data are stored in the storage device.

11. The data processing system according to claim 10, wherein the at least one processing device is further configured to: retrieving the first portion of the first data from the storage device; decoding the first portion using the first error correction code; Determine that decoding is unsuccessful; as well as In response to determining that the decoding was unsuccessful, the first portion is decoded using the second error correction code.

12. The data processing system according to claim 11, wherein the at least one processing device is further configured to: determining that the processing capability of the host system is above a predetermined threshold; and In response to determining that the processing capability is above the predetermined threshold, the first portion is sent to the host system, where the first portion is decoded by the host system using the second error correction code.

13. The data processing system of claim 10, wherein the storage device comprises a controller configured to encode the first data using the first error correction code.

14. The data processing system of claim 10, further comprising at least one sensor, wherein: determining the temperature based on an output from a machine learning model, wherein data collected by the sensor is an input to the machine learning model; The temperature determined is the predicted temperature; as well as The first portion of the first data is identified based on the determined temperature.

15. The data processing system of claim 14, wherein the at least one sensor determines at least one of an ambient temperature of the storage device and an internal temperature of the storage device.

16. The data processing system according to claim 10, wherein: The at least one processing device is further configured to send the second parity data to the host system for storage in a memory of the host system; as well as The first portion of the first data is decoded by the host system using the second error correction code and the second parity data.

17. A non-transitory computer-readable medium storing instructions that, when executed in a memory subsystem, cause the memory subsystem to perform a method comprising: receiving first data from a host system; encoding the first data using a first error correction code to generate first parity data; determining that a storage device configured to store data received from the host system is to cease receiving power from a power supply; in response to determining that the storage device will cease receiving power from the power supply, identifying at least a first portion of the first data; encoding the first portion using a second error correction code to generate second parity data, wherein the second error correction code has a higher error correction capability than the first error correction code; as well as The first portion, the first parity data, and the second parity data are stored in the storage device.

18. The non-transitory computer-readable medium of claim 17, wherein the method further comprises: determining that the power from the power supply is available to the storage device; responsive to determining that the power from the power supply is available, determining that data loss has occurred in the first portion; In response to determining that the data loss in the first portion has occurred, the first portion is sent to the host system, where the first portion is decoded by the host system using the second error correction code.

19. The non-transitory computer-readable medium of claim 18, wherein determining that the data loss in the first portion has occurred comprises: retrieving the first portion from the storage device; decoding the first portion using the first error correction code; as well as Determine if decoding was unsuccessful.

20. The non-transitory computer-readable medium of claim 17, wherein the method further comprises: encoding a second portion of the first data, wherein a data size of the second portion is larger than that of the first portion; storing the second portion in the storage device; determining a first result of decoding the first portion using the first error correction code; determining a second result of decoding the first portion using the second error correction code; comparing the first result and the second result; determining a failure to decode the first portion based on comparing the first result and the second result; as well as In response to determining that the decoding of the first portion has failed, the second portion is sent to the host system for decoding using the second error correction code.

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