Calculation Resource Utilization Efficiency Evaluation Method and Device

Abstract

An evaluation method for calculating resource utilization efficiency, which is applied to a convolutional neural network accelerator based on FPGA. The computing resources to be evaluated in the accelerator are DSP computing resources, including: calculating the throughput utilization rate of DSP computing resources based on the theoretical total throughput rate and the actual total throughput rate of performing multiplication operations on DSP computing resources; calculating the average resource utilization rate of DSP computing resources based on the theoretical average DSP throughput rate and the actual average DSP throughput rate of DSP computing resources; and evaluating the computing resource utilization efficiency of the accelerator according to the throughput utilization rate and the average resource utilization rate. The present disclosure also provides an evaluation device for calculating resource utilization efficiency. Compared with the traditional computing resource evaluation method, this method and device exclude the interference of factors such as data type, implementation frequency, and chip specifications on the evaluation of the computing resource utilization efficiency of the accelerator, enabling the evaluation to focus on the performance of the accelerator itself, and the evaluation results are more objective.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA hardware acceleration design, and particularly to a method and device for evaluating the utilization efficiency of computing resources. Background Art

[0002] Convolutional Neural Networks (CNNs) are one of the representative algorithms of deep learning. Due to their excellent performance in the field of artificial intelligence, they have been widely concerned and applied to high-tech applications such as image classification, speech recognition, face recognition, autonomous driving, and medical imaging.

[0003] With the continuous development of CNNs, the network structure has become increasingly complex and the number of parameters has exploded, which poses challenges to the design of CNN hardware accelerators. Field Programmable Gate Array (FPGA) has excellent flexible programmability and outstanding performance-power ratio. Most mainstream CNN forward inference accelerators adopt acceleration schemes based on FPGA. To fully utilize the computing power of FPGA, the core of the accelerator design is to efficiently utilize the on-chip computing resources. The most efficient computing resource for high-bit-width data multiplication operations on FPGA chips is the Digital Signal Processor (DSP). Therefore, it is very crucial to efficiently utilize DSP computing resources. Accurately evaluating the utilization efficiency of DSP computing resources can help designers distinguish the advantages and disadvantages of different designs and guide designers to adjust and improve their designs. Currently, various methods used in the academic community to evaluate the utilization efficiency of DSP computing resources have defects and cannot objectively and accurately evaluate the utilization efficiency of DSP computing resources. Summary of the Invention

[0004] The present disclosure provides a method and device for evaluating the utilization efficiency of computing resources to solve the defects existing in the traditional methods for evaluating the utilization efficiency of DSP computing resources.

[0005] On the one hand, the present disclosure provides a method for evaluating the utilization efficiency of computing resources, which is applied to a convolutional neural network accelerator based on FPGA. The computing resources to be evaluated of the accelerator are DSP computing resources, and the method includes: calculating the throughput utilization rate of the DSP computing resources based on the theoretical total throughput rate and the actual total throughput rate of the multiplication operation executed by the DSP computing resources; calculating the average resource utilization rate of the DSP computing resources based on the theoretical average DSP throughput rate and the actual average DSP throughput rate of the DSP computing resources; and evaluating the utilization efficiency of the computing resources of the accelerator according to the throughput utilization rate and the average resource utilization rate.

[0006] Optionally, the DSP computing resources consist of multiple DSPs. Calculating the throughput utilization rate of the DSP computing resources based on the theoretical total throughput rate and the actual total throughput rate of performing multiplication operations on the DSP computing resources includes: calculating the actual total throughput rate of the DSP computing resources for performing multiplication operations based on the amount of multiplication operations, addition operations, and the actual total throughput rate that the accelerator can perform; calculating the theoretical total throughput rate of the DSP computing resources for performing multiplication operations based on the number of multiplication operations that can be achieved by a single DSP, the total number of DSPs, and the clock frequency of the DSPs; calculating the ratio of the actual total throughput rate to the theoretical total throughput rate of the DSP computing resources for performing multiplication operations to obtain the throughput utilization rate.

[0007] Optionally, calculating the actual total throughput rate of the DSP computing resources for performing multiplication operations based on the amount of multiplication operations, addition operations, and the actual total throughput rate that the accelerator can perform includes: Let OPS mul represent the amount of multiplication operations that the accelerator can perform, OPS add represent the amount of addition operations that the accelerator can perform, GOP acc / s represent the actual total throughput rate of the accelerator, and GOP impl / s represent the actual total throughput rate of the DSP computing resources for performing multiplication operations. Then:

[0008] 。

[0009] Optionally, calculating the theoretical total throughput rate of the DSP computing resources for performing multiplication operations based on the number of multiplication operations that can be achieved by a single DSP, the total number of DSPs, and the clock frequency of the DSPs includes: Let #Mul DSP represent the number of multiplication operations that can be achieved by a single DSP, #DSP avl represent the total number of DSPs, Freq represent the clock frequency at which the DSPs operate, and GOP avl / s represent the theoretical total throughput rate of the DSP computing resources for performing multiplication operations. Then:

[0010] 。

[0011] Optionally, calculating the ratio of the actual total throughput rate to the theoretical total throughput rate of the DSP computing resources for performing multiplication operations to obtain the throughput utilization rate includes: Let R1_score represent the throughput utilization rate, GOP impl / s represent the actual total throughput rate, and GOP avl / s represent the theoretical total throughput rate. Then:

[0012] 。

[0013] Optionally, the DSP computing resources are composed of multiple DSPs. Calculating the average resource utilization rate of the DSP computing resources based on the theoretical average DSP throughput rate and the actual average DSP throughput rate of the DSP computing resources includes: calculating the ratio of the actual total throughput rate of the DSP computing resources for performing multiplication operations to the number of DSPs actually used to obtain the actual average DSP throughput rate of the DSP computing resources; calculating the ratio of the theoretical total throughput rate of the DSP computing resources for performing multiplication operations to the total number of DSPs to obtain the theoretical average DSP throughput rate of the DSP computing resources; calculating the ratio of the actual average DSP throughput rate to the theoretical average DSP throughput rate to obtain the average resource utilization rate.

[0014] Optionally, calculating the ratio of the actual average DSP throughput rate to the theoretical average DSP throughput rate to obtain the average resource utilization rate includes: Let R2_score represent the average resource utilization rate, represent the actual average DSP throughput rate, represent the theoretical average DSP throughput rate, then:

[0015] .

[0016] Optionally, evaluating the computing resource utilization efficiency of the accelerator based on the throughput utilization rate and the average resource utilization rate includes: obtaining the throughput utilization rate and the average resource utilization rate of multiple accelerators with different designs; comparing the magnitudes of the throughput utilization rate and the average resource utilization rate of each accelerator; evaluating the computing resource utilization efficiency of each accelerator according to the comparison results, where the higher the throughput utilization rate and the higher the average resource utilization rate, the higher the computing resource utilization efficiency of the corresponding accelerator.

[0017] Optionally, the priority of the throughput utilization rate is higher than that of the average resource utilization rate. Evaluating the computing resource utilization efficiency of each accelerator according to the comparison results includes: the higher the throughput utilization rate, the higher the computing resource utilization efficiency of the corresponding accelerator; when the throughput utilization rates of multiple accelerators are the same, the higher the average resource utilization rate, the higher the evaluation of the computing resource utilization efficiency of the corresponding accelerator.

[0018] On the other hand, the present disclosure provides an evaluation device for the utilization efficiency of computing resources, including: a throughput utilization rate calculation module, configured to calculate the throughput utilization rate of the DSP computing resources based on the theoretical total throughput rate and the actual total throughput rate of the multiplication operation performed by the DSP computing resources; an average resource utilization rate calculation module, configured to calculate the average resource utilization rate of the DSP computing resources based on the theoretical average DSP throughput rate and the actual average DSP throughput rate of the DSP computing resources; and a resource utilization efficiency evaluation module, configured to evaluate the utilization efficiency of the computing resources of the accelerator according to the throughput utilization rate and the average resource utilization rate.

[0019] A method and device for evaluating the utilization efficiency of computing resources provided by the present disclosure are applied to a convolutional neural network accelerator based on an FPGA. Among them, the computing resources to be evaluated of the accelerator are DSP computing resources, and the DSP computing resources are evaluated from two aspects: throughput utilization rate and average resource utilization rate. Among them, the throughput utilization rate reflects how much the computing power of the DSP computing resources is developed, and the average resource utilization rate reflects the level of resource utilization efficiency of a single DSP in the DSP computing resources. Compared with the traditional evaluation method, it excludes the interference of factors such as data type, implementation frequency, and chip specifications, making the evaluation of the DSP computing resources focus on the accelerator performance itself. Since this evaluation system can objectively and comprehensively evaluate the utilization effect of the DSP computing resources in the convolutional neural network accelerator structure based on an FPGA, it can objectively evaluate the implementation effect, advantages and disadvantages of this accelerator structure, and can be used to provide accurate guidance for the optimization of the structure, which has important significance for optimizing the implementation of CNN algorithms on different FPGA platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 It is a schematic flowchart of a method for evaluating the utilization efficiency of computing resources provided by an embodiment of the present disclosure;

[0022] Figure 2 It is a schematic structural diagram of an evaluation device for the utilization efficiency of computing resources provided by another embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0024] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The words "a", "an", and "the" used herein should also include the meanings of "multiple" and "multiple kinds" unless the context clearly indicates otherwise. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0026] Some block diagrams and / or flowcharts are shown in the accompanying drawings. It should be understood that some blocks or combinations of blocks in the block diagrams and / or flowcharts can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when executed by the processor, these instructions can create a device for implementing the functions / operations illustrated in these block diagrams and / or flowcharts.

[0027] Therefore, the technology of the present disclosure can be implemented in the form of hardware and / or software (including firmware, microcode, etc.). In addition, the technology of the present disclosure can take the form of a computer program product on a computer-readable medium storing instructions, and this computer program product can be used by an instruction execution system or in combination with an instruction execution system. In the context of the present disclosure, a computer-readable medium can be any medium that can contain, store, transmit, propagate, or transport instructions. For example, a computer-readable medium can include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, components, or propagation media. Specific examples of computer-readable media include: magnetic storage devices such as magnetic tapes or hard disk drives (HDDs); optical storage devices such as compact discs (CD-ROMs); memories such as random access memories (RAMs) or flash memories; and / or wired / wireless communication links.

[0028] There are many methods for evaluating the utilization efficiency of computing resources adopted in the academic and industrial fields. Currently, the most commonly used core evaluation formulas are the following three (Formulas (1)-(3)). Among them, DSP_Eff represents the computing resource utilization efficiency of the core computing resource DSP, #DSPimpl represents the number of DSPs actually participating in the operation when the accelerator implements a convolutional neural network, #DSPavl represents the total number of all available DSPs on the FPGA chip, GOPacc / s represents the actual total throughput rate of the accelerator, and #Logic represents the total on-chip logic resource number of the FPGA chip.

[0029] (1);

[0030] (2);

[0031] (3);

[0032] The above three evaluation mechanisms for computing resource utilization efficiency each have their own defects:

[0033] What Formula (1) calculates is the actual occupancy rate of DSP computing resources. Since a high resource occupancy rate does not necessarily mean a high resource utilization efficiency. For example, some occupied computing resources are idle in some clock cycles. These idle computing resources not only do not participate in the effective data calculation process, but instead cause resource redundancy. They bring additional power consumption and reduce the performance-power ratio of the accelerator. Therefore, the evaluation result of Formula (1) cannot scientifically measure the utilization efficiency of computing resources.

[0034] Formula (2) uses the throughput rate of the accelerator as a measure of the acceleration efficiency. However, the throughput rate of the accelerator is directly related to the implementation frequency of the FPGA (the clock frequency when the FPGA is running), and the implementation frequency is directly affected by factors such as the RTL code programming ability of the accelerator designers, the process of the FPGA chip, and the computing performance of the chip itself. Therefore, Formula (2) cannot exclude these factors and objectively measure the utilization efficiency of the computing resources of a structure alone.

[0035] Formula (3) measures the computing resource utilization efficiency by the ratio of the throughput rate to the chip logic specification. However, this formula is seriously affected by the implementation method of the multiplication operation. If the accelerator is designed to use DSP resources to implement the multiplication operation, Formula (3) cannot reflect the utilization efficiency of DSP resources; if the design uses logic resources to implement the multiplication operation, Formula (3) will be affected by the implementation frequency.

[0036] Since the convolutional neural network is a computationally intensive structure, its massive matrix convolution calculations pose challenges to the accelerator design. The core of the accelerator design is to efficiently utilize the on-chip computing resources, and many classic designs focus on optimizing the core of matrix operations - the multiply-accumulate operation. Since the most efficient computing resource for high-bitwidth data multiplication on the FPGA chip is the DSP, it is very crucial to efficiently utilize the DSP computing resources. The embodiments of the present disclosure provide a method for evaluating the utilization efficiency of computing resources, which is used to evaluate the utilization efficiency of DSP computing resources. This method can be applied to electronic devices, including mobile phones, portable Android devices (PADs), laptops, and personal digital assistants (PDAs), etc.

[0037] Figure 1 FIG. schematically shows a flowchart of a method for evaluating the utilization efficiency of computing resources according to an embodiment of the present disclosure.

[0038] Specifically, as Figure 1 shown, a method for evaluating the utilization efficiency of computing resources provided by an embodiment of the present disclosure is applied to a convolutional neural network accelerator based on an FPGA. The computing resources to be evaluated in the accelerator are DSP computing resources, and the method includes steps S110 - S130.

[0039] S110, calculate the throughput utilization rate of the DSP computing resources based on the theoretical total throughput rate and the actual total throughput rate of performing multiplication operations by the DSP computing resources.

[0040] The DSP computing resources refer to multiple DSPs on the accelerator of a convolutional neural network accelerator based on an FPGA, which are used to perform multiplication operations and addition operations. Since the addition operation can be implemented by the DSP or by logical resources, it is difficult to count the throughput rate of the addition operation. However, the multiplication operation in the accelerator is only performed by the DSP. Therefore, the throughput rate of the DSP computing resources performing multiplication operations can be selected to represent its operation efficiency. According to the actual total throughput rate and the theoretical total throughput rate of the DSP computing resources performing multiplication operations, the utilization rate of its throughput rate can be calculated, that is, the percentage of the multiplication operation throughput rate provided by the DSP computing resources that is designed and developed. The utilization rate of the throughput rate can be used to evaluate the quality of the accelerator design to which the DSP computing resources belong from the aspect of operation efficiency.

[0041] S120, calculate the average resource utilization rate of the DSP computing resources based on the theoretical average DSP throughput rate and the actual average DSP throughput rate of the DSP computing resources.

[0042] Affected by the design, different accelerators have different redundant occupancies of DSP computing resources when performing operations. The less DSP redundancy indicates the higher utilization rate of DSP computing resources and the better design of the accelerator. The closer the actual average DSP throughput rate of the DSP computing resources is to the theoretical average DSP throughput rate, the higher the average resource utilization rate, indicating less redundancy of the DSP computing resources.

[0043] S130. Evaluate the computing resource utilization efficiency of the accelerator according to the throughput rate utilization and the average resource utilization.

[0044] In the embodiments of the present disclosure, starting from the DSP computing resources themselves, using the throughput rate utilization of the DSP computing resources and the average resource utilization, a comprehensive evaluation is carried out on both the computing power and the resource utilization efficiency of the DSP computing resources, and an evaluation of the computing resource utilization efficiency of the accelerator can be obtained. Among them, the higher the throughput rate utilization and the average resource utilization, the higher the corresponding computing resource utilization efficiency of the accelerator.

[0045] The following details the specific calculations of steps S110 - S130.

[0046] S110. The DSP computing resources are composed of multiple DSPs. Calculating the throughput rate utilization of the DSP computing resources based on the theoretical total throughput rate and the actual total throughput rate of performing multiplication operations on the DSP computing resources includes steps S111 - S113.

[0047] S111. Based on the amount of multiplication operations, the amount of addition operations, and the actual total throughput rate that the accelerator can perform, calculate the actual total throughput rate of the DSP computing resources for performing multiplication operations.

[0048] Let OPS mul represent the amount of multiplication operations that the accelerator can perform, OPS add represent the amount of addition operations that the accelerator can perform, GOP acc / s represent the actual total throughput rate of the accelerator, and GOP impl / s represent the actual total throughput rate of the DSP computing resources for performing multiplication operations. Then:

[0049] .

[0050] S112. Based on the number of multiplication operations that a single DSP can achieve, the total number of DSPs, and the clock frequency of the DSPs, calculate the theoretical total throughput rate of the DSP computing resources for performing multiplication operations.

[0051] Let #Mul DSP represent the number of multiplication operations that a single DSP can achieve, #DSPavl denotes the total number of the DSPs, Freq denotes the clock frequency at which the DSPs operate, and GOP avl / s denotes the theoretical total throughput rate of the DSP computing resources for performing multiplication operations, then:

[0052] .

[0053] Among them, #Mul DSP is determined by the accelerator chip model, the multiplier type, and the convolutional operation data bit width.

[0054] S113. Calculate the ratio of the actual total throughput rate of the DSP computing resources for performing multiplication operations to the theoretical total throughput rate to obtain the throughput rate utilization rate.

[0055] Let R1_score denote the throughput rate utilization rate, and GOP impl / s denote the actual total throughput rate, and GOP avl / s denote the theoretical total throughput rate, then:

[0056] ,

[0057] Among them, the closer the throughput rate utilization rate is to 1, the more efficiently the on-chip total DSP computing resources can be fully exploited by the accelerator design.

[0058] S120. The DSP computing resources are composed of multiple DSPs. Based on the theoretical average DSP throughput rate and the actual average DSP throughput rate of the DSP computing resources, calculate the average resource utilization rate of the DSP computing resources, including steps S121 to S123.

[0059] S121. Calculate the ratio of the actual total throughput rate of the DSP computing resources for performing multiplication operations to the number of the actually used DSPs to obtain the actual average DSP throughput rate of the DSP computing resources.

[0060] When performing the same amount of computation, for accelerators with different designs, if the throughput rate utilization rates of the DSP computing resources are the same but the number of used DSPs is different, the larger the number of used DSPs, the greater the redundancy and the lower the actual average DSP throughput rate. Therefore, the actual average DSP throughput rate reflects the actual utilization efficiency of the DSP computing resources during the actual operation process.

[0061] S122. Calculate the ratio of the theoretical total throughput rate of the DSP computing resources for performing multiplication operations to the total number of the DSPs to obtain the theoretical average DSP throughput rate of the DSP computing resources.

[0062] S123. Calculate the ratio of the actual average DSP throughput rate to the theoretical average DSP throughput rate to obtain the average resource utilization rate.

[0063] Let R2_score represent the average resource utilization rate, GOP impl / s represent the actual total throughput rate, GOP avl / s represent the theoretical total throughput rate, #DSP impl represent the number of actually participating DSPs, #DSP avl represent the total number of the DSPs, represent the actual average DSP throughput rate, represent the theoretical average DSP throughput rate, then:

[0064] .

[0065] Among them, the closer R2_score is to 1, the higher the usage efficiency of the DSP computing resources in actual operations, and the fewer the redundant occupied DSP resources.

[0066] S130. Evaluate the computing resource utilization efficiency of the accelerator according to the throughput rate utilization rate and the average resource utilization rate, including steps S131 to S133.

[0067] S131. Obtain the throughput rate utilization rate and the average resource utilization rate of multiple accelerators with different designs.

[0068] S132. Compare the magnitudes of the throughput rate utilization rate and the average resource utilization rate of each accelerator.

[0069] S133. Evaluate the computing resource utilization efficiency of each accelerator according to the comparison result. Among them, the higher the throughput rate utilization rate and the average resource utilization rate, the higher the computing resource utilization efficiency of the corresponding accelerator.

[0070] In the embodiments of the present disclosure, when evaluating the quality of an accelerator, the throughput rate utilization rate and the average resource utilization rate of multiple accelerators with different designs are compared. Generally, the higher the throughput rate utilization rate and the average resource utilization rate, the higher the evaluation of the corresponding accelerator.

[0071] Specifically, the higher the throughput rate utilization rate, the higher the computing resource utilization efficiency of the corresponding accelerator; when the throughput rate utilization rates of multiple accelerators are the same, the higher the average resource utilization rate, the higher the evaluation of the computing resource utilization efficiency of the corresponding accelerator.

[0072] A method and device for evaluating the utilization efficiency of computing resources provided by the present disclosure are applied to a convolutional neural network accelerator based on FPGA. Among them, the computing resources to be evaluated by the accelerator are DSP computing resources. The DSP computing resources are evaluated from two aspects: throughput utilization rate and average resource utilization rate. Among them, the throughput utilization rate reflects how much the computing power of the DSP computing resources is developed, and the average resource utilization rate reflects the level of resource utilization efficiency of a single DSP in the DSP computing resources. Compared with the traditional evaluation method, it excludes the interference of factors such as data type, implementation frequency, and chip specifications, making the evaluation of DSP computing resources focus on the accelerator performance itself. Since this evaluation system can objectively and comprehensively evaluate the utilization effect of DSP computing resources in the structure of a convolutional neural network accelerator based on FPGA, it can objectively evaluate the implementation effect, advantages and disadvantages of this accelerator structure, and can be used to provide accurate guidance for the optimization of the structure, which has important significance for optimizing the implementation of CNN algorithms on different FPGA platforms.

[0073] Figure 2 It is a schematic structural diagram of an evaluation device for the utilization efficiency of computing resources provided by another embodiment of the present disclosure.

[0074] As Figure 2 shown, on the other hand, the present disclosure provides an evaluation device 200 for the utilization efficiency of computing resources, which is applied to a convolutional neural network accelerator based on FPGA. The computing resources to be evaluated by the accelerator are DSP computing resources, including: a throughput utilization rate calculation module 210, an average resource utilization rate calculation module 220, and a resource utilization efficiency evaluation module 230.

[0075] The throughput utilization rate calculation module 210 is configured to calculate the throughput utilization rate of the DSP computing resources based on the theoretical total throughput rate and the actual total throughput rate of performing multiplication operations by the DSP computing resources.

[0076] The average resource utilization rate calculation module 220 is configured to calculate the average resource utilization rate of the DSP computing resources based on the theoretical average DSP throughput rate and the actual average DSP throughput rate of the DSP computing resources.

[0077] The resource utilization efficiency evaluation module 230 is configured to evaluate the utilization efficiency of the computing resources of the accelerator according to the throughput utilization rate and the average resource utilization rate.

[0078] In the embodiments of the present disclosure, the throughput utilization rate calculation module 210 calculates the utilization rate of the throughput based on the actual total throughput and the theoretical total throughput of the DSP computing resource for performing multiplication operations, that is, the percentage of the multiplication operation throughput provided by the DSP computing resource that is designed and developed, which can be used to evaluate the quality of the accelerator design to which the DSP computing resource belongs from the aspect of operation efficiency; the average resource utilization rate calculation module 220 calculates the average resource utilization rate of the DSP computing resource based on the theoretical average DSP throughput and the actual average DSP throughput of the DSP computing resource, which can be used to represent the level of the usage efficiency of a single DSP computing resource; the resource utilization efficiency evaluation module 230 comprehensively uses the results output by the throughput utilization rate calculation module 210 and the average resource utilization rate calculation module 220, and uses the throughput utilization rate and the average resource utilization rate of the DSP computing resource to comprehensively evaluate the computing power and resource utilization efficiency of the DSP computing resource in two aspects, and an evaluation of the resource utilization efficiency of the accelerator can be obtained. Among them, the higher the throughput utilization rate and the higher the average resource utilization rate, the higher the resource utilization efficiency of the corresponding accelerator.

[0079] The evaluation device 200 for the computing resource utilization efficiency includes the evaluation method for the computing resource utilization efficiency as shown in Figure 1 The specific steps and beneficial effects of each module executing the method are the same as those of this evaluation method.

[0080] It can be understood that the throughput utilization rate calculation module 210, the average resource utilization rate calculation module 220, and the resource utilization efficiency evaluation module 230 can be implemented in one module, or any one of them can be split into multiple modules. Or, at least part of the functions of one or more of these modules can be combined with at least part of the functions of other modules and implemented in one module. According to the embodiments of the present invention, at least one of the throughput utilization rate calculation module 210, the average resource utilization rate calculation module 220, and the resource utilization efficiency evaluation module 230 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on substrate, a system on package, an application specific integrated circuit (ASIC), or can be implemented in any other reasonable way of integrating or packaging the circuit, etc., in hardware or firmware, or implemented in an appropriate combination of software, hardware, and firmware. Or, at least one of the throughput utilization rate calculation module 210, the average resource utilization rate calculation module 220, and the resource utilization efficiency evaluation module 230 can be at least partially implemented as a computer program module, and when the program is run by a computer, it can execute the functions of the corresponding module.

[0081] It should be noted that, for the foregoing method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0082] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0083] The above is the description of the method, device, electronic device and storage medium for constructing the user mental model provided by the present invention. For those of ordinary skill in the art, according to the idea of the embodiments of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. An evaluation method for computing resource utilization efficiency, which is applied to a convolutional neural network accelerator based on FPGA. The computing resource to be evaluated in the accelerator is the DSP computing resource, and the DSP computing resource is composed of multiple DSPs. It is characterized in that, Including: Calculating the throughput utilization rate of the DSP computing resource based on the theoretical total throughput rate of the DSP computing resource for performing multiplication operations and the actual total throughput rate of the DSP computing resource for performing multiplication operations; Calculating the average resource utilization rate of the DSP computing resource based on the theoretical average DSP throughput rate and the actual average DSP throughput rate of the DSP computing resource, including: Calculating the ratio of the actual total throughput rate of the DSP computing resource for performing multiplication operations to the number of the DSPs actually used to obtain the actual average DSP throughput rate of the DSP computing resource; Calculating the ratio of the theoretical total throughput rate of the DSP computing resource for performing multiplication operations to the total number of the DSPs to obtain the theoretical average DSP throughput rate of the DSP computing resource; Calculating the ratio of the actual average DSP throughput rate to the theoretical average DSP throughput rate to obtain the average resource utilization rate, where the average resource utilization rate R2_score is: Among them, GOP impl / s represents the actual total throughput rate of the DSP computing resources for performing multiplication operations, and GOP avl / s represents the theoretical total throughput rate of the DSP computing resources for performing multiplication operations, #DSP impl represents the number of DSPs actually participating in the operations, #DSP avl represents the total number of the DSPs, represents the actual average DSP throughput rate, represents the theoretical average DSP throughput rate; Evaluating the computing resource utilization efficiency of the accelerator based on the throughput utilization rate and the average resource utilization rate.

2. The evaluation method according to claim 1, wherein The calculating the throughput utilization rate of the DSP computing resource based on the theoretical total throughput rate of the DSP computing resource for performing multiplication operations and the actual total throughput rate of the DSP computing resource for performing multiplication operations includes: Calculating the actual total throughput rate of the DSP computing resource for performing multiplication operations based on the amount of multiplication operations, the amount of addition operations, and the actual total throughput rate that the accelerator can execute; Calculating the theoretical total throughput rate of the DSP computing resource for performing multiplication operations based on the number of multiplication operations that a single DSP can achieve, the total number of the DSPs, and the clock frequency of the DSP; Calculating the ratio of the actual total throughput rate of the DSP computing resource for performing multiplication operations to the theoretical total throughput rate to obtain the throughput utilization rate, where the throughput utilization rate R1_score is; Among them, GOP impl / s represents the actual total throughput rate of the DSP computing resources for performing multiplication operations, and GOP avl / s represents the theoretical total throughput rate of the DSP computing resources for performing multiplication operations.

3. The evaluation method according to claim 2, characterized in that, The calculating the actual total throughput rate of the DSP computing resource for performing multiplication operations based on the amount of multiplication operations, the amount of addition operations, and the actual total throughput rate that the accelerator can execute includes: Let OPS mul represent the amount of multiplication operations that the accelerator can perform, and OPS add represent the amount of addition operations that the accelerator can perform. GOP acc / s represents the actual total throughput rate of the accelerator, and GOP impl / s represents the actual total throughput rate of the DSP computing resources for performing multiplication operations. Then: 。 4. The evaluation method according to claim 2, characterized in that The calculating the theoretical total throughput rate of the DSP computing resource for performing multiplication operations based on the number of multiplication operations that a single DSP can achieve, the total number of the DSPs, and the clock frequency of the DSP includes: Let #Mul DSP represent the number of multiplication operations that can be achieved by a single said DSP, #DSP avl represent the total number of said DSPs, Freq represent the clock frequency at which the DSP operates, GOP avl / s represents the theoretical total throughput rate of the multiplication operations executed by the DSP computing resources, then: 。 5. The evaluation method according to claim 1, characterized in that The evaluating the computing resource utilization efficiency of the accelerator based on the throughput utilization rate and the average resource utilization rate includes: Obtaining the throughput utilization rate and the average resource utilization rate of multiple accelerators with different designs; Comparing the magnitudes of the throughput utilization rate and the average resource utilization rate of each accelerator; Evaluating the computing resource utilization efficiency of each accelerator according to the comparison result, where the higher the throughput utilization rate and the higher the average resource utilization rate, the higher the computing resource utilization efficiency of the corresponding accelerator.

6. The evaluation method according to claim 5, wherein The priority of the throughput utilization rate is higher than that of the average resource utilization rate. The evaluating the computing resource utilization efficiency of each accelerator according to the comparison result includes: The higher the throughput utilization rate, the higher the computing resource utilization efficiency of the corresponding accelerator; When the throughput utilization rates of multiple accelerators are the same, the higher the average resource utilization rate, the higher the evaluation of the computing resource utilization efficiency of the corresponding accelerator.

7. An evaluation device for calculating resource utilization efficiency, which is applied to a convolutional neural network accelerator based on FPGA. The computing resources to be evaluated of the accelerator are DSP computing resources, and the DSP computing resources are composed of multiple DSPs. It is characterized in that, It includes: A throughput utilization rate calculation module, configured to calculate the throughput utilization rate of the DSP computing resource based on the theoretical total throughput of the DSP computing resource for performing multiplication operations and the actual total throughput of the DSP computing resource for performing multiplication operations; An average resource utilization rate calculation module, configured to calculate the average resource utilization rate of the DSP computing resource based on the theoretical average DSP throughput and the actual average DSP throughput of the DSP computing resource, including: Calculating the ratio of the actual total throughput of the DSP computing resource for performing multiplication operations to the number of actually used DSPs to obtain the actual average DSP throughput of the DSP computing resource; Calculating the ratio of the theoretical total throughput of the DSP computing resource for performing multiplication operations to the total number of DSPs to obtain the theoretical average DSP throughput of the DSP computing resource; Calculating the ratio of the actual average DSP throughput to the theoretical average DSP throughput to obtain the average resource utilization rate, where the average resource utilization rate R2_score is: Among them, GOP impl / s represents the actual total throughput rate of the DSP computing resources for performing multiplication operations, and GOP avl / s represents the theoretical total throughput rate of the DSP computing resources for performing multiplication operations, #DSP impl represents the number of DSPs actually participating in the operations, #DSP avl represents the total number of the DSPs, represents the actual average DSP throughput rate, represents the theoretical average DSP throughput rate; A resource utilization efficiency evaluation module, configured to evaluate the computing resource utilization efficiency of the accelerator according to the throughput utilization rate and the average resource utilization rate.

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