Simulation Method of Integrated Circuit

Abstract

A simulation method for an integrated circuit, comprising: providing an initial unit circuit layout, the initial unit circuit layout including a plurality of initial interconnect patterns; obtaining interconnect cut layer information; performing simulation processing on the initial unit circuit layout according to the interconnect cut layer information to obtain a preset unit circuit layout; establishing a post-layout simulation netlist according to the preset unit circuit layout. Through the simulation method of the integrated circuit, the accuracy and reliability of the simulation result of the integrated circuit can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to a simulation method for integrated circuits. Background Art

[0002] With the rapid development of very large scale integrated circuit processes, the number of components in integrated circuits has been continuously increasing, while the size of integrated circuits has been getting smaller and smaller. Therefore, it is necessary to connect each component through an increasing number of metal interconnect layers to improve the speed and integration of the chip.

[0003] In advanced processes, after the layout design of an integrated circuit (IC) is completed, the layout of the integrated circuit is simulated to determine whether the design scheme of the integrated circuit meets the requirements.

[0004] Determining whether the design scheme of an integrated circuit meets the requirements mainly includes two aspects: on the one hand, it is to determine whether the circuit functions of each unit circuit in each integrated circuit meet the design standards; on the other hand, during the chip design process, there are many timing violations. Therefore, during the design, it is necessary to verify the correctness of the timing through timing analysis (Time Analysis).

[0005] Timing analysis usually includes dynamic timing simulation and static timing analysis (STA). Dynamic timing analysis mainly uses input vectors as stimuli to verify the timing function of the entire design. The accuracy of dynamic timing analysis depends on the coverage rate of the input stimuli. Its biggest drawback is that it is very slow. For example, when performing a full coverage test on a design with millions of gates, the time spent needs to be calculated in months. Static timing analysis, on the other hand, applies a specific timing model to analyze whether a specific circuit violates the timing constraints given by the designer. Compared with dynamic timing analysis, static timing analysis is very fast because it does not require input stimuli. At the same time, since static timing analysis is based on path analysis (PathBased) and uses an exhaustive logic, in theory, it can analyze whether all synchronous logics violate the constraints.

[0006] Generally speaking, when determining whether the circuit functions of each unit circuit in an integrated circuit meet the design standards, it is necessary to obtain the post-layout simulation netlist of each unit circuit based on the design scheme of the integrated circuit and verify it according to the data in the post-layout simulation netlist. When performing timing analysis, it is necessary to perform timing analysis on the integrated circuit according to the data in the post-layout simulation netlist and the corresponding fabrication process parameters. Therefore, during the process of simulating the layout of an integrated circuit, the accuracy of the data in the post-layout simulation netlist is particularly important.

[0007] However, the existing post-layout netlist data is still not accurate enough, resulting in inaccurate and unreliable simulation results for the layout of integrated circuits. Summary of the Invention

[0008] The technical problem solved by the present invention is to provide a simulation method for integrated circuits to increase the accuracy and reliability of the simulation results for the layout of integrated circuits.

[0009] To solve the above technical problem, the technical solution of the present invention provides a simulation method for integrated circuits, including: providing an initial unit circuit layout, where the initial unit circuit layout includes a plurality of initial interconnect patterns; obtaining interconnect cut layer information; performing simulation processing on the initial unit circuit layout according to the interconnect cut layer information to obtain a preset unit circuit layout; and establishing a post-layout netlist according to the preset unit circuit layout.

[0010] Optionally, the method for obtaining the interconnect cut layer information includes: providing an interconnect cut layer layout; and obtaining the interconnect cut layer information according to the interconnect cut layer layout.

[0011] Optionally, the interconnect cut layer layout includes a plurality of interconnect cut patterns; the interconnect cut layer information includes: the shapes and positions of a plurality of the interconnect cut patterns.

[0012] Optionally, the interconnect cut layer layout includes a plurality of interconnect cut patterns; the interconnect cut layer information includes: information reflecting the shapes and positions of a plurality of the interconnect cut patterns.

[0013] Optionally, the method for the simulation processing includes: obtaining a plurality of to-be-processed patterns according to the interconnect cut layer information and the initial unit circuit layout, where the to-be-processed patterns are initial interconnect patterns adjacent to the interconnect cut patterns and having different extension directions; and extending all the to-be-processed patterns along the extension directions of the to-be-processed patterns to corresponding associated boundaries to form first interconnect patterns, where the corresponding associated boundaries are the boundaries where the interconnect cut patterns are adjacent to the corresponding to-be-processed patterns.

[0014] Optionally, the post-layout netlist includes a first post-layout netlist, and the first post-layout netlist includes first RC information.

[0015] Optionally, the method for establishing the first post-layout netlist according to the preset unit circuit layout includes: obtaining the first RC information according to the initial interconnect patterns and the first interconnect patterns of the preset unit circuit layout.

[0016] Optionally, the first post-layout netlist further includes first MOS transistor information.

[0017] Optionally, the initial unit circuit layout further includes a plurality of MOS device patterns, and the MOS device patterns of the preset unit circuit layout are the same as those of the initial unit circuit layout; the method for establishing the first post-layout simulation netlist according to the preset unit circuit layout further includes: obtaining the first MOS transistor information according to the MOS device patterns of the preset unit circuit layout.

[0018] Optionally, the first MOS transistor information includes ss process corner information.

[0019] Optionally, it further includes: establishing a first timing model according to the first post-layout simulation netlist.

[0020] Optionally, it further includes: establishing a second post-layout simulation netlist according to the initial unit circuit layout.

[0021] Optionally, the method for establishing the second post-layout simulation netlist according to the initial unit circuit layout includes: obtaining the second RC information according to the initial interconnect pattern of the initial unit circuit layout.

[0022] Optionally, the method for establishing the second post-layout simulation netlist according to the initial unit circuit layout further includes: obtaining the second MOS transistor information according to the MOS device patterns of the initial unit circuit layout, and the second MOS transistor information includes ff process corner information.

[0023] Optionally, it further includes: establishing a second timing model according to the second post-layout simulation netlist.

[0024] Optionally, it further includes: performing a first unit circuit function test according to the first post-layout simulation netlist to obtain a first circuit function test result; performing a second unit circuit function test according to the second post-layout simulation netlist to obtain a second circuit function test result; obtaining a circuit function judgment result according to the first circuit function test result and the second circuit function test result, and the circuit function judgment result includes that the circuit function is qualified or unqualified.

[0025] Optionally, the method for obtaining the circuit function judgment result includes: providing a design specification standard; when the first circuit function test result is within the design specification standard range, and when the second circuit function test result is within the design specification standard range, the circuit function judgment result is that the circuit function is qualified; when the first circuit function test result or the second circuit function test result is outside the design specification standard range, the circuit function judgment result is that the circuit function is unqualified.

[0026] Optionally, it further includes: when the circuit function judgment result is that the circuit function is qualified, performing simulation on the integrated circuit according to the first timing model and the second timing model to obtain a simulation result of the integrated circuit.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] In the simulation method of the integrated circuit provided by the technical solution of the present invention, since the initial unit circuit layout is simulated according to the interconnect cut layer information to obtain a preset unit circuit layout, the preset unit circuit layout can preset the modification (extension) situation of several initial interconnect patterns in the subsequent design of the top-level circuit layout. Since the post-layout simulation netlist is established according to the preset unit circuit layout, the post-layout simulation netlist can reflect the information data after several initial interconnect patterns are modified (extended). Therefore, the accuracy of the post-layout simulation netlist for the initial unit circuit layout is improved. Since the accuracy of the post-layout simulation netlist for the initial unit circuit layout is improved, on the one hand, the accuracy of the timing model established by the subsequent post-layout simulation netlist can be improved, and in the subsequent process of simulating the integrated circuit according to the timing model, it is beneficial to improve the accuracy and reliability of the simulation results. On the other hand, it can more accurately judge whether the circuit function of the initial unit circuit layout is qualified in the subsequent process, so that the initial unit circuit layout that can be used for simulating the integrated circuit can be more accurately screened. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic flowchart of a simulation method for an integrated circuit;

[0030] Figure 2 is a schematic layout diagram of a unit circuit of an integrated circuit;

[0031] Figure 3 is a schematic flowchart of a simulation method for an integrated circuit according to an embodiment of the present invention;

[0032] Figure 4 is a schematic diagram of an initial unit circuit layout according to an embodiment of the present invention;

[0033] Figure 5 is a schematic structural diagram of an interconnect cut layer layout according to an embodiment of the present invention;

[0034] Figure 6 is a schematic diagram of a preset unit circuit layout according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] As described in the background art, the existing post-layout simulation netlist data is still not accurate enough, resulting in inaccurate simulation results for the layout of the integrated circuit. The following is an analysis and description in combination with specific embodiments.

[0036] Figure 1 is a schematic flowchart of a simulation method for an integrated circuit.

[0037] Figure 2It is a layout schematic diagram of a cell circuit of an integrated circuit.

[0038] Please refer to Figure 1 , and the simulation method of the integrated circuit includes:

[0039] Step S100, providing the layout of the cell circuit;

[0040] Step S110, establishing a post-layout simulation netlist of the layout of the cell circuit according to the layout of the cell circuit;

[0041] Step S120, establishing a cell circuit timing model according to the post-layout simulation netlist;

[0042] Step S130, performing a functional test on the cell circuit according to the post-layout simulation netlist, and obtaining a cell circuit functional test result;

[0043] Step S140, providing a design specification standard, and comparing the cell circuit functional test result with the design specification standard;

[0044] When the result of the cell circuit functional test is outside the range of the design specification standard, execute Step S150, and will; when the result of the cell circuit functional test is within the range of the design specification standard, continue to execute Step S160.

[0045] Step S150, determining that the layout design of the cell circuit is unqualified, and modifying the layout of the cell circuit.

[0046] Step S160, performing integrated circuit simulation according to the cell circuit timing model.

[0047] The layout 10 of the cell circuit (as Figure 2 shown) includes: a plurality of first interconnect patterns 11, and the first interconnect patterns 11 are used to form the first interconnect structure.

[0048] The layout 10 of the cell circuit is used to form an integrated circuit subsequently.

[0049] The post-layout simulation netlist includes RC information and MOS transistor information. When the MOS transistor information includes ss process corner information, a first timing model is established through the post-layout simulation netlist; when the MOS transistor information includes ff process corner information, a second timing model is established through the post-layout simulation netlist.

[0050] Thus, the integrated circuit can be simulated according to the first timing model and the second timing model to obtain the timing delay situation of the integrated circuit.

[0051] It should be noted that for the sake of easy understanding, Figure 2 only some of the first interconnect patterns 11 in the layout 10 of the cell circuit are schematically shown in

[0052] However, in order to improve the integration density of the integrated circuit, during the subsequent top-level circuit design process, it is necessary to splice the layout diagrams 10 of multiple unit circuits. After splicing the layout diagrams 10 of multiple unit circuits, on the one hand, in the layout diagrams 10 of each unit circuit, the end-to-end spacing S2 (not shown) between some adjacent first interconnect patterns 11 is relatively small. On the other hand, the end-to-end spacing S1 (as shown in Figure 2 shown) between some first interconnect patterns 11 and the integrated interconnect pattern 21 of the top-level circuit layout (as shown in Figure 2 shown) is relatively small. Since the end-to-end spacing S2 and the end-to-end spacing S1 are relatively small, therefore, it is necessary to use an interconnect cutting pattern 20 (as shown in Figure 2 shown) to disconnect the connected first interconnect pattern 11 and the integrated interconnect pattern 21, so as to form a first interconnect structure and an integrated interconnect structure corresponding to this part of the first interconnect pattern 11 and the integrated interconnect pattern 21.

[0053] On the one hand, in order to reduce the area occupied by the interconnect cutting structure formed by the interconnect cutting pattern 20 and reduce the influence of the interconnect cutting structure on the formation positions of other semiconductor structures, therefore, the critical dimension of the interconnect cutting pattern 20 is relatively small. On the other hand, an interconnect cutting pattern 20 may need to cope with different end-to-end spacings S1 and S2. In order to correspond to the smallest end-to-end spacings S1 and S2 among the end-to-end spacings S1 and S2, therefore, it will also cause the critical dimension of the interconnect cutting pattern 20 to be relatively small. As a result, after the layout design of some first interconnect patterns 11 in the unit circuit is completed, in order to cooperate with the interconnect cutting pattern 20, modification is required. That is: after the layout design of the unit circuit layout 10 is completed, during the subsequent top-level circuit design, some first interconnect patterns 11 are extended to the interconnect cutting pattern 20 to form an augmented first interconnect pattern 13 (as shown in Figure 2 shown).

[0054] Since the augmented first interconnect pattern 13 is formed, therefore, the parasitic resistance and parasitic capacitance corresponding to the unit circuit layout 10 are increased, resulting in poor accuracy of the RC information of the unit circuit layout 10 in the post-layout simulation netlist established by the above integrated circuit simulation method, that is, the data accuracy of the post-layout simulation netlist is poor. As a result, not only the result of the unit circuit function test performed through the post-layout simulation netlist is unreliable. At the same time, since the accuracy of the RC information mainly reflects the resistance-capacitance delay situation, the increase in parasitic resistance and parasitic capacitance leads to poor accuracy of the RC information, making the accuracy of the first timing model established based on the post-layout simulation netlist poor, that is: the timing model established according to the post-layout simulation netlist is difficult to reflect the extreme (worst) timing delay situation of the unit circuit. Due to the poor accuracy of the first timing model, therefore, the result of the integrated circuit simulation is inaccurate, and it is impossible to accurately estimate the extreme situation of the timing delay of the integrated circuit.

[0055] To solve the above technical problem, an embodiment of the present invention provides a simulation method for an integrated circuit. By obtaining a preset unit circuit layout for each unit circuit according to the interconnect cut pattern layer information and each initial unit circuit layout, and establishing a post-layout simulation netlist based on each preset unit circuit layout, the data accuracy of the post-layout simulation netlist is improved, which is beneficial to improving the accuracy and reliability of the simulation results.

[0056] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of specific embodiments of the present invention will be provided in conjunction with the accompanying drawings.

[0057] Figure 3 is a schematic flowchart of a simulation method for an integrated circuit according to an embodiment of the present invention.

[0058] Please refer to Figure 3 , the simulation method for the integrated circuit includes:

[0059] Step S200: Provide an initial unit circuit layout, where the initial unit circuit layout includes a plurality of initial interconnect patterns.

[0060] After performing step S200, step S210 and step S220 are respectively executed.

[0061] Step S210: Obtain the interconnect cut layer information.

[0062] After performing step S210, step S211 to step S214 are sequentially executed.

[0063] Step S211: Perform simulation processing on the initial unit circuit layout according to the interconnect cut layer information to obtain a preset unit circuit layout.

[0064] Step S212: Establish a post-layout simulation netlist according to the preset unit circuit layout, where the post-layout simulation netlist includes a first post-layout simulation netlist.

[0065] Step S213: Establish a first timing model according to the first post-layout simulation netlist.

[0066] Step S214: Perform a first unit circuit function test according to the first post-layout simulation netlist to obtain a first circuit function test result.

[0067] Step S220: Establish a second post-layout simulation netlist according to the initial unit circuit layout.

[0068] After performing step S220, step S221 to step S222 are sequentially executed.

[0069] Step S221: Establish a second timing model according to the second post-layout simulation netlist.

[0070] Step S222: Conduct a second unit circuit function test according to the second post-layout simulation netlist to obtain a second circuit function test result.

[0071] After executing step S214 and step S222, execute step S230.

[0072] Step S230: Obtain a circuit function judgment result according to the first circuit function test result and the second circuit function test result, where the circuit function judgment result includes that the circuit function is qualified or the circuit function is unqualified.

[0073] When the circuit function judgment result is that the circuit function is unqualified, execute step S240.

[0074] Step S240: Modify the initial unit circuit layout.

[0075] After executing step S240, use the modified initial unit circuit layout as the initial unit circuit layout in step S200, restart step S200, and repeat the above steps until the circuit function judgment result is that the circuit function is qualified.

[0076] When the circuit function judgment result is that the circuit function is qualified, execute step S250.

[0077] Step S250: Simulate the integrated circuit according to the first timing model and the second timing model to obtain a simulation result of the integrated circuit.

[0078] Since the initial unit circuit layout is simulated according to the interconnect cut layer information to obtain a preset unit circuit layout, the preset unit circuit layout can preset the modification (extension) situation of several initial interconnect patterns in the design of the top-level circuit layout. Since the post-layout simulation netlist is established according to the preset unit circuit layout, the post-layout simulation netlist can reflect the information data after the modification (extension) of the preset several initial interconnect patterns. Thus, the accuracy of the post-layout simulation netlist for the initial unit circuit layout is improved. Since the accuracy of the post-layout simulation netlist for the initial unit circuit layout is improved, and at the same time, since the post-layout simulation netlist includes the first post-layout simulation netlist, on the one hand, it can improve the accuracy of the first timing model established through the first post-layout simulation netlist. During the process of simulating the integrated circuit according to the first timing model, it is beneficial to improve the accuracy and reliability of the simulation result. On the other hand, it can more accurately judge whether the circuit function of the initial unit circuit layout is qualified. Thus, it can more accurately screen the initial unit circuit layout that can be used for simulating the integrated circuit.

[0079] The following is a detailed description in conjunction with the accompanying drawings.

[0080] Figure 4 It is a schematic diagram of the layout of the initial unit circuit of an embodiment of the present invention.

[0081] Please refer to Figure 4 , perform step S200 to provide an initial unit circuit layout 200, where the initial unit circuit layout 200 includes a number of initial interconnect patterns 201.

[0082] The initial unit circuit layout 200 is used to form a unit circuit, and the initial interconnect pattern 201 is used to form the unit electrical interconnect structure in the unit circuit.

[0083] It should be noted that when performing integrated circuit design, a number of initial unit circuit layouts 200 need to be designed separately first, and then, top-level circuit layout design is performed to form a complete integrated circuit layout. Thus, through the top-level circuit corresponding to the top-level circuit layout, the unit circuits corresponding to the respective initial unit circuit layouts 200 can be electrically connected according to the design requirements. Since each initial unit circuit layout 200 is designed according to the actual functional requirements, therefore, according to whether the actual functional requirements for each initial unit circuit layout 200 are the same or different, the respective unit circuit layouts 200 can also be the same or different.

[0084] It should be noted that for the convenience of understanding the simulation method of the integrated circuit described in this embodiment, Figure 4 3 initial interconnect patterns 201 are schematically illustrated in. Since the initial unit circuit layout 200 is designed according to the actual functional requirements, therefore, the actual number of initial interconnect patterns 201 can be 1 or multiple, and moreover, the shape of the actual initial interconnect pattern 201 can also be different from Figure 4 the shape of the initial interconnect pattern 201 shown. The number and shape of the initial interconnect pattern 201 do not affect the effect of the simulation method of the integrated circuit.

[0085] In this embodiment, the initial unit circuit layout 200 further includes a number of semiconductor device patterns, and the semiconductor device patterns include MOS device patterns (not shown).

[0086] The semiconductor device patterns are used to form the semiconductor devices of the unit circuit, and the MOS device patterns are used to form the MOS transistors in the semiconductor devices.

[0087] In other embodiments, the semiconductor device patterns further include patterns of devices such as resistors and capacitors.

[0088] Please refer to Figure 5 , Figure 5It is a schematic structural diagram of the interconnect cut layer layout of an embodiment of the present invention. Execute step S210 to obtain the interconnect cut layer information.

[0089] In this embodiment, the method for obtaining the interconnect cut layer information includes: providing an interconnect cut layer layout (not labeled in the figure); obtaining the interconnect cut layer information according to the interconnect cut layer layout.

[0090] The interconnect cut layer layout includes a plurality of interconnect cut patterns 301, and the interconnect cut pattern 301 has a boundary 302 of the interconnect cut pattern 301.

[0091] It should be noted that the interconnect cut layer layout is used to form the interconnect cut layer, and the interconnect cut pattern 301 is used to form the interconnect cut structure in the interconnect cut layer. During the process of integrated circuit design, in order to improve the integration degree of the integrated circuit, the top layer circuit layout includes a top layer interconnect structure layout and the interconnect cut layer layout. Thus, on the one hand, a plurality of top layer electrical interconnect structures are formed through the top layer interconnect structure layout to realize the electrical connection between each unit circuit. On the other hand, by transmitting the semiconductor structure formed by the shapes of a plurality of interconnect cut patterns 301 in the interconnect cut layer layout, the unit electrical interconnect structures of each unit circuit, the semiconductor devices of each unit circuit, and a plurality of top layer electrical interconnect structures can be spaced apart. Thus, according to the design requirements, electrical insulation can be achieved between the unit electrical interconnect structures of each unit circuit, between the unit electrical interconnect structure of each unit circuit and the semiconductor device, between the unit electrical interconnect structure of each unit circuit and a plurality of top layer electrical interconnect structures, and between the semiconductor devices of each unit circuit and a plurality of top layer electrical interconnect structures.

[0092] In this embodiment, the interconnect cut layer information includes: the shapes and positions of a plurality of the interconnect cut patterns 301.

[0093] It should be noted that for the convenience of understanding the integrated circuit simulation method described in this embodiment, Figure 5 1 interconnect cut pattern 301 in the interconnect cut layer layout is schematically illustrated. Since the interconnect cut layer layout is designed according to the actual requirements for electrical insulation, the actual number of interconnect cut patterns 301 can be 1 or multiple, and moreover, the shape of the actual interconnect cut pattern 301 can also be different from Figure 5 the shape of the interconnect cut pattern 301 shown. The number and shape of the interconnect cut patterns 301 do not affect the effect of the integrated circuit simulation method.

[0094] It should be noted that for the convenience of understanding the integrated circuit simulation method described in this embodiment, Figure 5 the 1 interconnect cut pattern 301 exemplified is compared with Figure 4The initial unit circuit layout 200 shown is overlapped to facilitate the description of the corresponding position of the interconnect cutting pattern 301 in the initial unit circuit layout 200.

[0095] In other embodiments, the interconnect cutting layer information includes: information reflecting the shapes and positions of a plurality of the interconnect cutting patterns, such as coordinate data reflecting the shapes and positions of a plurality of the interconnect cutting patterns, etc.

[0096] In this embodiment, after step S200 is executed, step S210 is executed.

[0097] In other embodiments, after step S210 is executed, step S200 is executed. Or, step S200 and step S210 are executed simultaneously.

[0098] Since the purpose of executing step S200 and step S210 is to perform simulation processing on the initial unit circuit layout 200 subsequently, that is, to execute step S211, therefore, the execution order between step S200 and step S210 does not affect the effect of the integrated circuit simulation method.

[0099] Please refer to Figure 6 , Figure 6 which is a schematic diagram of a preset unit circuit layout according to an embodiment of the present invention. After step S200 and step S210 are executed, step S211 is executed, and simulation processing is performed on the initial unit circuit layout 200 (as shown in Figure 4 ) according to the interconnect cutting layer information to obtain the preset unit circuit layout 210.

[0100] In this embodiment, the method of the simulation processing includes: obtaining a plurality of to-be-processed patterns (not marked in the figure) according to the interconnect cutting layer information and the initial unit circuit layout 200, where the to-be-processed patterns are initial interconnect patterns 201 adjacent to the interconnect cutting pattern 301 and having different extension directions; extending all the to-be-processed patterns along the extension directions of the to-be-processed patterns to the corresponding associated boundaries 303 to form first interconnect patterns 211, and the corresponding associated boundaries are the boundaries 302 where the interconnect cutting pattern 301 is adjacent to the corresponding to-be-processed patterns.

[0101] Since in this embodiment, in the simulation processing, all the initial interconnect patterns 201 adjacent to the interconnect cutting pattern 301 and having different extension directions are processed (extended to the corresponding associated boundaries 303), therefore, the preset unit circuit layout 210 can preset the most extreme influence of the top-level circuit layout design on the initial unit circuit layout 200, that is: in the process of the top-level circuit layout design, the situation where the most initial interconnect patterns 201 are extended to the limit.

[0102] It should be noted that, for the sake of facilitating the understanding of the method of the simulation process, Figure 6 is represented by a dashed box A in which the extended part of the first interconnect pattern 211 relative to the initial interconnect pattern 201 before the corresponding simulation process (as Figure 4 shown) is shown.

[0103] In another embodiment, the method of the simulation process further includes: obtaining a plurality of to-be-processed patterns according to the interconnect cutting layer information and the initial unit circuit layout, where the to-be-processed patterns are initial interconnect patterns adjacent to the interconnect cutting pattern and having different extension directions; extending 50% of the to-be-processed patterns along the extension direction of the to-be-processed patterns to the corresponding associated boundary to form the first interconnect pattern, where the corresponding associated boundary is the boundary where the interconnect cutting pattern is adjacent to the corresponding to-be-processed pattern. Therefore, compared with the most extreme influence, the preset unit circuit layout can preset the situation where the top-layer circuit layout design has a 50% influence on the initial unit circuit layout, that is: in the process of the top-layer circuit layout design, 50% of the initial interconnect patterns are extended.

[0104] Since the simulation process does not include the processing of the semiconductor device patterns in the initial unit circuit layout 200, the MOS device patterns of the preset unit circuit layout 210 are the same as the MOS device patterns of the initial unit circuit layout 200.

[0105] Please continue to refer to Figure 6 , after obtaining the preset unit circuit layout 210, then perform step S212 to establish a post-layout simulation netlist according to the preset unit circuit layout 210, where the post-layout simulation netlist includes a first post-layout simulation netlist; after step S212, perform step S213 to establish a first timing model according to the first post-layout simulation netlist.

[0106] In this embodiment, the first post-layout simulation netlist includes first RC information.

[0107] In this embodiment, the first post-layout simulation netlist further includes first MOS transistor information.

[0108] In other embodiments, the first post-layout simulation netlist does not include first MOS transistor information.

[0109] In this embodiment, the first MOS transistor information includes ss process corner information.

[0110] In this embodiment, the first timing model can be a static timing model (for static timing analysis) or a dynamic timing model (for dynamic timing analysis).

[0111] Specifically, in this embodiment, the method for establishing the first post-layout simulation netlist according to the preset unit circuit layout 210 includes: obtaining the first RC information according to the initial interconnection pattern 201 and the first interconnection pattern 211 of the preset unit circuit layout 210; obtaining the first MOS transistor information according to the MOS device pattern of the preset unit circuit layout 210.

[0112] It should be noted that due to the influence of the manufacturing process precision in the actual manufacturing process of integrated circuits, there are easily deviations between the actually formed integrated circuit and the integrated circuit corresponding to the integrated circuit layout, resulting in inconsistent characteristics between the actual integrated circuit and the designed integrated circuit. The ss process corner information refers to the relevant process parameter data when the reaction speed of MOS transistors (including NMOS transistors and PMOS transistors) formed in the actual manufacturing process of integrated circuits is the slowest, that is, when the manufacturing process precision is the worst.

[0113] Since the first RC information is obtained according to the initial interconnection pattern 201 and the first interconnection pattern 211 of the preset unit circuit layout 210, the first RC information includes the relevant data information of the most extreme influence of the top-level circuit layout design on the initial unit circuit layout 200. Since the first MOS transistor information is obtained according to the MOS device pattern of the preset unit circuit layout 210, and the first MOS transistor information includes the ss process corner information, the first MOS transistor information includes the relevant data information of the semiconductor device corresponding to the initial unit circuit layout 200 when the manufacturing process deviation is the largest. Thus, the first post-layout simulation netlist includes not only the most adverse effects caused by the manufacturing process precision but also the most extreme effects caused by the top-level circuit layout design, making the accuracy of the first post-layout simulation netlist higher.

[0114] Since the first timing model is established according to the first post-layout simulation netlist, the first timing model can not only reflect the most extreme influence of the manufacturing process precision on the unit circuit but also reflect the most extreme influence of the top-level circuit layout design on the unit electrical interconnection structure. Thus, the first timing model can more accurately reflect the slowest timing situation of the unit circuit after the initial unit circuit layout 200 is affected by the top-level circuit layout design, that is, improve the accuracy of the ss process corner in the simulation. When performing subsequent simulation of the integrated circuit according to the first timing model, it is beneficial to improve the accuracy and reliability of the simulation results.

[0115] In another embodiment, after extending 50% of the to-be-processed pattern along the extension direction of the to-be-processed pattern to the corresponding associated boundary to form a first interconnection pattern, and after obtaining the preset unit circuit layout, a post-layout simulation netlist is established according to the preset unit circuit layout. The post-layout simulation netlist includes a third post-layout simulation netlist. Moreover, a third timing model is established according to the third post-layout simulation netlist. The third timing model can be a static timing model (for static timing analysis) or a dynamic timing model (for dynamic timing analysis). Thus, compared with the most extreme influence, the third post-layout simulation netlist includes the relevant data information when the top-level circuit layout design causes a 50% influence on the initial unit circuit layout, which is beneficial to improving the accuracy of the tt process corner in the simulation.

[0116] In this embodiment, after step S213, step S214 is executed to perform a first unit circuit function test according to the first post-layout simulation netlist to obtain a first circuit function test result.

[0117] It should be noted that the first circuit function test result refers to the data reflecting the unit circuit function corresponding to the preset unit circuit layout 210, that is, the circuit function data of the unit circuit when it is subject to the worst manufacturing process deviation and is most affected by the top-level circuit layout design.

[0118] Similarly, since the accuracy of the first post-layout simulation netlist is improved, after performing the first unit circuit function test according to the first post-layout simulation netlist, a first circuit function test result with higher accuracy can be obtained.

[0119] In other embodiments, after step S214 is executed, step S213 is executed. Or, step S214 and step S213 are executed simultaneously.

[0120] It should be noted that the sequence order between step S213 and step S214 does not affect the effect of the integrated circuit simulation method.

[0121] Please continue to refer to Figure 4 , after step S200, step S220 is executed to establish a second post-layout simulation netlist according to the initial unit circuit layout 200; after step S220, step S221 is executed to establish a second timing model according to the second post-layout simulation netlist.

[0122] In this embodiment, the second post-layout simulation netlist includes second RC information.

[0123] In this embodiment, the second post-layout simulation netlist further includes second MOS transistor information.

[0124] In other embodiments, the second post-layout simulation netlist does not include second MOS transistor information.

[0125] In this embodiment, the second MOS transistor information includes ff process corner information.

[0126] In this embodiment, the second timing model can be a static timing model (for static timing analysis) or a dynamic timing model (for dynamic timing analysis).

[0127] Specifically, in this embodiment, the method for establishing the second post-layout simulation netlist according to the initial cell circuit layout 200 includes: obtaining the second RC information according to the initial interconnection pattern 201 of the initial cell circuit layout 200; and obtaining the second MOS transistor information according to the MOS device pattern of the initial cell circuit layout 200.

[0128] The ff process corner information refers to the process parameter data when the reaction speed of the MOS transistors (including NMOS transistors and PMOS transistors) formed in the actual manufacturing process of the integrated circuit is the fastest, that is, when the manufacturing process accuracy is the best.

[0129] Since the second RC information is obtained according to the initial interconnection pattern 201 of the initial cell circuit layout 200, the second RC information includes the relevant data information when the top-level circuit layout design has no influence on the initial cell circuit layout 200. Since the second MOS transistor information is obtained according to the MOS device pattern of the initial cell circuit layout 200, and the second MOS transistor information includes ff process corner information, the second MOS transistor information includes the relevant data information of the semiconductor devices corresponding to the initial cell circuit layout 200 when the manufacturing process deviation is the least. Thus, the second post-layout simulation netlist includes the relevant data information when the influence caused by the manufacturing process deviation is the least and the influence caused by the top-level circuit layout design is the least.

[0130] Since the second timing model is established according to the second post-layout simulation netlist, the second timing model can reflect the fastest timing situation of the cell circuit.

[0131] In this embodiment, after step S221, step S222 is executed to perform a second cell circuit function test according to the second post-layout simulation netlist to obtain a second circuit function test result.

[0132] It should be noted that the second circuit function test result refers to the data reflecting the cell circuit function corresponding to the initial cell circuit layout 200, that is, the circuit function data of the cell circuit when it is subject to the least manufacturing process deviation and is not affected by the top-level circuit layout design.

[0133] In other embodiments, after step S222 is executed, step S221 is executed. Or, step S222 and step S221 are executed simultaneously.

[0134] It should be noted that the sequence order between step S221 and step S222 does not affect the effect of the integrated circuit simulation method.

[0135] In this embodiment, after performing step S214 and step S222, step S230 is performed.

[0136] Step S230: Obtain a circuit function judgment result according to the first circuit function test result and the second circuit function test result, where the circuit function judgment result includes that the circuit function is qualified or the circuit function is unqualified.

[0137] Since the accuracy of the first circuit function test result is improved, therefore, it is possible to more accurately judge whether the circuit function of the initial unit circuit layout 200 is qualified, and thus, it is possible to more accurately screen the initial unit circuit layout 200 that can be used for integrated circuit simulation.

[0138] Specifically, in this embodiment, the method for obtaining the circuit function judgment result includes: providing a design specification standard; when the first circuit function test result is within the design specification standard range, and when the second circuit function test result is within the design specification standard range, the circuit function judgment result is that the circuit function is qualified; when the first circuit function test result or the second circuit function test result is outside the design specification standard range, the circuit function judgment result is that the circuit function is unqualified.

[0139] It should be noted that since the sequence order between step S213, step S221 and step S230 does not affect the effect of the integrated circuit simulation method, therefore, in other embodiments, step S213 and step S221 can also be performed after step S230, or step S213 or step S221 and step S230 are performed simultaneously.

[0140] Next, in this embodiment, when the circuit function judgment result is that the circuit function is unqualified, step S240 is performed to modify the initial unit circuit layout 200.

[0141] After performing step S240, the modified initial unit single circuit layout is used as the initial unit circuit layout in step S200, and step S200 is restarted and the above steps are repeated until the circuit function judgment result is that the circuit function is qualified.

[0142] In other embodiments, step S240 is not performed, the initial unit single circuit layout 200 is abandoned, and a new initial unit circuit layout is redesigned.

[0143] In this embodiment, when the circuit function judgment result is that the circuit function is qualified, step S250 is executed to simulate the integrated circuit according to the first timing model and the second timing model, and obtain the simulation result of the integrated circuit.

[0144] The first timing model can more accurately reflect the slowest timing situation of the unit circuit after the initial unit circuit layout 200 is affected by the top-level circuit layout design. Therefore, the accuracy of the simulation result of the integrated circuit is improved, and the timing range of the integrated circuit is more accurately simulated, which is beneficial to improving the accuracy and reliability of the simulation result.

[0145] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A simulation method for an integrated circuit, characterized in that, Including: Providing an initial unit circuit layout, the initial unit circuit layout including a plurality of initial interconnect patterns; Obtaining interconnect cut layer information; Performing simulation processing on the initial unit circuit layout according to the interconnect cut layer information to obtain a preset unit circuit layout; Establishing a post-layout simulation netlist according to the preset unit circuit layout; The method of the simulation processing includes: obtaining a plurality of graphics to be processed according to the interconnect cut layer information and the initial unit circuit layout, the graphics to be processed being initial interconnect patterns adjacent to the interconnect cut pattern and having different extension directions; Extending all the graphics to be processed along the extension direction of the graphics to be processed to a corresponding associated boundary to form a first interconnect pattern, the corresponding associated boundary being the boundary where the interconnect cut pattern is adjacent to the corresponding graphic to be processed.

2. The simulation method of the integrated circuit according to claim 1, wherein, The method of obtaining the interconnect cut layer information includes: providing an interconnect cut layer layout; obtaining the interconnect cut layer information according to the interconnect cut layer layout; the interconnect cut layer layout including a plurality of interconnect cut patterns.

3. The simulation method of the integrated circuit according to claim 2, wherein The interconnect cut layer layout includes a plurality of interconnect cut patterns; The interconnect cut layer information includes: the shapes and positions of a plurality of the interconnect cut patterns.

4. The simulation method of an integrated circuit according to claim 2, characterized in that, The interconnect cut layer layout includes a plurality of interconnect cut patterns; The interconnect cut layer information includes: information reflecting the shapes and positions of a plurality of the interconnect cut patterns.

5. The simulation method of the integrated circuit according to claim 3 or 4, characterized in that, The post-layout simulation netlist includes a first post-layout simulation netlist, and the first post-layout simulation netlist includes first RC information.

6. The simulation method of the integrated circuit according to claim 5, characterized in that, The method of establishing a first post-layout simulation netlist according to the preset unit circuit layout includes: obtaining the first RC information according to the initial interconnect patterns and the first interconnect pattern of the preset unit circuit layout.

7. The simulation method of the integrated circuit according to claim 6, wherein, The first post-layout simulation netlist further includes first MOS transistor information.

8. The simulation method of an integrated circuit according to claim 7, wherein The initial unit circuit layout further includes a plurality of MOS device patterns, and the MOS device patterns of the preset unit circuit layout are the same as those of the initial unit circuit layout; The method of establishing a first post-layout simulation netlist according to the preset unit circuit layout further includes: obtaining the first MOS transistor information according to the MOS device patterns of the preset unit circuit layout.

9. The simulation method of the integrated circuit according to claim 8, characterized in that, The first MOS transistor information includes ss process corner information.

10. The simulation method of the integrated circuit according to claim 9, characterized in that, Also including: Establishing a first timing model according to the first post-layout simulation netlist.

11. The simulation method of the integrated circuit according to claim 10, characterized in that, Also including: Establishing a second post-layout simulation netlist according to the initial unit circuit layout.

12. The simulation method of the integrated circuit according to claim 11, wherein, The second post-layout simulation netlist includes second RC information; the method of establishing a second post-layout simulation netlist according to the initial unit circuit layout includes: obtaining the second RC information according to the initial interconnect patterns of the initial unit circuit layout.

13. The simulation method of the integrated circuit according to claim 12, wherein, The second post-layout simulation netlist further includes second MOS transistor information; the method of establishing a second post-layout simulation netlist according to the initial unit circuit layout further includes: obtaining the second MOS transistor information according to the MOS device patterns of the initial unit circuit layout, and the second MOS transistor information includes ff process corner information.

14. The simulation method of the integrated circuit according to claim 13, wherein Also including: Establishing a second timing model according to the second post-layout simulation netlist.

15. The simulation method of the integrated circuit according to claim 14, wherein, Also including: Performing a first unit circuit function test according to the first post-layout simulation netlist to obtain a first circuit function test result; Perform a second unit circuit function test based on the second post-layout netlist to obtain a second circuit function test result; Obtain a circuit function judgment result based on the first circuit function test result and the second circuit function test result, where the circuit function judgment result includes that the circuit function is qualified or unqualified.

16. The simulation method of the integrated circuit according to claim 15, characterized in that, The method for obtaining the circuit function judgment result includes: providing a design specification standard; when the first circuit function test result is within the range of the design specification standard and when the second circuit function test result is within the range of the design specification standard, the circuit function judgment result is that the circuit function is qualified; when the first circuit function test result or the second circuit function test result is outside the range of the design specification standard, the circuit function judgment result is that the circuit function is unqualified.

17. The simulation method of the integrated circuit according to claim 16, wherein It further includes: When the circuit function judgment result is that the circuit function is qualified, perform simulation on the integrated circuit according to the first timing model and the second timing model to obtain a simulation result of the integrated circuit.

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