Control circuit for ternary content addressable memory

Abstract

The present invention discloses a control circuit for a ternary content addressable memory (TCAM). The control circuit includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line, and a second power supply line. When the voltages of the first search line and the second search line match the voltages of the first storage unit and the second storage unit, the second logic unit provides a path to electrically connect the first power supply line to the second power supply line.

Description

[0001] This patent application is a divisional application of the following invention patent applications:

[0002] Application number: 201810777449.7

[0003] Application date: July 16, 2018

[0004] Invention Title: Control Circuit for Ternary Content Addressable Memory Technical Field

[0005] The present invention relates to a control circuit for a ternary content addressable memory, and more particularly to a control circuit for electrically connecting two power supply lines when the voltages of a search line and a storage voltage match each other. Background Art

[0006] Ternary content-addressable memory (TCAM) is currently commonly used in applications supporting high-volume lookups, such as URL lookups. In a typical TCAM, each memory cell can support three data states: 1, 0, and don't care. Because multiple memory cells can be arranged in an array, they can be compared simultaneously during large-volume lookups, thus supporting high-speed lookups. However, this architecture has the following technical disadvantages. In conventional architectures, multiple memory cells are coupled to a match line. During the first period of the search phase (also known as the precharge period), the match line is charged to a high voltage. If the data on the search line does not match the data in any of the multiple memory cells, a discharge path is provided. During the second period (also known as the evaluation period), the match line is drained to a low voltage, thereby determining a data mismatch. In other words, the voltage change on the match line can be observed to determine whether a mismatch has occurred. However, when a large number of memory cells are coupled to the match line, the increased load makes it difficult to avoid unintended leakage. Therefore, it is possible that even if all memory cells have matched, the voltage on the match line may erroneously drop too low due to leakage, leading to subsequent misjudgments. Furthermore, the node voltage on the match line may also erroneously drop due to charge sharing, leading to misjudgments.

[0007] In addition to the above two deficiencies that may cause misjudgment, the current three-state content-addressable memory must first charge the match line during the pre-charge period and then observe the voltage changes on the match line during the evaluation period, which increases the temporal complexity of the operation and makes the design more difficult. Summary of the Invention

[0008] An embodiment provides a control circuit for a ternary content-addressable memory, the control circuit comprising a first logic unit and a second logic unit. The first logic unit comprises a first terminal coupled to a data access terminal of a first memory cell for receiving a first storage voltage; a second terminal coupled to a data access terminal of a second memory cell for receiving a second storage voltage; a third terminal coupled to a first search line; a fourth terminal coupled to a second search line; a fifth terminal coupled to a reference voltage terminal; and a sixth terminal coupled to a match line. The second logic unit comprises a first terminal coupled to the data access terminal of the first memory cell; a second terminal coupled to the data access terminal of the second memory cell; a third terminal coupled to the first search line; a fourth terminal coupled to the second search line; a fifth terminal coupled to a first power supply line; and a sixth terminal coupled to a second power supply line. When the first search voltage of the first search line and the second search voltage of the second search line match the first storage voltage and the second storage voltage, the second logic unit can provide a path to electrically connect the first power supply line to the second power supply line. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 1 is an application diagram of a control circuit in an embodiment.

[0010] Figure 2 In the embodiment, Figure 1 Application diagram of the control circuit.

[0011] Figure 3 In the embodiment, Figure 1 Application diagram of the control circuit.

[0012] Figure 4 In the embodiment, Figure 1 Schematic diagram of an application where the control circuit is located in the first stage of the array.

[0013] Figure 5 In the embodiment, Figure 1 Schematic diagram of an application where the control circuit is located at the last stage of the array.

[0014] Figures 6 to 9 In the embodiment, Figure 1 Schematic diagram of the coupling between the control circuit in the ternary content addressable memory array and the previous stage array unit and the previous stage array unit.

[0015] Figure 10 In the embodiment, Figure 1 、 Figure 4 、 Figure 5 and Figure 7 Figure 2 shows a circuit diagram of a ternary content addressable memory array.

[0016] Figure 11 yes Figure 1Schematic diagram of an embodiment in which the first storage unit and the second storage unit are static random access memories.

[0017]

Main component symbol description

[0018] 100 Control Circuit

[0019] 110 First Logic Unit

[0020] 120 Second Logic Unit

[0021] 19 Ternary Content Addressable Memory

[0022] 191 First storage unit

[0023] 192 Second storage unit

[0024] Va first storage voltage

[0025] Vb second storage voltage

[0026] SL, SL0, SL1, SL2, SLn First search line

[0027] SLB, SLB0, SLB1, SLB2, second search line SLBn

[0028] Vs1 first search voltage

[0029] Vs2 Second search voltage

[0030] t11, t21 first end

[0031] t12, t22 second end

[0032] t13, t23 third end

[0033] t14, t24 fourth end

[0034] t15, t25 fifth end

[0035] t16, t26 sixth end

[0036] ML, ML0, ML1, ML2, match line MLm

[0037] MLB1, MLB 6i1 , MLB 6(i+1)1 、 First power line MLB 7i1 , MLB 7(i+1)1 , MLB 8i1 , MLB 8(i+1)1 , MLB 9i1 , MLB 9(i+1)1

[0038] MLB2, MLB 6i2 , MLB 6(i+1)2 , Second power line MLB 7i2 , MLB 7(i+1)2 , MLB 8i2 , MLB 8(i+1)2 , MLB 9i2 , MLB 9(i+1)2

[0039] MLB00, MLB10, MLB20, power supply line MLBm0

[0040] Vref reference voltage terminal

[0041] Vcc high voltage

[0042] Vss low voltage

[0043] T11, T12, T13, T14, T21, switch T22, T23, T24, T11', T12', T13', T14', T21', T22', T23', T24'

[0044] Vd Enable Voltage

[0045] 510 Sense Amplifier

[0046] 6i, 7i, 8i, 9i pre-array units

[0047] 6(i+1), 7(i+1), 8(i+1), 9(i+1) rear array unit

[0048] x00, x01, x02, x0n, x10, array elements x11, x12, x1n, x20, x21, x22, x2n, xm0, xm1, xm2, xmn,

[0049] R0, R1, R2, Rm result signal

[0050] path2 conductive path

[0051] PU11, PU12, PD11, PD12, transistors PG11, PG12, PU21, PU22, PD21, PD22, PG21, PG22

[0052] WL word line

[0053] BLa, BLBa, BLb, BLBb bit lines DETAILED DESCRIPTION

[0054] Figure 11 is a schematic diagram of an application of a control circuit 100 in an embodiment. The control circuit 100 is used to control a ternary content addressable memory 19 . The ternary content addressable memory 19 includes a first storage unit 191 and a second storage unit 192 . The control circuit 100 includes a first logic unit 110 and a second logic unit 120 . Figure 1 The control circuit 100 and the ternary content addressable memory 19 may constitute an array unit, which may be part of an array of ternary content addressable memories. The array will be described below. The first logic unit 110 may include a first terminal t11 to a sixth terminal t16. The first terminal t11 is coupled to the data access terminal of the first storage unit 191 for receiving the first storage voltage Va. The second terminal t12 is coupled to the data access terminal of the second storage unit 192 for receiving the second storage voltage Vb. The third terminal t13 is coupled to the first search line SL. The fourth terminal t14 is coupled to the second search line SLB. The fifth terminal t15 is coupled to the reference voltage terminal Vref. And the sixth terminal t16 is coupled to the match line ML. The second logic unit 120 may include a first terminal t21 to a sixth terminal t26. The first terminal t21 is coupled to the data access terminal of the first storage unit 191 for receiving the first storage voltage Va. The second terminal t22 is coupled to the data access terminal of the second storage cell 192 for receiving the second storage voltage Vb. The third terminal t23 is coupled to the first search line SL. The fourth terminal t24 is coupled to the second search line SLB. The fifth terminal t25 is coupled to the first power line MLB1. The sixth terminal t26 is coupled to the second power line MLB2. When the first search voltage Vs1 of the first search line SL and the second search voltage Vs2 of the second search line SLB match the first storage voltage Va and the second storage voltage Vb, the second logic unit 120 can provide a path to electrically connect the first power line MLB1 to the second power line MLB2.

[0055] The matching of the first search voltage Vs1 of the first search line SL and the second search voltage Vs2 of the second search line SLB with the first storage voltage Va and the second storage voltage Vb can be described in Table 1 below.

[0056]

[0057] (Table 1)

[0058] Table 1 is explained as follows. When the data expected to be stored in the ternary content-addressable memory 19 is a logic 0, the first storage voltage Va can be set to a logic 0 (e.g., the first voltage) and the second storage voltage Vb can be set to a logic 1 (e.g., the second voltage). In this case, if the first search voltage Vs1 is set to a logic 0 and the second search voltage Vs2 is set to a logic 1, the first search voltage Vs1 and the second search voltage Vs2 can be considered to match the first storage voltage Va and the second storage voltage Vb. Furthermore, if the first search voltage Vs1 and the second search voltage Vs2 are set to other voltages, they can be considered to be mismatched. The first and second voltages can be different voltages, such as a high voltage and a low voltage, respectively.

[0059] When the data expected to be stored in the ternary content-addressable memory 19 is a logic 1, the first storage voltage Va can be set to a logic 1 and the second storage voltage Vb can be set to a logic 0. In this case, if the first search voltage Vs1 is set to a logic 1 and the second search voltage Vs2 is set to a logic 0, the first search voltage Vs1 and the second search voltage Vs2 can be considered to match the first storage voltage Va and the second storage voltage Vb. Furthermore, if the first search voltage Vs1 and the second search voltage Vs2 are set to other voltages, they can be considered to be mismatched.

[0060] When the data expected to be stored in the ternary content addressable memory 19 is X (no comparison), the first storage voltage Va can be set to logic 0 and the second storage voltage Vb can be set to logic 0. In this case, no matter what voltages the first search voltage Vs1 and the second search voltage Vs2 are set to, the first search voltage Vs1 and the second search voltage Vs2 can be considered to match the first storage voltage Va and the second storage voltage Vb.

[0061] According to an embodiment, the setting of setting the first storage voltage Va to logic 1 and setting the second storage voltage Vb to logic 1 is a disabled setting and is currently unusable.

[0062] Table 1 above is only an example to illustrate the application and operation of the circuit, and is not intended to limit the embodiments. Other reasonable variations also fall within the scope of the embodiments.

[0063] Figure 2 In the embodiment, Figure 1 Schematic diagram of an application of the control circuit 100. Figure 2 In the embodiment of FIG, the control circuit 100 may be of AND type. Figure 2 , the first logic unit 110 may include switches T11 to T14 , and the second logic unit 120 may include switches T21 to T24 .

[0064] like Figure 2In the first logic unit 110, the switch T11 may include a first end coupled to the fifth end t15 of the first logic unit 110, a second end, and a control end coupled to one of the second end t12 and the third end t13 of the first logic unit 110. The switch T12 may include a first end coupled to the second end of the switch T11, a second end coupled to the sixth end t16 of the first logic unit 110, and a control end coupled to the other of the second end t12 and the third end t13 of the first logic unit 110. In other words, the control ends of the switch T11 and the switch T12 may be coupled to the second end t12 and the third end t13, respectively, or to the third end t13 and the second end t12, respectively. The switch T13 may include a first end coupled to the fifth end t15 of the first logic unit 110, a second end, and a control end coupled to one of the first end t11 and the fourth end t14 of the first logic unit 110. The switch T14 may include a first terminal coupled to the second terminal of the switch T13, a second terminal coupled to the sixth terminal t16 of the first logic unit 110, and a control terminal coupled to the other of the first terminal t11 and the fourth terminal t14 of the first logic unit 110. In other words, the control terminals of the switch T13 and the switch T14 may be coupled to the first terminal t11 and the fourth terminal t14, respectively, or to the fourth terminal t14 and the first terminal t11, respectively.

[0065] like Figure 2 In the second logic unit 120, the switch T21 may include a first end coupled to the fifth end t25 of the second logic unit 120, a second end, and a control end coupled to one of the first end t21 and the third end t23 of the second logic unit 120. The switch T22 may include a first end coupled to the second end of the switch T21, a second end coupled to the sixth end t26 of the second logic unit 120, and a control end coupled to the other of the first end t21 and the third end t23 of the second logic unit 120. In other words, the control ends of the switch T21 and the switch T22 may be coupled to the first end t21 and the third end t23, respectively, or to the third end t23 and the first end t21, respectively. The switch T23 may include a first end coupled to the fifth end t25 of the second logic unit 120, a second end, and a control end coupled to one of the second end t22 and the fourth end t24 of the second logic unit 120. The switch T24 may include a first terminal coupled to the second terminal of the switch T23, a second terminal coupled to the sixth terminal t26 of the second logic unit 120, and a control terminal coupled to the other of the second terminal t22 and the fourth terminal t24 of the second logic unit 120. In other words, the control terminals of the switch T23 and the switch T24 may be coupled to the second terminal t22 and the fourth terminal t24, respectively, or to the fourth terminal t24 and the second terminal t22, respectively.

[0066] Figure 2In the embodiment, the switches T11, T12, T13 and T14 may be n-type transistors, the switches T21, T22, T23 and T24 may be p-type transistors, and the reference voltage terminal Vref may have a low voltage Vss, such as a ground voltage.

[0067] according to Figure 2 When the first search voltage Vs1 and the second search voltage Vs2 match the first storage voltage Va and the second storage voltage Vb, the switches T21 and T22 of the second logic unit 120 can be turned on synchronously, or the switches T23 and T24 can be turned on synchronously, thereby providing a conductive path to electrically connect the first power line MLB1 to the second power line MLB2.

[0068] Figure 3 In the embodiment, Figure 1 Schematic diagram of an application of the control circuit 100. Figure 3 In the embodiment of FIG. 1 , the control circuit 100 may be a NAND type. Figure 3 , the first logic unit 110 may include switches T11 ′ to T14 ′, and the second logic unit 120 may include switches T21 ′ to T24 ′.

[0069] like Figure 3 In the first logic unit 110, the switch T11' may include a first end coupled to the fifth end t15 of the first logic unit 110, a second end, and a control end coupled to one of the second end t12 and the third end t13 of the first logic unit 110. The switch T12' may include a first end coupled to the second end of the switch T11', a second end coupled to the sixth end t16 of the first logic unit 110, and a control end coupled to the other of the second end t12 and the third end t13 of the first logic unit 110. In other words, the control ends of the switch T11' and the switch T12' may be coupled to the second end t12 and the third end t13, respectively, or to the third end t13 and the second end t12, respectively. The switch T13' may include a first end coupled to the fifth end t15 of the first logic unit 110, a second end, and a control end coupled to one of the first end t11 and the fourth end t14 of the first logic unit 110. The switch T14' may include a first terminal coupled to the second terminal of the switch T13', a second terminal coupled to the sixth terminal t16 of the first logic unit 110, and a control terminal coupled to the other of the first terminal t11 and the fourth terminal t14 of the first logic unit 110. In other words, the control terminals of the switch T13' and the switch T14' may be coupled to the first terminal t11 and the fourth terminal t14, respectively, or to the fourth terminal t14 and the first terminal t11, respectively.

[0070] like Figure 3In the second logic unit 120, the switch T21′ may include a first end coupled to the fifth end t25 of the second logic unit 120, a second end, and a control end coupled to one of the first end t21 and the third end t23 of the second logic unit 120. The switch T22′ may include a first end coupled to the second end of the switch T21′, a second end coupled to the sixth end t26 of the second logic unit 120, and a control end coupled to the other of the first end t21 and the third end t23 of the second logic unit 120. In other words, the control ends of the switch T21′ and the switch T22′ may be coupled to the first end t21 and the third end t23, respectively, or to the third end t23 and the first end t21, respectively. The switch T23′ may include a first end coupled to the fifth end t25 of the second logic unit 120, a second end, and a control end coupled to one of the second end t22 and the fourth end t24 of the second logic unit 120. The switch T24′ may include a first end coupled to the second end of the switch T23′, a second end coupled to the sixth end t26 of the second logic unit 120, and a control end coupled to the other of the second end t22 and the fourth end t24 of the second logic unit 120. In other words, the control ends of the switch T23′ and the switch T24′ may be coupled to the second end t22 and the fourth end t24, respectively, or to the fourth end t24 and the second end t22, respectively.

[0071] Figure 3 In the embodiment, the switches T11 ′, T12 ′, T13 ′, and T14 ′ may be p-type transistors, and the switches T21 ′, T22 ′, T23 ′, and T24 ′ may be n-type transistors. Figure 3 In the embodiment of FIG. 5 , the reference voltage terminal Vref may have a high voltage Vcc, such as a voltage provided by a voltage supplier.

[0072] according to Figure 3 When the first search voltage Vs1 and the second search voltage Vs2 match the first storage voltage Va and the second storage voltage Vb, the switches T21' and T22' of the second logic unit 120 can be synchronously turned on, or the switches T23' and T24' can be synchronously turned on, thereby providing a conductive path to electrically connect the first power line MLB1 to the second power line MLB2.

[0073] According to an embodiment, a plurality of control circuits 100 can be used to control a plurality of groups of memory cells respectively, and are arranged in an array. Figure 4 In the embodiment, Figure 1 The control circuit 100 is located in the first level of the array. The first level of the array mentioned here is the first level of the array. If the number starts from 0, it can also be called level 0. Figure 4, the first power line MLB1 or the second power line MLB2 of the control circuit 100 at the first stage can be used to receive the enabling voltage Vd, which can be equal to the high voltage Vcc. Figure 4 In one embodiment, the first power line MLB1 receives the enable voltage Vd, and the second power line MLB2 is used to couple to the next stage of the array; in another embodiment, the second power line MLB2 can receive the enable voltage Vd, and the first power line MLB1 can be used to couple to the next stage.

[0074] Figure 5 In the embodiment, Figure 1 Schematic diagram of an application in which the control circuit 100 is located at the last stage of the array. According to an embodiment, the first power supply line MLB1 or the second power supply line MLB2 of the control circuit 100 located at the last stage can be coupled to the matching line ML. Figure 5 In one embodiment, when the first power line MLB1 is coupled to the previous stage of the array, the second power line MLB2 can be coupled to the match line ML. In another embodiment, when the second power line MLB2 is coupled to the previous stage of the array, the first power line MLB1 can be coupled to the match line ML. According to another embodiment, the control circuit 100 at the final stage can be externally connected to a sense amplifier 510 to amplify the voltage on the match line ML. If the voltage on the match line ML is too low, it can be determined that a mismatch has occurred during the search process.

[0075] Figures 6 to 9 In the embodiment, Figure 1 Schematic diagram of the coupling between the control circuit of the ternary content addressable memory array, the previous stage array unit and the next stage array unit. Figures 6 to 9 Therefore Figure 2 Take the circuit type as an example. Figure 6 In the preceding array unit 6i, the second power supply line MLB 6i2 The first power supply line MLB of the previous array unit 6i can be coupled to the previous array unit. 6i1 A first power line MLB coupled to the subsequent array unit 6(i+1) 6(i+1)1 , and the second power supply line MLB of the subsequent array unit 6(i+1) 6(i+1)2 Can be coupled to a later-stage array unit. Figure 7 In the preceding array unit 7i, the first power supply line MLB 7i1 The second power supply line MLB of the previous array unit 7i can be coupled to the previous array unit. 7i2 A first power line MLB coupled to the subsequent array unit 7(i+1) 7(i+1)1 , and the second power supply line MLB of the subsequent array unit 7(i+1) 7(i+1)2 Can be coupled to a later-stage array unit. Figure 8In the preceding array unit 8i, the second power supply line MLB 8i2 The first power supply line MLB of the previous array unit 8i can be coupled to the previous array unit. 8i1 A second power supply line MLB coupled to the subsequent array unit 8(i+1) 8(i+1)2 , and the first power supply line MLB of the subsequent array unit 8(i+1) 8(i+1)1 Can be coupled to a later-stage array unit. Figure 9 In the preceding array unit 9i, the first power supply line MLB 9i1 The second power supply line MLB of the previous array unit 9i can be coupled to the previous array unit. 9i2 A second power supply line MLB coupled to the subsequent array unit 9(i+1) 9(i+1)2 , and the first power supply line MLB of the subsequent array unit 9(i+1) 9(i+1)1 It can be coupled to the array unit at a later stage. In other words, the first power supply line and the second power supply line of the previous stage array unit, and the first power supply line and the second power supply line of the next stage array unit, can form a controllable conductive path, so that when the search of the previous stage array unit and the next stage array unit are matched, the enable voltage can be transmitted through the conductive path. For related applications, see Figure 10 .

[0076] Figure 10 In the embodiment, Figure 1 、 Figure 4 、 Figure 5 and Figure 7 Figure 2 shows a circuit diagram of a ternary content addressable memory array. Figure 10 In the embodiment, each array unit may include a first logic unit, a second logic unit, a first storage unit, and a second storage unit. Figure 10 The control circuit is based on Figure 2 This is just an example and is not intended to limit the embodiment. Figure 10 In FIG. 1 , each first storage unit and each second storage unit are represented by a circuit consisting of two inverters to represent the function of the storage unit. Figure 10 In the example, the array element in the i-th row and the j-th column can be represented as array element xij, where i and j are integers greater than or equal to 0, 0≤i≤m, 0≤j≤n. The leftmost array elements x00 to xm0 can be mapped to Figure 4 That is, in the array units x00 to xm0, the first power supply line or the second power supply line of the second logic unit of each array unit (for example, x10) can receive an enable voltage. Figure 10 In the example, the enabling voltage is the high voltage Vcc. Figure 10In the figure, the rightmost array elements x0n to xmn correspond to Figure 5 That is, in the array cells x0n to xmn, the second power supply line or the first power supply line of the second logic unit of each array cell can be coupled to the corresponding matching lines ML0 to MLm, respectively. Figure 10 In the example, two adjacent array cells in the same row are Figure 7 However, this is just an example. According to the embodiment, two adjacent array units can also be coupled using Figure 6 、 Figure 8 or Figure 9 mode coupling.

[0077] Now Figure 10 Line 2 (that is, Figure 10 , the third row from the top is used as an example. If the first search voltage and the second search voltage of each array cell in array cells x20 through x2n match the first storage voltage and the second storage voltage (the matching conditions can be found in Table 1 above), the second logic unit in the control circuit of each array cell can provide a conductive path. Thus, a conductive path path2 can be obtained, and an enable voltage (e.g., a high voltage Vcc) can be used to charge the match line ML2 via the conductive path path2. This prevents the voltage of the match line from erroneously dropping due to excessive load or charge sharing, thereby preventing misjudgment. Furthermore, according to the embodiment, there is no need to charge the match line during the precharge period, thereby simplifying the timing design. Figure 10 In the example, the second logic unit of each row of the 0th level array unit is used to receive the power supply lines of the enable voltage, which are respectively power supply lines MLB00, MLB10, MLB20 to MLBm0 as shown in the figure.

[0078] According to an embodiment, an array of a ternary content addressable memory can be searched synchronously, for example, Figure 10 The first search line SL0 and the second search line SLB0 can synchronously search and compare the data stored in array cells x00 through xm0. The first search line SL1 and the second search line SLB1 can synchronously search and compare the data stored in array cells x01 through xm1. Similarly, the first search line SLn and the second search line SLBn can synchronously search and compare the data stored in array cells x0n through xmn. Therefore, result signals R0 through Rm can be generated virtually synchronously, and whether the search results in each row match can be determined based on result signals R0 through Rm. For the array cells in row i to reach an enable voltage, all search results must match.

[0079] Figure 11 yes Figure 1 In the embodiment of FIG. 1 , the first storage unit 191 and the second storage unit 192 are schematic diagrams of static random access memories (SRAMs). Figure 11 In the example, the first logic unit 110 and the second logic unit 120 are Figure 2 Taking the circuit of as an example, the first storage unit 191 and the second storage unit 192 can be static random access memories having six transistors respectively. Figure 11 In first memory cell 191, transistors PU11 and PU12 are pull-up transistors, transistors PD11 and PD12 are pull-down transistors, control terminals of transistors PG11 and PG12 can be coupled to word line WL, and transistors PG11 and PG12 can be coupled to bit lines BLa and BLBa, respectively. A node coupled to transistors PG11, PD11, and PU11 can store a first storage voltage Va. Figure 11 In second storage cell 192, transistors PU21 and PU22 are pull-up transistors, transistors PD21 and PD22 are pull-down transistors, control terminals of transistors PG21 and PG22 can be coupled to word line WL, and transistors PG21 and PG22 can be coupled to bit lines BLb and BLBb, respectively. The node coupled to transistors PG21, PD21, and PU21 can store a second storage voltage Vb.

[0080] Figure 11 For example only, the first storage unit 191 and the second storage unit 192 are not limited to static random access memory. According to an embodiment, the first storage unit 191 and the second storage unit 192 may also be dynamic random access memory (DRAM), flash memory (FLASH), or other memory that supports ternary content addressable memory operations.

[0081] In summary, the ternary content-addressable memory control circuit, its coupling scheme, and its operating method provided in the embodiments can prevent the voltage of the match line from erroneously dropping due to excessive load or charge sharing, thereby avoiding misjudgments. Furthermore, there is no need to charge the match line during the precharge period, simplifying the timing design and reducing its complexity and difficulty, which is helpful in addressing the challenges in this field.

[0082] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A control circuit for a ternary content addressable memory, characterized in that: The control circuit comprises: The first logic unit includes: The first terminal is coupled to the data access terminal of the first memory unit and is used to receive a first storage voltage; The second end is coupled to the data access end of the second memory unit and is used to receive a second storage voltage; The third end is coupled to the first search line; The fourth end is coupled to the second search line; The fifth terminal is coupled to the reference voltage terminal; and The sixth terminal is coupled to the matching line; and The second logic unit includes: A first end is coupled to the data access end of the first storage unit; The second end is coupled to the data access end of the second storage unit; The third end is coupled to the first search line; The fourth end is coupled to the second search line; The fifth end is coupled to the first power supply line; and The sixth end is coupled to the matching line; The control circuit further includes a sense amplifier coupled to the match line such that when the control circuit is in the last stage of the array, a low voltage on the match line determines that the result of the lookup is a no match; The second logic unit provides a conductive path, and an enable voltage charges the match line through the conductive path.

2. The control circuit of claim 1 , wherein when a first search voltage of the first search line and a second search voltage of the second search line match the first storage voltage and the second storage voltage, the second logic unit provides a path to electrically connect the first power line to the second power line.

3. The control circuit according to claim 2, wherein: When the first lookup voltage and the second lookup voltage match the first storage voltage and the second storage voltage, the first lookup voltage is equal to the first storage voltage, and the second lookup voltage is equal to the second storage voltage.

4. The control circuit according to claim 2, wherein: When the first search voltage and the second search voltage match the first storage voltage and the second storage voltage, the first storage voltage and the second storage voltage correspond to a non-comparison state.

5. The control circuit according to claim 1, wherein: The second logic unit further includes: a first switch comprising a first terminal coupled to the fifth terminal of the second logic unit, a second terminal, and a control terminal coupled to one of the first terminal and the third terminal of the second logic unit; a second switch comprising a first terminal coupled to the second terminal of the first switch, a second terminal coupled to the sixth terminal of the second logic unit, and a control terminal coupled to the other of the first terminal and the third terminal of the second logic unit; a third switch including a first terminal coupled to the fifth terminal of the second logic unit, a second terminal, and a control terminal coupled to one of the second terminal and the fourth terminal of the second logic unit; and The fourth switch includes a first end coupled to the second end of the third switch, a second end coupled to the sixth end of the second logic unit, and a control end coupled to the other of the second end and the fourth end of the second logic unit.

6. The control circuit according to claim 5, wherein: The first switch, the second switch, the third switch, and the fourth switch are p-type transistors.

7. The control circuit according to claim 5, wherein: The first logic unit further includes: a fifth switch comprising a first terminal coupled to the fifth terminal of the first logic unit, a second terminal, and a control terminal coupled to one of the second terminal and the third terminal of the first logic unit; a sixth switch comprising a first terminal coupled to the second terminal of the fifth switch, a second terminal coupled to the sixth terminal of the first logic unit, and a control terminal coupled to the other of the second terminal and the third terminal of the first logic unit; a seventh switch comprising a first terminal coupled to the fifth terminal of the first logic unit, a second terminal, and a control terminal coupled to one of the first terminal and the fourth terminal of the first logic unit; and An eighth switch includes a first end coupled to the second end of the seventh switch, a second end coupled to the sixth end of the first logic unit, and a control end coupled to the other of the first end and the fourth end of the first logic unit.

8. The control circuit according to claim 7, wherein: The fifth switch, the sixth switch, the seventh switch, and the eighth switch are n-type transistors.

9. The control circuit according to claim 5, wherein: The first switch, the second switch, the third switch, and the fourth switch are n-type transistors.

10. The control circuit according to claim 7, wherein: The fifth switch, the sixth switch, the seventh switch, and the eighth switch are p-type transistors.

11. The control circuit according to any one of claims 1 to 10, characterized in that: The first power supply line is coupled to the matching line.

12. The control circuit according to any one of claims 2 to 4, characterized in that: The second power supply line is coupled to the matching line.

13. The control circuit according to any one of claims 1 to 10, characterized in that: The first power supply line is used to receive the enabling voltage.

14. The control circuit according to any one of claims 2 to 4, characterized in that: The second power supply line is used to receive the enabling voltage.

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