A low-power high-capacity CAM circuit structure

Abstract

The application provides a low-power large-capacity CAM circuit structure, which changes the circuit structure of the existing CAM, divides the working process of the large-capacity CAM into several pipeline stages, performs partitioned sequential search addressing and latching, and finally generates a result address and outputs the result address after uniformly encoding all addressing results, so that the transient large power consumption of the CAM is distributed in multiple pipeline stages, and the transient high current requirement for the chip power supply network is reduced. The application has important application value in large-scale low-power SoC using CAM IP.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronic technology and memory, in particular to a low-power large-capacity CAM circuit structure. BACKGROUND

[0002] As a content addressable memory, CAM has high search efficiency but inevitably has large power consumption, especially for a CAM circuit with large capacity, the transient power consumption problem is particularly prominent, which may seriously affect the power integrity of the IP itself or the entire SoC. In the existing CAM design technology, in order to improve the access speed of the circuit, the data search, the matching result generation and the matching address coding three processes are generally placed in the same clock cycle, and the matching query operation is for the entire memory array. If the capacity of the memory is large, the transient power consumption will be quite large because all the storage units simultaneously discharge to the matching line.

[0003] CAM is a branch of RAM, which can perform search operation in addition to the read and write functions of RAM. One of the main functions of RAM is to read data, that is, the input address information can obtain the data stored in the RAM; and the main function of CAM is to search data, that is, the input search data can obtain the matching address and matching signal. The functions are compared as follows Figure 1 .

[0004] CAM mainly consists of the following five parts: CAM storage unit M, sensitive amplifier SA, search line SL drive, address decoder and priority encoder. The simplified structure block diagram is shown in Figure 2 , and the CAM array structure is shown in Figure 5 . Among them, the CAM storage unit is the core part of the CAM, each row of which constitutes a word, and each unit constituting the word is called a bit. It is mainly responsible for data storage and comparison, and the comparison result is represented by the voltage change of the matching line ML, which is then amplified by the SA, and finally the highest priority matching result is output by the priority encoder. In addition, the SL drive is used to load the search data onto the SL, and the address decoder is used for address decoding during read and write operations.

[0005] According to the different connection modes of the storage units, CAM is divided into NOR (NOR) type CAM and NAND (NAND) type CAM, and the typical transistor level circuit diagrams are shown in Figure 3 and Figure 4 . The NOR type CAM is mounted in parallel on a ML, which performs logical "or" operation, and the NAND type CAM is connected in series through multiple MLs, which performs logical "and" operation.

[0006] As shown in Figure 3As shown, the NOR type CAM cell uses four tubes M1-M4 to realize the comparison operation of the stored data (D, D#) and the search data (SL, SL#), wherein "#" represents "not". M1-M4 realize the "XOR" operation through dynamic logic circuit, and the details are described as follows. When SL is equal to or matches D, M1, M4 or M2, M3 are cut off, and ML keeps the high level in the pre-charge state; when SL does not match D, M1, M3 or M2, M4 are turned on, and ML is discharged to the ground. For a word, only when each storage bit matches the corresponding search bit, ML is high, that is, the whole word matches, which is called full match; otherwise, ML is pulled down, which is called word mismatch.

[0007] As shown in the figure, Figure 4 As shown, the NAND type CAM cell uses three tubes M1-M3 to realize the comparison operation of the stored data and the search data. When SL matches D, M2 or M3 is turned on, the B point level is pulled high by SL, and then M1 is turned on, and ML continues to propagate to the next stage; otherwise, the B point level is pulled low by SL, and M1 is turned off, and MLn+1 is suspended. Therefore, all the NAND type CAM cells in a word are connected in series through multiple MLs, realizing the "NAND" operation of ML.

[0008] Among them, the NOR type CAM does not have a transistor in series on the match line, and there is no voltage drop caused by the transistor, so it can support a longer match line, thereby obtaining a larger memory capacity and higher speed, but because the storage cells on the match line are in parallel structure, they will be discharged at the same time during the query operation, so the transient power consumption will be very large. Each storage cell of the NAND type CAM is connected in series with a transistor on the match line, which causes the match line to be too long, the capacity to be too large, and the series discharge speed to be slow, but the advantage of the series match line is that if a transistor on the match line is not turned on, the entire match line will not be discharged. Therefore, the NAND type CAM has the advantage of low transient power consumption. In summary, in order to support a large capacity CAM, the NOR type CAM architecture is generally used. SUMMARY

[0009] In view of the problem of large transient power consumption of the content addressable memory CAM in the prior art during high-speed search, the present application provides a low-power large-capacity CAM circuit structure, which realizes pipelining search by partitioning by address, so as to distribute the transient large power consumption of the CAM in multiple pipeline stages, thereby reducing the transient high current requirement of the chip power supply network.

[0010] The present application is realized by the following technical solutions:

[0011] The application discloses a low-power-consumption large-capacity CAM circuit structure which comprises a CAM array, a search driving module, a timing control module, an encoder and a plurality of latches; the CAM array comprises a plurality of storage blocks arranged in parallel; each storage block is provided with a match line ML; the input end of the search driving module is connected with the output end of a query data module; the output end of the search driving module is connected with the plurality of storage blocks through a plurality of search lines SL; the query data is transmitted to the plurality of storage blocks through the plurality of search lines SL for matching comparison; the matching results are transmitted to the latches through the match lines ML of the plurality of storage blocks; the timing control module is provided with timing switches Sel on the match lines ML of the plurality of storage blocks according to the address range corresponding to the storage blocks; the timing switches Sel are opened in sequence in each clock cycle; the match lines ML of the plurality of storage blocks are inquired; the matching results on the match lines ML are transmitted to the corresponding latches for backup in each clock cycle; the output end of the latches is connected with the encoder; when all the storage blocks are inquired, the results in the latches are encoded by the encoder in the next clock cycle to generate a corresponding matching address for output.

[0012] Preferably, the CAM array is divided into a plurality of block storage blocks according to address order; the timing control module inquires one block storage block in each clock cycle according to clock order; the selection signal is generated on the timing switch Sel through the block address to realize the switch control of the timing switch Sel by the timing control module.

[0013] Preferably, the match line ML in the storage block comprises a plurality of roots; the query data is input into the corresponding storage block through the search line SL for matching comparison and the matching results are transmitted through the plurality of match lines ML in the storage block.

[0014] Preferably, the search driving module transmits the data on the search line SL to the corresponding storage block in each clock cycle for matching comparison.

[0015] Preferably, when one or more bits in all bits in the query data are inconsistent with the data in the storage block, the match line ML in the storage block outputs low level; when all bits in the query data are matched with all the data in the storage block, the match line ML in the storage block outputs high level.

[0016] Preferably, the matching results transmitted by the match line ML are partitioned and latched; the matching results of the completed inquiry are latched in the corresponding latches in the clock cycle; when all the storage blocks in the CAM array structure are inquired, the latched matching results are uniformly encoded in the encoder in the subsequent clock cycle to generate a matching address.

[0017] Preferably, one memory block in the CAM array structure is queried in each clock cycle, and the matching result of the memory block is transmitted to the latch through the match line ML for latching.

[0018] Preferably, the timing control module realizes timing control of each memory block in the CAM array structure through the pipeline control circuit.

[0019] Compared with the prior art, the application has the following beneficial technical effects:

[0020] The application provides a low-power-consumption large-capacity CAM circuit structure, which changes the circuit structure of the existing CAM, divides the working process of the large-capacity CAM into several pipeline stages, performs partitioned sequential search addressing and latching, and finally generates a result address and outputs the result address after uniformly encoding all the addressing results, so that the transient large power consumption of the CAM is distributed in multiple pipeline stages, and the transient high current requirement of the chip power supply network is reduced.

[0021] Further, the CAM array is divided into several memory blocks according to the address sequence, and the transient large power consumption in the CAM query operation process is distributed in each memory block in each clock cycle, effectively reducing the transient power consumption of the CAM and achieving the effect of reducing the burden of the circuit power supply network.

[0022] Further, the query data on the search line SL is distributed to the corresponding memory block in each clock cycle, and the other memory blocks do not work, so that only one memory block in the CAM array works in each clock cycle, effectively reducing the transient current.

[0023] Further, when the query of the last memory block is completed, the encoding operation is performed on all the matching results in the next clock cycle, so as to generate the matching address result of the entire memory, ensure the whole matching address result, and effectively reduce the transient high current requirement of the chip power supply network.

[0024] Further, by adopting the pipeline grading working mode, the transient power consumption of the large-capacity CAM memory is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 It is a function comparison diagram of RAM and CAM in the prior art;

[0026] Figure 2 It is a simplified CAM structure block diagram in the prior art;

[0027] Figure 3A typical NOR-type CAM cell transistor-level circuit diagram in the prior art;

[0028] Figure 4 A typical NAND-type CAM cell transistor-level circuit diagram in the prior art;

[0029] Figure 5 A CAM array structure in the prior art;

[0030] Figure 6 A low-power high-capacity CAM circuit structure in the present application;

[0031] Figure 7 A CAM block array structure in the present application;

[0032] Figure 8 A CAM block pipelined operation timing diagram in the present application. DETAILED DESCRIPTION

[0033] In order to make the personnel in the technical field better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0034] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] The present application will be described in further detail below in conjunction with the drawings:

[0036] In an embodiment of the present application, a low-power high-capacity CAM circuit structure is provided, which is a circuit structure for pipelined search by address partitioning, so that the transient high power consumption of the CAM is distributed in multiple pipelined stages to reduce the transient high current requirement on the chip power supply network.

[0037] Specifically, the low-power high-capacity CAM circuit structure is as follows:Figure 6 As shown, it includes a CAM array, a search driver module, a timing control module, an encoder, and several latches; the CAM array includes several parallel storage blocks; each storage block has a matching line ML, such as... Figure 7 As shown; the input of the search driving module is connected to the output of the query data module, and the output of the search driving module is connected to several memory blocks through several search lines SL; the query data is transmitted to several memory blocks through several search lines SL for matching and comparison, and the matching result is transmitted to the latch through the matching lines ML of several memory blocks. The timing control module sets timing switches Sel on the matching lines ML of several memory blocks according to the address range corresponding to the memory blocks, and opens several timing switches Sel in sequence in each clock cycle to perform query operations on the matching lines ML of several memory blocks respectively. In each clock cycle, the matching result completed on the matching line ML is transmitted to the corresponding latch for latching and backup. The output of the latch is connected to the encoder. When all memory blocks have been queried, in the next clock cycle, the encoder encodes the results in the latch and generates the corresponding matching address for output.

[0038] Specifically, the CAM array is divided into several memory blocks according to address order. The timing control module performs a query operation on one of the memory blocks in each clock cycle according to the clock order. The selection signal is generated on the timing switch Sel through the block address, so as to realize the switching control of the timing switch Sel by the timing control module.

[0039] Specifically, the matching lines ML in the storage block include several lines. Query data is input to the corresponding storage block for matching and comparison through the search lines SL, and the matching results are transmitted through the several matching lines ML in the storage block.

[0040] Specifically, in each clock cycle, the search driver module transmits the data on the search line SL to a corresponding memory block for matching and comparison.

[0041] Specifically, when query data is transmitted to the matching lines ML of several storage blocks via several search lines SL for matching and comparison, if one or more bits in the query data do not match the data in the storage block, the matching line ML in the storage block outputs a low level; if all bits in the query data match all the data in the storage block, the matching line ML in the storage block outputs a high level.

[0042] Specifically, the match result partition latched by the match line ML is stored in the corresponding latch in the clock cycle, and the match result of the completed query is latched in the corresponding latch, and when all the storage blocks in the CAM array structure are queried, the latched match result is uniformly encoded in the encoder in the subsequent clock cycle to generate a match address.

[0043] Specifically, in each clock cycle, a storage block in the CAM array structure is queried, and the match result of the block storage block is transported to the latch through the match line ML for latching.

[0044] Specifically, the timing control module realizes timing control of each storage block in the CAM array structure through the flow control circuit, as shown in Figure 8 .

[0045] In the present application, the CAM matrix result is a conventional CAM with a data bit width of m and an address depth of n. When performing a match query, data is input from m search lines SL and compared with the data of all cells in the array. N match lines reflect the match result, that is, when one or more bits of the input data do not match the data stored in the row, the match line ML of the row outputs a low level, otherwise if all m bits match, a high level is output.

[0046] Embodiment

[0047] According to Figure 6 , when an m-bit query data is queried in the CAM, the query data is sent to the search driving module of the CAM circuit, and the query data is sent to the CAM array through m search lines SL_1... search line SL_m. At this time, the timing control module opens the timing switch Sel_1 to the timing switch Sel_x in each clock cycle according to the clock sequence, respectively queries a plurality of storage blocks of the CAM array, and sends the match result on the match line MLx_1-MLx_n corresponding to the completed match line in each clock cycle to the corresponding latch x for latching. When the query operation of all storage block arrays is completed, all the results of the latches 1-latches x are uniformly encoded by the encoder in the next clock cycle to generate a corresponding match address output, thereby completing the entire query operation.

[0048] In this process, since the storage array of the large-capacity CAM is divided into a plurality of storage blocks, the transient large power consumption in the CAM query operation process is distributed in each clock cycle of the storage block, effectively reducing the transient power consumption of the CAM, and achieving the effect of reducing the burden of the circuit power supply network.

[0049] In summary, the application provides a low-power large-capacity CAM circuit structure, which changes the circuit structure of the existing CAM, divides the working process of the large-capacity CAM into several pipeline stages, performs partitioned sequential search addressing and latching, and finally generates a result address and outputs the result address after uniformly encoding all the addressing results, so that the transient large power consumption of the CAM is distributed in multiple pipeline stages, and the transient high current requirement for the chip power supply network is reduced. The application has important application value in large-scale low-power SoC using CAM IP.

[0050] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present application, but not to limit it, although the present application has been described in detail with reference to the above examples, those skilled in the art should understand that: the specific embodiments of the present application can still be modified or replaced by the equivalent, without departing from the spirit and scope of the present application, any modification or equivalent replacement, which should be covered within the protection scope of the claims of the present application.

Claims

1. A low-power, high-capacity CAM circuit structure, characterized in that, The CAM array, the search driving module, the timing control module, the encoder and the plurality of latches are included; the CAM array includes a plurality of parallel storage blocks; each storage block is provided with a match line ML; the input end of the search driving module is connected to the output end of the query data module, and the output end of the search driving module is connected to the plurality of storage blocks through a plurality of search lines SL; the query data is transmitted to the plurality of storage blocks through the plurality of search lines SL for matching comparison, and the matching results are transmitted to the latches through the match lines ML of the plurality of storage blocks; the timing control module is provided with timing switches Sel on the match lines ML of the plurality of storage blocks according to the address range corresponding to the storage blocks, and the timing switches Sel are opened in turn in each clock cycle to perform the query operation on the match lines ML of the plurality of storage blocks, and the matching results on the match lines ML are transmitted to the corresponding latches for latching in each clock cycle; the output end of the latch is connected to the encoder, and when all the storage blocks are queried, the results in the latches are encoded by the encoder in the next clock cycle to generate the corresponding matching address for output. The CAM array is divided into a plurality of block storage blocks according to the address order, and the timing control module performs the query operation on one of the block storage blocks in each clock cycle to generate the selection signal on the timing switch Sel through the block address, thereby realizing the switch control of the timing switch Sel by the timing control module.

2. The low-power high-capacity CAM circuit structure according to claim 1, wherein, The match line ML in the storage block includes a plurality of roots, the query data is input into the corresponding storage block through the search line SL for matching comparison, and the matching results are transmitted through the plurality of match lines ML in the storage block.

3. The low-power high-capacity CAM circuit structure of claim 1, wherein, In each clock cycle, the search driving module transmits the data on the search line SL to the corresponding storage block for matching comparison.

4. The low-power high-capacity CAM circuit structure of claim 1, wherein, When one or more bits of the query data are inconsistent with the data in the storage block, the match line ML in the storage block outputs a low level; when all the bits of the query data are matched with all the data in the storage block, the match line ML in the storage block outputs a high level.

5. The low power high capacity CAM circuit structure of claim 1, wherein, The matching results transmitted by the match line ML are latched in zones, the matching results of the completed query are latched in the corresponding latches in the clock cycle, and the latched matching results are uniformly encoded in the encoder to generate the matching address in a subsequent clock cycle when all the storage blocks in the CAM array structure are queried.

6. The low-power high-capacity CAM circuit structure of claim 1, wherein, In each clock cycle, one of the storage blocks in the CAM array structure is queried, and the matching results of the block storage block are transmitted to the latches for latching.

7. The low-power high-capacity CAM circuit structure of claim 1, wherein, The timing control module realizes the timing control of each storage block in the CAM array structure through the flow control circuit.

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