Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region; forming a first gate structure on the first region, forming first source / drain doped regions in the substrate on both sides of the first gate structure, and forming a dielectric structure on the substrate located on the sidewall and top surfaces of the first gate structure; forming a first opening in the dielectric structure above the first region to expose the surface of the first source / drain doped region; forming an initial isolation layer on the sidewall and bottom surfaces of the first opening; performing a first ion implantation on the first source / drain doped region; after the first ion implantation, forming a mask layer on the substrate to expose the first region; performing a second ion implantation on the first source / drain doped region using the mask layer as a mask; after the second ion implantation, removing the mask layer; and after removing the mask layer, etching back the initial isolation layer until the surface of the first source / drain doped region is exposed, thereby forming a first isolation layer on the sidewalls of the first opening. The semiconductor structure formed by this method has improved performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Metal interconnects are essential structures in semiconductor devices, used to interconnect active areas, transistors, or metal lines on different layers, enabling signal transmission and control. Therefore, during semiconductor manufacturing, the formation of metal interconnects significantly impacts semiconductor device performance and manufacturing costs. To increase device density, the size of semiconductor devices in integrated circuits has been continuously reduced. To achieve electrical connections between individual semiconductor devices, multi-layer interconnect structures are typically required.

[0003] Typically, during the back-end interconnection process of semiconductor device manufacturing, the first metal layer (M1) needs to form an electrical connection with the underlying active device structures (including the source / drain regions and the gate structure). Therefore, before forming the first metal layer, it is usually necessary to pre-form a local interconnect structure (Local Interconnect) for the semiconductor device. This local interconnect structure includes a zeroth metal layer (M0) electrically connected to the underlying source / drain regions, and a zeroth gate metal layer (M0G) electrically connected to the gate structure.

[0004] However, the manufacturing process of the semiconductor structure with the local interconnect structure in the prior art is complicated, and the performance of the formed semiconductor structure needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of a semiconductor structure with a local interconnection structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region; forming a first gate structure on the first region, forming first source-drain doped regions in the substrate on both sides of the first gate structure, and forming a dielectric structure on the substrate, the dielectric structure being located on the sidewall surface and top surface of the first gate structure; forming a first opening in the dielectric structure on the first region, the first opening exposing the surface of the first source-drain doped region; forming an initial isolation layer on the sidewall surface and bottom surface of the first opening; performing a first ion implantation on the first source-drain doped region; after performing the first ion implantation, forming a mask layer on the substrate, the mask layer exposing the first region; performing a second ion implantation on the first source-drain doped region using the mask layer as a mask; after performing the second ion implantation, removing the mask layer; after removing the mask layer, etching back the initial isolation layer until the surface of the first source-drain doped region is exposed, thereby forming a first isolation layer on the sidewall of the first opening.

[0007] Optionally, the substrate also includes a second region; the formation method also includes: forming a second gate structure on the second region, forming a second source and drain doped region in the substrate on both sides of the second gate structure, and the dielectric structure is located on the sidewall surface and top surface of the second gate structure.

[0008] Optionally, before performing the first ion implantation, the method further includes: forming a second opening in the dielectric structure on the second region, wherein the second opening exposes the surface of the second source / drain doped region; forming an initial isolation layer on the sidewall surface and the bottom surface of the second opening; and the mask layer is also located in the second opening.

[0009] Optionally, the method further includes: performing the first ion implantation process on the second source / drain doping region.

[0010] Optionally, the first ions in the first ion implantation process include Group IV ions or inert gas ions.

[0011] Optionally, after removing the mask layer, the method further includes: etching back the initial isolation layer on the second region until the surface of the second source / drain doped region is exposed, and forming a second isolation layer on the sidewall of the second opening; after forming the first isolation layer and the second isolation layer, forming a first conductive structure in the first opening, the first conductive structure being electrically connected to the first source / drain doped region, and forming a second conductive structure in the second opening, the second conductive structure being electrically connected to the second source / drain doped region.

[0012] Optionally, the method for forming the mask layer includes: forming an initial mask layer on a substrate; and removing the initial mask layer on the first region to form the mask layer.

[0013] Optionally, the material of the first source / drain doping region includes silicon germanium; and the material of the second source / drain doping region includes carbon silicon.

[0014] Optionally, the second ions in the second ion implantation process include P-type ions, and the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0015] Optionally, the material of the mask layer includes photoresist.

[0016] Optionally, the process of removing the mask layer includes an ashing process, and the gas of the ashing process includes oxygen or a gas containing oxygen.

[0017] Optionally, the material of the initial isolation layer includes a dielectric material, and the dielectric material includes silicon nitride.

[0018] Optionally, the process of forming the initial isolation layer includes an atomic layer deposition process.

[0019] Optionally, after removing the mask layer and before forming the first isolation layer, the method further includes: performing surface treatment on the initial isolation layer.

[0020] Optionally, the process for surface treatment of the initial isolation layer includes a gas treatment process; the gas of the gas treatment process includes a mixed gas of nitrogen and hydrogen.

[0021] Optionally, the method for forming the first gate structure, the second gate structure, the first source-drain doped region, the second source-drain doped region and the dielectric structure includes: forming a first dummy gate structure on the first region of the substrate, and forming a second dummy gate structure on the second region of the substrate; forming a first source-drain doped region in the substrate on both sides of the first dummy gate structure, and forming a second source-drain doped region in the substrate on both sides of the second dummy gate structure; forming an initial dielectric structure on the substrate, wherein the initial dielectric structure is located on the sidewalls of the first dummy gate structure and the sidewalls of the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure, forming a first gate opening in the initial dielectric structure on the first region, and forming a second gate opening in the initial dielectric structure on the second region; forming a first gate structure in the first gate opening, and forming a second gate structure in the second gate opening; after forming the first gate structure and the second gate structure, forming the dielectric structure, wherein the dielectric structure is located on the sidewall surface and top surface of the first gate structure, and the dielectric structure is located on the sidewall surface and top surface of the second gate structure.

[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0023] In the method for forming a semiconductor structure in the technical solution of the present invention, after forming an initial isolation layer, a first ion implantation is first performed on the first source / drain doping region, and then a second ion implantation is performed on the first source / drain doping region. The first ion implantation process causes a certain number of first ions to be present on the surface of the initial isolation layer. The first ions are not easily affected by the subsequent formation of a mask layer, the second ion implantation process on the first source / drain doping region, and the removal of the mask layer. Therefore, after the mask layer is removed, the initial isolation layer is modified and the volume expansion is small. Therefore, when the conductive structure material is subsequently filled into the first opening, the filling effect is less affected, thereby ensuring better contact between the formed conductive structure and the first source / drain doping region.

[0024] Furthermore, after the second ion implantation, the initial isolation layer is surface treated. The surface treatment can reduce the volume change of the initial isolation layer during the formation of the mask layer, the second ion implantation process of the first source and drain doping region, and the removal of the mask layer. Thus, when the material of the conductive structure is subsequently filled in the first opening, the filling effect is less affected, thereby enabling the formed conductive structure to have better contact with the first source and drain doping region. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 3 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0026] Figures 4 to 11 It is a schematic cross-sectional structural diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] As described in the background art, the performance of the existing back-end metal interconnection process and the semiconductor structure formed therefrom still needs to be improved. This will now be analyzed and explained in conjunction with specific embodiments.

[0028] Figures 1 to 3 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment.

[0029] Please refer to Figure 1A substrate 100 is provided, wherein the substrate 100 includes a first region I and a second region II; a first gate structure 101 is formed on the first region I, and a second gate structure 102 is formed on the second region II; first source-drain doped regions 103 are formed in the substrate on both sides of the first gate structure 101; second source-drain doped regions 104 are formed in the substrate on both sides of the second gate structure 102; a dielectric structure 105 is formed on the substrate, wherein the dielectric structure 105 is located on the sidewalls of the first gate structure 101 and the sidewalls of the second gate structure 102; a first opening 106 is formed in the dielectric structure 105 on the first region I, wherein the first opening 106 exposes the surface of the first source-drain doped region 103; and a second opening 107 is formed in the dielectric structure 105 on the second region II, wherein the second opening 107 exposes the surface of the second source-drain doped region 104.

[0030] Please refer to Figure 2 A first isolation layer 108 is formed on the sidewall of the first opening 106 , and a second isolation layer 109 is formed on the sidewall of the second opening 107 .

[0031] Please refer to Figure 3 , forming a mask layer 110 on the substrate, wherein the mask layer 110 exposes the first region I; and performing ion implantation on the first source / drain doped region 103 using the mask layer 110 as a mask.

[0032] In the method for forming a semiconductor structure, the first region I is used to form a PMOS device, and the second region II is used to form an NMOS device. The first isolation layer 108 is used to increase electrical isolation between the conductive structure subsequently formed within the first opening 106 and the first gate structure 101. The material of the first isolation layer 108 includes a dielectric material, typically silicon nitride. After ion implantation, the ion concentration on the surface of the first source / drain doped region 103 is relatively high. When a conductive structure is subsequently formed within the first opening 106 and electrically connected to the first source / drain doped region 103, the contact resistance between the conductive structure and the first source / drain doped region 103 is reduced.

[0033] However, when forming the mask layer 110 that exposes the first region I, it is necessary to go through the steps of exposure, development, and etching. After ion implantation into the first source / drain doping region 103, the mask layer 110 needs to be removed. As a result, after the first isolation layer 108 undergoes the above-mentioned exposure, development, etching, removal, and ion implantation processes, the first isolation layer 108 is easily oxidized into a modified isolation layer 111, so that the volume of the modified isolation layer 111 increases, thereby reducing the size of the first opening 106 in the modified isolation layer 111. When metal material is subsequently deposited in the first opening 106 to form a conductive structure, it is difficult for the metal material to be filled into the surface of the first source / drain doping region 103, thereby reducing the contact area between the formed conductive structure and the first source / drain doping region 103, thereby affecting the conductive effect between the conductive structure and the first source / drain doping region 103.

[0034] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure: first, a first ion implantation is performed on the first source / drain doping region, and then a second ion implantation is performed on the first source / drain doping region. The first ion implantation process causes a certain number of first ions to be present on the surface of the initial isolation layer, and the first ions are not easily affected by the subsequent formation of a mask layer, the second ion implantation process on the first source / drain doping region, and the removal of the mask layer. Therefore, after the mask layer is removed, the initial isolation layer is modified and the volume expansion is small. Therefore, when the conductive structure material is subsequently filled in the first opening, the filling effect is less affected, thereby ensuring that the formed conductive structure has better contact with the first source / drain doping region.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 4 to 11 It is a schematic cross-sectional structural diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0037] Please refer to Figure 4 , providing a substrate 200, wherein the substrate 200 includes a first region I.

[0038] In this embodiment, the substrate 200 further includes a second region II.

[0039] The first region I is used for subsequently forming a PMOS device, and the second region II is used for subsequently forming an NMOS device.

[0040] In this embodiment, the substrate 200 is made of silicon.

[0041] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0042] Please refer to Figure 5 A first gate structure 201 is formed on the first region I, a first source-drain doped region 203 is formed in the substrate 200 on both sides of the first gate structure 201, and a dielectric structure 205 is formed on the substrate 200. The dielectric structure 205 is located on the sidewall surface and the top surface of the first gate structure 201.

[0043] In this embodiment, a second gate structure 202 is formed on the second region II, and second source-drain doped regions 204 are formed in the substrate 200 on both sides of the second gate structure 202 . The dielectric structure 205 is located on the sidewall surface and top surface of the second gate structure 202 .

[0044] In this embodiment, the material of the first source / drain doping region 203 includes silicon germanium; the material of the second source / drain doping region 204 includes carbon silicon.

[0045] The method for forming the first gate structure 201, the second gate structure 202, the first source-drain doped region 203, the second source-drain doped region 204 and the dielectric structure 205 includes: forming a first dummy gate structure (not shown) on the first region I of the substrate 200, and forming a second dummy gate structure (not shown) on the second region II of the substrate 200; forming first source-drain doped regions 203 in the substrate 200 on both sides of the first dummy gate structure, and forming second source-drain doped regions 204 in the substrate 200 on both sides of the second dummy gate structure; forming an initial dielectric structure (not shown) on the substrate 200, the initial dielectric structure being located on the sidewalls of the first dummy gate structure and the sidewalls of the second dummy gate structure. wall; removing the first dummy gate structure and the second dummy gate structure, forming a first gate opening (not shown) in the initial dielectric structure on the first region I, and forming a second gate opening (not shown) in the initial dielectric structure on the second region II; forming a first gate structure 201 in the first gate opening, and forming a second gate structure 202 in the second gate opening; after forming the first gate structure 201 and the second gate structure 202, forming the dielectric structure 205, the dielectric structure 205 is located on the sidewall surface and the top surface of the first gate structure 201, and the dielectric structure 205 is located on the sidewall surface and the top surface of the second gate structure 202.

[0046] The first gate structure 201 includes a first gate dielectric layer (not shown) and a first gate layer (not shown) located on the first gate dielectric layer. In this embodiment, the first gate structure 201 also includes a first work function layer (not shown), which is located between the first gate dielectric layer and the first gate layer.

[0047] The material of the first gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the first gate layer includes a metal, and the metal includes tungsten; the material of the first work function layer includes a P-type work function material, and the P-type work function material includes titanium nitride or tantalum nitride.

[0048] The second gate structure 202 includes a second gate dielectric layer (not shown) and a second gate layer (not shown) located on the second gate dielectric layer. In this embodiment, the second gate structure 202 also includes a second work function layer (not shown), which is located between the second gate dielectric layer and the second gate layer.

[0049] The material of the second gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the second gate layer includes a metal, and the metal includes tungsten; the material of the second work function layer includes an N-type work function material, and the N-type work function material includes titanium aluminum.

[0050] The dielectric structure 205 is made of a dielectric material, which may be a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the dielectric structure 205 is made of silicon oxide.

[0051] Please refer to Figure 6 A first opening 206 is formed in the dielectric structure 205 on the first region I, and the first opening 206 exposes the surface of the first source-drain doped region 203 .

[0052] In this embodiment, while forming the first opening 206 , a second opening 207 is also formed in the dielectric structure 205 on the second region II. The second opening 207 exposes the surface of the second source / drain doped region 204 .

[0053] The method for forming the first opening 206 and the second opening 207 includes: forming a patterned layer (not shown) on the dielectric structure 205, wherein the patterned layer exposes the dielectric structure 205 on the surface of the first source / drain doped region 203 and the dielectric structure 205 on the surface of the second source / drain doped region 204; using the patterned layer as a mask, etching the dielectric structure 205 until the surfaces of the first source / drain doped region 203 and the second source / drain doped region 204 are exposed, thereby forming the first opening 206 in the dielectric structure 205 on the first region I and the second opening 207 in the dielectric structure 205 on the second region II.

[0054] In this embodiment, the process of etching the dielectric structure 205 includes a dry etching process. The dry etching process can obtain the first opening 206 and the second opening 207 with good sidewall morphology and high dimensional accuracy.

[0055] Please refer to Figure 7 An initial isolation layer 208 is formed on the sidewall surfaces and the bottom surface of the first opening 206 .

[0056] In this embodiment, the initial isolation layer 208 is also formed on the sidewall surfaces and the bottom surface of the second opening 207 .

[0057] The initial isolation layer 208 is used to subsequently form a first isolation layer on the sidewall of the first opening 206 , and is used to form a second isolation layer on the sidewall of the second opening 207 .

[0058] The material of the initial isolation layer 208 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0059] In this embodiment, the material of the initial isolation layer 208 includes silicon nitride.

[0060] The process for forming the initial isolation layer 208 includes an atomic layer deposition process or a chemical vapor deposition process. In this embodiment, the process for forming the initial isolation layer 208 includes an atomic layer deposition process, which can form an initial isolation layer 208 with a dense structure and a relatively thin thickness.

[0061] Please continue to refer to Figure 7 After forming the initial isolation layer 208 , ion implantation is performed on the first source / drain doping region 203 using a first ion implantation process.

[0062] In this embodiment, the first ion implantation process further implants ions into the second source / drain doping region 204 .

[0063] The first ion implantation process is used to amorphize the material of the first source / drain doping region 203 and the material of the second source / drain doping region 204, so that it is easy to subsequently form metal silicide between the first conductive structure and the first source / drain doping region 203, and between the second conductive structure and the second source / drain doping region 204. At the same time, the quality of the formed metal silicide is good, thereby reducing the contact resistance between the first conductive structure and the first source / drain doping region 203, and reducing the contact resistance between the second conductive structure and the second source / drain doping region 204, thereby improving the conductive performance.

[0064] The first ions in the first ion implantation process include Group IV ions or inert gas ions.

[0065] In this embodiment, the first ions in the first ion implantation process include germanium ions.

[0066] First, a first ion implantation is performed on the first source / drain doping region 203. The implanted ions of the first ion implantation process include germanium ions, so that a certain number of germanium ions are present on the surface of the initial isolation layer 208. The germanium ions are not easily affected by the subsequent formation of the mask layer 209, the second ion implantation process on the first source / drain doping region 203, and the removal of the mask layer 209. Therefore, after the mask layer 209 is removed, the initial isolation layer 208 is modified and the degree of volume expansion is small.

[0067] Please refer to Figure 8 After the first ion implantation, a mask layer 209 is formed on the substrate 200 , wherein the mask layer 209 exposes the first region I.

[0068] In this embodiment, the mask layer 209 is also located in the second opening 207 .

[0069] The method for forming the mask layer 209 includes: forming an initial mask layer (not shown) on the substrate 200 ; and removing the initial mask layer on the first region I to form the mask layer 209 .

[0070] In this embodiment, the material of the mask layer 209 includes photoresist; and the process of forming the mask layer 209 includes an exposure process and a development process.

[0071] Please continue to refer to Figure 8 , performing a second ion implantation on the first source / drain doping region 203 using the mask layer 209 as a mask.

[0072] The second ion implantation process increases the ion concentration on the surface of the first source / drain doped region 203, thereby reducing the Schottky barrier between the subsequently formed first conductive structure and the first source / drain doped region 203, thereby reducing the contact resistance between the first conductive structure and the first source / drain doped region 203 and improving the performance of the semiconductor structure.

[0073] The second ions in the second ion implantation process include P-type ions, and the P-type ions include boron ions, boron fluoride ions, or indium ions.

[0074] The second ions in the second ion implantation process include P-type ions, which can increase the number of holes in the first source / drain doping region 203 , thereby increasing the hole mobility of the channel and improving the performance of the device on the first region I.

[0075] Please refer to Figure 9 After the second ion implantation, the mask layer 209 is removed.

[0076] In this embodiment, the process of removing the mask layer 209 includes an ashing process, and the gas used in the ashing process includes oxygen or a gas containing oxygen.

[0077] The first ion implantation process causes a certain number of first ions to be present on the surface of the initial isolation layer 208. The first ions are not easily affected by the subsequent formation of the mask layer 209, the second ion implantation process on the first source / drain doping region 203, and the removal of the mask layer 209. Therefore, after removing the mask layer 209, the initial isolation layer 208 is oxidized and the volume expansion is less. Therefore, when the conductive structure material is subsequently filled in the first opening 206, the filling effect is less affected, thereby ensuring better contact between the first conductive structure formed in the first opening 206 and the first source / drain doping region 203.

[0078] Please continue to refer to Figure 9 After removing the mask layer 209 , the method further includes: performing surface treatment on the initial isolation layer 208 on the first region I and the second region II.

[0079] The process of performing surface treatment on the initial isolation layer 208 includes a gas treatment process; the gas used in the gas treatment process includes a mixed gas of nitrogen and hydrogen.

[0080] The surface treatment can weaken the volume change of the initial isolation layer 208 on the first region I when it is oxidized during the formation of the mask layer 209, the second ion implantation process of the first source / drain doping region 203, and the removal of the mask layer 209, so that when the conductive structure material is subsequently filled in the first opening 206, the filling effect is less affected, thereby making the first conductive structure formed in the first opening better contact with the first source / drain doping region 203.

[0081] In other embodiments, the process of surface treating the initial isolation layer includes a wet treatment process.

[0082] In other embodiments, the initial isolation layer may not be surface treated.

[0083] Please refer to Figure 10 After surface treatment of the initial isolation layer 208 , the initial isolation layer is etched back until the surfaces of the first source / drain doped region 203 and the second source / drain doped region 204 are exposed, forming a first isolation layer 210 in the first opening 206 and a second isolation layer 211 in the second opening 207 .

[0084] The first isolation layer 210 is used to increase electrical isolation between the first conductive structure subsequently formed in the first opening 206 and the first gate structure 201 . The second isolation layer 211 is used to increase electrical isolation between the second conductive structure subsequently formed in the second opening 207 and the second gate structure 202 .

[0085] Please refer to Figure 11 After forming the first isolation layer 210 and the second isolation layer 211, a first conductive structure 212 is formed in the first opening 206, and the first conductive structure 212 is electrically connected to the first source-drain doped region 203. A second conductive structure 213 is formed in the second opening 207, and the second conductive structure 213 is electrically connected to the second source-drain doped region 204.

[0086] The method for forming the first conductive structure 212 and the second conductive structure 213 includes: forming a conductive material layer (not shown) in the first opening 206, in the second opening 207, and on the dielectric structure 205; planarizing the conductive material layer until the surface of the dielectric structure 205 is exposed, forming the first conductive structure 212 in the first opening 206, and forming the second conductive structure 213 in the second opening 207.

[0087] The process of forming the conductive material layer includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the process of forming the conductive material layer includes a chemical vapor deposition process.

[0088] Since the first source-drain doping region 203 is firstly subjected to the first ion implantation, the first ion implantation process causes a certain number of first ions to be present on the surface of the initial isolation layer 208. The first ions are not easily affected by the formation of the mask layer 209, the second ion implantation process on the first source-drain doping region 203, and the removal of the mask layer 209. Therefore, after the mask layer 209 is removed, the initial isolation layer 208 is modified and the volume expansion is smaller. Therefore, when the conductive structure material is filled in the first opening 206, the filling effect is less affected, thereby making the first conductive structure 212 formed in the first opening 206 better in contact with the first source-drain doping region 203.

[0089] After forming the first conductive structure 212 and the second conductive structure 213, the method further includes: annealing the first conductive structure 212 and the second conductive structure 213 to form a metal silicide (not shown) between the first conductive structure 212 and the first source-drain doping region 203 and between the second conductive structure 213 and the second source-drain doping region 204. The process of forming the metal silicide is a common technical means in the art and will not be repeated here.

[0090] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region; forming a first gate structure on the first region, forming first source-drain doped regions in the substrate on both sides of the first gate structure, and forming a dielectric structure on the substrate, wherein the dielectric structure is located on the sidewall surface and the top surface of the first gate structure; forming a first opening in the dielectric structure on the first region, wherein the first opening exposes a surface of the first source-drain doped region; forming an initial isolation layer on the sidewall surface and the bottom surface of the first opening; Performing a first ion implantation on the first source / drain doping region at the bottom of the initial isolation layer, wherein the first ions of the first ion implantation process include Group IV ions or inert gas ions; After performing the first ion implantation, forming a mask layer on the substrate, wherein the mask layer exposes the first region; Using the mask layer as a mask, performing a second ion implantation on the first source / drain doping region at the bottom of the initial isolation layer; After performing the second ion implantation, removing the mask layer; After removing the mask layer, etching back the initial isolation layer until the surface of the first source and drain doped region is exposed, forming a first isolation layer on the sidewall of the first opening; A first conductive structure is formed in the first opening, and the first conductive structure is electrically connected to the first source-drain doped region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The substrate also includes a second region; the formation method further includes: forming a second gate structure on the second region, forming second source and drain doped regions in the substrate on both sides of the second gate structure, and the dielectric structure is located on the sidewall surface and top surface of the second gate structure.

3. The method for forming a semiconductor structure according to claim 2, wherein: Before performing the first ion implantation, the method further includes: forming a second opening in the dielectric structure on the second region, wherein the second opening exposes the surface of the second source / drain doped region; forming an initial isolation layer on the sidewall surface and the bottom surface of the second opening; and the mask layer is also located in the second opening.

4. The method for forming a semiconductor structure according to claim 3, wherein: Also includes: The first ion implantation process further performs first ion implantation on the second source / drain doping region.

5. The method for forming a semiconductor structure according to claim 3, wherein: After removing the mask layer, the method further includes: etching back the initial isolation layer on the second region until the surface of the second source / drain doped region is exposed, and forming a second isolation layer on the sidewall of the second opening; after forming the first isolation layer and the second isolation layer, forming a first conductive structure in the first opening, the first conductive structure being electrically connected to the first source / drain doped region, and forming a second conductive structure in the second opening, the second conductive structure being electrically connected to the second source / drain doped region.

6. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the mask layer includes: forming an initial mask layer on a substrate; and removing the initial mask layer on the first region to form the mask layer.

7. The method for forming a semiconductor structure according to claim 2, wherein: The material of the first source / drain doping region includes silicon germanium; the material of the second source / drain doping region includes carbon silicon.

8. The method for forming a semiconductor structure according to claim 7, wherein: The second ions in the second ion implantation process include P-type ions, and the P-type ions include boron ions, boron fluoride ions, or indium ions.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the mask layer includes photoresist.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process of removing the mask layer includes an ashing process, and the gas of the ashing process includes oxygen.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the initial isolation layer includes a dielectric material, and the dielectric material includes silicon nitride.

12. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the initial isolation layer includes an atomic layer deposition process.

13. The method for forming a semiconductor structure according to claim 1, wherein: After removing the mask layer and before forming the first isolation layer, the method further includes: performing surface treatment on the initial isolation layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The process of performing surface treatment on the initial isolation layer includes a gas treatment process; the gas in the gas treatment process includes a mixed gas of nitrogen and hydrogen.

15. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the first gate structure, the second gate structure, the first source-drain doped region, the second source-drain doped region and the dielectric structure includes: forming a first dummy gate structure on a first region of the substrate, and forming a second dummy gate structure on a second region of the substrate; forming a first source-drain doped region in the substrate on both sides of the first dummy gate structure, and forming a second source-drain doped region in the substrate on both sides of the second dummy gate structure; forming an initial dielectric structure on the substrate, wherein the initial dielectric structure is located on the sidewalls of the first dummy gate structure and the sidewalls of the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure, forming a first gate opening in the initial dielectric structure on the first region, and forming a second gate opening in the initial dielectric structure on the second region; forming a first gate structure in the first gate opening, and forming a second gate structure in the second gate opening; after forming the first gate structure and the second gate structure, forming the dielectric structure, wherein the dielectric structure is located on the sidewall surface and top surface of the first gate structure, and the dielectric structure is located on the sidewall surface and top surface of the second gate structure.

Images