Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a method of fabricating the same. The semiconductor structure has a substrate, a dielectric layer, at least one main feature, at least one first conductive feature, at least one first gap sub-feature, a plurality of second conductive features, and a plurality of second gap sub-features. The dielectric layer is disposed on the substrate. The main feature is disposed in the dielectric layer and contacts the substrate. The first conductive feature is disposed in the dielectric layer and on the main feature. The first gap sub-feature is interposed between the dielectric layer and a portion of the first conductive feature. The second conductive features are disposed in the dielectric layer and on either side of the first conductive feature. The second gap sub-features are interposed between the dielectric layer and portions of the second conductive features.

Description

Technical Field

[0001] This application claims priority and benefits to U.S. formal application No. 16 / 936,194, filed July 22, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor structure. In particular, it relates to a semiconductor structure having a reduced pitch (half-pitch feature) and a method for fabricating the same. Background Technology

[0003] Photolithography is one of the fundamental processes used in manufacturing integrated circuit (IC) products. In photolithography systems, achieving high resolution is crucial for resolving fine, high-density, high-resolution patterns. Traditionally, this involves minimizing the feature size and pitch in IC products so that a desired pattern cannot be formed using a single patterned photoresist layer.

[0004] However, as integrated circuit technology continues to advance, component dimensions and spacing have shrunk to technology nodes, and existing lithography tools are unable to form a single patterned mask layer that contains all the features of the entire target pattern. Furthermore, these lithography tools are, for example, 193nm wavelength lithography tools. Without advanced lithography tools, such as an extreme ultraviolet (EUV) scanner, it is difficult to fabricate semiconductor structures with all the required spacing. Therefore, designers have adopted techniques involving performing multiple exposures to define a specific pattern within a single layer of material. One such technique is called multipatterning. Generally, multipatterning is an exposure method that involves splitting (i.e., dividing or separating) a dense, monolithic target circuit pattern into two separate, less dense patterns.

[0005] Multiple patterning techniques can effectively reduce the complexity of lithography processes and improve achievable resolution without the need for more advanced lithography tools.

[0006] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0007] An embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer, at least one main feature, at least one first conductive feature, at least one first gap sub, a plurality of second conductive features, and a plurality of second gap subs. The dielectric layer is disposed on the substrate. The main feature is disposed in the dielectric layer and contacts the substrate. The first conductive feature is disposed in the dielectric layer and on the main feature. The first gap sub is interposed between the dielectric layer and a portion of the first conductive feature. The second conductive features are disposed in the dielectric layer and on either side of the first conductive feature. The second gap subs are interposed between the dielectric layer and a portion of the second conductive features.

[0008] In some embodiments, the first conductive feature is centered on the main feature.

[0009] In some embodiments, the dielectric layer includes a plurality of first dielectric features disposed on the substrate and on either side of the main feature, wherein a first pitch is equal to a distance between centerlines of two adjacent first dielectric features, a second pitch is equal to a distance from one first conductive feature to a nearest second conductive feature plus a width of one first or second conductive feature, and the second pitch is half of the first pitch.

[0010] In some embodiments, the first dielectric features and the main feature have a same first width that is equal to half of the first pitch.

[0011] In some embodiments, the semiconductor structure further includes a first termination layer covering the first dielectric features and a portion of the main feature, wherein the first termination layer surrounds portions of the first conductive feature, and the first gap sub is disposed on the first termination layer and covers portions of the first conductive feature disposed on the first termination layer.

[0012] In some embodiments, the dielectric layer further includes a plurality of second dielectric features disposed on the first termination layer.

[0013] In some embodiments, the second dielectric features, the first gap sub, and the first conductive feature have coplanar upper surfaces that form a first planar upper surface.

[0014] In some embodiments, the semiconductor structure further includes a second termination layer disposed on the first planar upper surface, wherein portions of the second conductive features are surrounded by the second termination layer.

[0015] In some embodiments, the dielectric layer further includes a plurality of third dielectric features disposed on the second termination layer.

[0016] In some embodiments, the second spacer is on the second termination layer and covers sidewalls of the third dielectric features.

[0017] In some embodiments, the third dielectric features, the second spacer, and the second conductive features have coplanar upper surfaces that form a second planar upper surface.

[0018] In some embodiments, the first conductive features extend into the main features.

[0019] In some embodiments, the first spacer and the second spacer have the same thickness.

[0020] In some embodiments, the first conductive features and the second conductive features have the same width.

[0021] Another embodiment of the present disclosure provides a method of fabricating a semiconductor structure. The method includes forming a plurality of main features on a substrate; forming a first dielectric layer on the substrate, wherein the first dielectric layer includes a plurality of first dielectric features on either side of the main features; forming a first termination layer on the first dielectric features and the main features; forming a second dielectric layer on the first termination layer, wherein the second dielectric layer includes a plurality of second dielectric features on the first dielectric features; forming a plurality of first spacers on sidewalls of the second dielectric features; forming a plurality of first openings through portions of the first termination layer not covered by the second dielectric layer and the first spacers; forming a plurality of first conductive features in the first openings and contacting the main features; forming a second termination layer covering the second dielectric features, the first spacers, and the first conductive features; forming a plurality of third dielectric features on the first spacers and the first conductive features; forming a plurality of second spacers on sidewalls of the third dielectric features; removing the portions of the second termination layer not covered by the third dielectric features and the second spacers to form a plurality of second openings exposing portions of the second dielectric features; removing the portions of the second dielectric features not covered by the second termination layer and the second spacers to form a plurality of third openings; and forming a plurality of second conductive features in the second openings, in the third openings, and in a plurality of fourth openings between adjacent second openings.

[0022] In some embodiments, the forming of the main features includes forming a main layer on the substrate; forming a first photoresist pattern on the main layer; and removing portions of the main layer exposed by the first photoresist pattern to form the plurality of main features.

[0023] In some embodiments, the formation of the second dielectric feature includes: forming a second dielectric layer on the first termination layer; forming a second photoresist pattern on the second dielectric layer; and removing portions of the second dielectric layer exposed via the second photoresist pattern to form the plurality of second dielectric features; wherein the formation of the third dielectric feature includes: forming a third dielectric layer on the second termination layer; forming a third photoresist pattern on the third dielectric layer; and removing portions of the third dielectric layer exposed via the third photoresist pattern to form the plurality of third dielectric features; wherein the formation of the second photoresist pattern and the formation of the third photoresist pattern include the use of a first photomask, and the formation of the second photoresist pattern includes the use of a second photomask, wherein the second photomask is reverse-tone with the first photomask.

[0024] In some embodiments, the first opening extends into the main feature.

[0025] In some embodiments, forming the first spacer includes: depositing a first spacer layer on the second dielectric feature and on the portion of the first termination layer exposed via the second dielectric feature; and removing some horizontal portions of the first spacer layer; wherein the formation of the first opening is performed simultaneously with the removal of the horizontal portions of the first spacer layer.

[0026] In some embodiments, the formation of the second spacer includes: depositing a second spacer layer on the third dielectric feature and on portions of the second termination layer exposed via the third dielectric feature; and removing portions of the second spacer layer horizontally; wherein the formation of the second opening and the removal of the horizontal portions of the second spacer layer are performed simultaneously.

[0027] Fabricating multiple interconnect structures with compact multiple pitches is quite challenging, especially when the pitch is less than 75 nm. This disclosure provides a multiple patterning method that reduces the pitch of a semiconductor structure and fabricates a compactly pitched semiconductor structure. This disclosure uses a first mask used in first and third lithography processes, and a second mask used in a second lithography process, with the second mask having a reverse tone to the first mask. Furthermore, this disclosure uses multiple spacers as a hard mask and controls the thickness of the spacers to adjust the width of multiple conductive features. Therefore, given a pitch defined by two adjacent principal features (e.g., a gate structure), the final pitch defined by two adjacent conductive features (e.g., a metal line) can be halved, resulting in a reduced minimum feature size.

[0028] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0029] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0030] Figure 1 A cross-sectional schematic diagram illustrating an embodiment of the present disclosure of a semiconductor structure.

[0031] Figure 2 Examples of embodiments of this disclosure ( Figure 1 A top view schematic diagram of the semiconductor structure.

[0032] Figure 3 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure.

[0033] Figures 4 to 27 The illustrations show cross-sectional schematic diagrams of semiconductor structures at different manufacturing stages according to embodiments of the present disclosure.

[0034] The reference numerals in the attached figures are explained as follows:

[0035] 10: Base

[0036] 110: Main characteristics

[0037] 110A: Main Layer

[0038] 110B: Main Pattern

[0039] 112: Opening

[0040] 120: Photoresist characteristics

[0041] 120A: First photoresist layer

[0042] 120B: First photoresist pattern

[0043] 122: Opening

[0044] 130: First dielectric characteristic

[0045] 130A: First dielectric layer

[0046] 210: First Termination Layer

[0047] 220: Second photoresist feature

[0048] 220A: Second photoresist layer

[0049] 220B: Second photoresist pattern

[0050] 222: Opening

[0051] 230: Second dielectric characteristic

[0052] 230A: Second dielectric layer

[0053] 230B: Second dielectric layer

[0054] 232: Opening

[0055] 240': Horizontal section

[0056] 240: First gap

[0057] 240A: Interstitial Sublayer

[0058] 242: Opening

[0059] 250: First conductivity characteristic

[0060] 252: Opening

[0061] 310: Second Termination Layer

[0062] 320: Third photoresist feature

[0063] 320A: Third photoresist layer

[0064] 320B: Third photoresist pattern

[0065] 322: Opening

[0066] 330: Third dielectric characteristic

[0067] 330A: Third dielectric layer

[0068] 330B: Third dielectric layer

[0069] 332: Opening

[0070] 340: Second gap

[0071] 340A: Interstitial Sublayer

[0072] 340': Horizontal section

[0073] 341: Vertical section

[0074] 350: Second conductivity characteristic

[0075] 400: Dielectric layer

[0076] 1000: Semiconductor Structure

[0077] 2000: Preparation Method

[0078] B: First width

[0079] HV1: First radiation

[0080] hv2: Second radiation

[0081] hv3: Third radiation

[0082] MA1: First Photomask

[0083] MA2: Second Photomask

[0084] O1: First opaque part

[0085] O2: Second opaque part

[0086] P1: First spacing

[0087] P2: Second spacing

[0088] S1: Upper surface

[0089] S101: Steps

[0090] S103: Steps

[0091] S105: Steps

[0092] S107: Steps

[0093] S109: Steps

[0094] S111: Steps

[0095] S113: Steps

[0096] S115: Steps

[0097] S117: Steps

[0098] S119: Steps

[0099] S121: Steps

[0100] S123: Steps

[0101] S125: Steps

[0102] S127: Steps

[0103] S129: Steps

[0104] S131: Steps

[0105] S133: Steps

[0106] S135: Steps

[0107] S137: Steps

[0108] S139: Steps

[0109] S2: Upper surface

[0110] S3: Upper surface

[0111] T1: First Transparent Section

[0112] T2: Second Transparent Section

[0113] X: Thickness

[0114] Y: Width Detailed Implementation

[0115] The following description of this disclosure, accompanied by drawings incorporated in and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0116] It should be understood that while the terms "first," "second," "third," etc., may be used in this text to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the "first element," "component," "region," "layer," or "section" discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this text.

[0117] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, the terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0118] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0119] Figure 1 A cross-sectional schematic diagram illustrating a semiconductor structure 1000 according to an embodiment of this disclosure is provided. Please refer to... Figure 1 The semiconductor structure 1000 mainly includes a substrate 10, one or more main features 110, one or more first dielectric features 130, one or more second dielectric features 230, one or more third dielectric features 330, one or more first conductive features 250, one or more second conductive features 350, one or more first spacers 240, one or more second spacers 340, a first termination layer 210, and a second termination layer 310. The main features 110 and the first dielectric features 130 are alternately disposed on the substrate 10. A first spacing P1 is present such that the first spacing P1 is equal to a distance from one of the main features 110 to an adjacent main feature 110. The first conductive features 250 are located on the main features 110, wherein a portion of each first conductive feature 250 is surrounded by one of the first spacers 240. Each first conductive feature 250 is located at the center of the top of one of the main features 110, and a portion of the first conductive feature 250 not surrounded by the first spacer 240 extends into the main feature 110. A first terminating layer 210 covers the main feature 110 and a portion of the first dielectric feature 130 exposed via the first conductive feature 250.

[0120] The second dielectric feature 230, the first spacer 240, and the second conductive feature 350 are located on the first termination layer 210, wherein the first spacer 240 covers portions of the sidewalls of each of the first conductive features 250. Each second conductive feature 350 is partially surrounded by the second spacer 340 and is located at the center of the top of each first dielectric feature 130. A second spacing P2 is present such that the second spacing P2 is equal to the distance from one of the first conductive features 250 to the nearest second conductive feature 350 plus the width of the first conductive feature 250. The second spacing P2 is half of the first spacing P1. Each first dielectric feature 130 and each main feature 110 have the same first width, which is equal to half of the first spacing P1. The first spacer 340 and the second spacer 340 have the same thickness X. Each first conductive feature 250 and each second conductive feature 350 have the same width Y. The second dielectric feature 230, the first spacer 240, and the first conductive feature 250 each have coplanar upper surfaces forming a second flat upper surface S2. A second terminating layer 310 is on the upper surface S2, wherein the second terminating layer 310 surrounds a portion of each second conductive feature 350. A portion of the first terminating layer 210 is inserted between the first dielectric feature 130 and the second dielectric feature 230, and the remaining portion of the first terminating layer 210 is inserted between the first spacer 240 and the main feature 110. The third dielectric feature 330 is located on the second terminating layer 310. The second spacer 340 is located on the second terminating layer 310 and covers the sidewalls of the third dielectric feature 330. The third dielectric feature 330, the second spacer 340, and the second conductive feature 350 each have coplanar upper surfaces forming a third flat upper surface S3.

[0121] A portion of the second termination layer 310 is inserted between the second spacer 340 and the second dielectric feature 230, another portion of the second termination layer 310 is inserted between the third dielectric feature 330 and the first spacer 240, and the remaining portion of the second termination layer 310 is inserted between the third dielectric feature 330 and the first conductive feature 250. Each second conductive feature 350 is generally located between any two first conductive features 250. The first dielectric feature 130, the second dielectric feature 230, and the third dielectric feature 330 are combined into a dielectric layer 400, while the main feature 110, the first conductive feature 250, the first spacer 240, and the first and second termination layers 210 and 310 are embedded in the dielectric layer 400, and the second conductive feature 350 and the second spacer 340 are disposed in the dielectric layer 400.

[0122] Figure 2 Examples of embodiments of this disclosure are shown in Figure 1 The diagram shows a top view of the semiconductor structure 1000. Please refer to the provided text. Figure 1 and Figure 2 The first spacing P1 is equal to 4X + 2Y, which is the distance between two adjacent main features 110 plus the width of the main feature 110. In some embodiments, the first spacing P1 is equal to the distance between the center lines of the two adjacent main features 110. The second spacing P2 is equal to 2X + Y, which is the distance between two adjacent conductive features 250 and 350 plus the width of conductive feature 250 or 350. The second spacing P2 is half of the first spacing P1.

[0123] Figure 3 A schematic flowchart illustrating a method 2000 for fabricating a semiconductor structure 1000 according to an embodiment of the present disclosure is shown. In particular, the fabrication method 2000 includes a multi-patterning process. Figures 4 to 27 A cross-sectional schematic diagram illustrating each manufacturing stage of the preparation method 2000 according to an embodiment of the present disclosure.

[0124] Please refer to Figure 4 According to Figure 3 In step S101, a master layer 110A is formed on a substrate 10. In some embodiments, the substrate 10 may be a dielectric material, such as silicon oxide and / or a low-k material. In these embodiments, the substrate 10 may be formed using a spin coating process or a chemical vapor deposition (CVD) process. In other embodiments, the substrate 10 may primarily comprise silicon, a dielectric material, a conductive material, or a combination thereof. In these embodiments, the substrate 10 may comprise various doped regions, dielectric features, or multilevel interconnects. In some embodiments, the master layer 110A may comprise polysilicon or other suitable materials. In some embodiments, the master layer 110A may be formed using a CVD process.

[0125] Please refer to Figure 4 and Figure 5 According to Figure 3 In step S103, a first lithography process is performed. First, please refer to... Figure 4A first photoresist layer 120A is deposited to completely cover the main layer 110A. In some embodiments, the first photoresist layer 120A may be a positive tone photoresist, characterized by removing each exposed area using a developing solution. In some embodiments, the first photoresist layer 120A includes a chemical amplifier (CA) photoresist. The chemical amplifier photoresist includes a photoacid generator (PAG), which can be decomposed to form acids during the lithography exposure process. More acids can be generated through a catalytic reaction.

[0126] Please refer to Figure 5 Using a first photomask MA1 and a lithography system, a first photoresist layer 120A is exposed to a first radiation hv1. In some embodiments, the first radiation hv1 may include deep ultraviolet (DUV) light, but is not limited thereto. The first photomask MA1 includes a plurality of first transparent portions T1 and a plurality of first opaque portions O1. In one embodiment, the first transparent portions T1 and the first opaque portions O1 are of equal horizontal length. Exposure causes a photochemical reaction that alters the chemical properties of some portions of the first photoresist layer 120A. For example, it exposes portions of the first photoresist layer 120A corresponding to the first transparent portions T1, making it more responsive to the development process. In some embodiments, after the first photoresist layer 120A is exposed, a post-exposure baking (PEB) may be performed.

[0127] Next, please refer to Figure 6 A suitable developer is used to rinse the exposed portions of the first photoresist layer 120A. The exposed portions of the first photoresist layer 120A react with the developer and can be easily removed. After the development process is completed, a first photoresist pattern 120B is formed on the main layer 110A. The first photoresist pattern 120B includes a plurality of first photoresist features 120 and a plurality of openings 122, the openings 122 being configured together with the first photoresist features 120. In some embodiments, the first photoresist features 120B and the openings 122 respectively correspond to, for example... Figure 5 The first opaque portion O1 and the first transparent portion T1 of the first photomask MA1 are shown. A portion of the main layer 110A is covered by the first photoresist feature 120.

[0128] Please refer to Figure 7 ,in accordance withFigure 3 Step S105 involves performing a first etching process. In some embodiments, a first photoresist pattern 120B is used as an etching mask to etch the main layer 110A. Specifically, uncovered portions of the main layer 110A are removed using a first etchant (not shown) to expose portions of the substrate 10. Therefore, a main pattern 110B includes a plurality of main features 110 and a plurality of openings 112, and the main pattern 110B is formed on the substrate 10. In some embodiments, the main features 110 can be used as a gate structure in a transistor. In some embodiments, the main features 110 are connected to the first photoresist feature 120, and the openings 112 communicate with the openings 122.

[0129] Please refer to Figure 8 ,in accordance with Figure 3 Step S107 involves performing a first photoresist removal process. After the first etching process is completed, for example, the first photoresist pattern 120B can be removed by an ashing process or a wet etching process. In some embodiments, a first spacing P1 exists in the main pattern 110B, wherein the first spacing P1 is the distance between the center lines of two adjacent main features 110. In some embodiments, the first spacing P1 is defined according to a predetermined integrated circuit layout in the first photomask MA1.

[0130] Please refer to Figure 9 ,in accordance with Figure 3 In step S109, a first dielectric layer 130A is deposited in the opening 112. Specifically, the first dielectric layer 130A is deposited uniformly and conformally to fill the opening 112 and cover the main feature 110. In some embodiments, the first dielectric layer 130A may comprise the same material as the substrate 10. In some embodiments, the first dielectric layer 130A may be formed using a spin coating process or a CVD process.

[0131] Please refer to Figure 9 and Figure 10 After the opening 112 is filled with the first dielectric layer 130A, a chemical mechanical polishing (CMP) process is performed to remove some portions of the first dielectric layer 130A on the upper surface of the main feature 110. At this time, a plurality of first dielectric features 130 are formed. In some embodiments, because the first dielectric features 130 and the main feature 110 respectively correspond to... Figure 5The first transparent portion T1 and the first opaque portion O1 in the first photomask MA1 shown have the same first width B as the first dielectric feature 130 and the main feature 110, wherein the first transparent portion T1 and the first opaque portion O1 are equal in horizontal length. In some embodiments, the first width B is equal to half of the first spacing P1, that is, P1 = 2B. In some embodiments, the first dielectric feature 130 and the main feature 110 have coplanar upper surfaces, which form a flat upper surface S1.

[0132] Please refer to Figure 11 ,in accordance with Figure 3 In step S111, a first termination layer 210 and a second dielectric layer 230A are formed on the upper surface S1. In some embodiments, the first termination layer 210 may comprise silicon nitride (SiN), silicon oxynitride (SiON), or other suitable materials selected for compatibility, but this disclosure is not limited thereto. In some embodiments, the first termination layer 210 may be formed using a plasma-enhanced chemical vapor deposition (PECVD) process. In some embodiments, the first termination layer 210 may be used as an etch stop layer to improve planarization. In some embodiments, the first termination layer 210 is thin, preferably less than [a certain thickness]. Thickness, but this disclosure is not limited thereto. Please refer to [other sources]. Figure 11 The process involves depositing a second dielectric layer 230A to completely cover the first termination layer 210. In some embodiments, the second dielectric layer 230A may contain the same material as the substrate 10. In some embodiments, the second dielectric layer 230A may be formed using a spin coating process or a CVD process. Prior to the next process, a chemical mechanical polishing process is performed to planarize the second dielectric layer 230A.

[0133] Please refer to Figure 12 and Figure 13 ,in accordance with Figure 3 Step S113 involves performing a second lithography process. First, please refer to... Figure 12First, a second photoresist layer 220A is deposited to completely cover the second dielectric layer 230A. Then, using a second photomask MA2 and a lithography system, the second photoresist layer 220A is exposed to a second radiation hv2. In some embodiments, the second radiation hv2 may include deep ultraviolet light, but is not limited thereto. The second photomask MA2 includes a plurality of second transparent portions T2 and a plurality of second opaque portions O2. In some embodiments, the second transparent portions T2 and the second opaque portions O2 are of equal horizontal length. In some embodiments, the second photomask MA2 is a reverse-tone photomask of the first photomask MA1, meaning that the configuration of the second transparent portions T2 and the second opaque portions O2 is opposite to the configuration of the first transparent portions T1 and the first opaque portions O1. Exposure causes a photochemical reaction that alters the chemical properties of some portions of the second photoresist layer 220A. In some embodiments, a post-exposure baking may be performed after the second photoresist layer 220A is exposed.

[0134] Next, please refer to Figure 13 A suitable developer is used to rinse the exposed second photoresist layer 220A. The exposed portion of the second photoresist layer 220A reacts with the developer and can be easily removed. After the development process is complete, a second photoresist pattern 220B is formed on the second dielectric layer 230A. The second photoresist pattern 220B includes a plurality of second photoresist features 220 and a plurality of openings 222, the openings 222 being disposed together with the second photoresist features 220. In some embodiments, the second photoresist features 220 and the openings 222 respectively correspond as follows: Figure 12 The second opaque portion O2 and the second transparent portion T2 of the second photomask MA2 are shown. Some portions of the second dielectric layer 230A are not covered by the second photoresist feature 220.

[0135] Please refer to Figure 14 ,in accordance with Figure 3 Step S115 involves performing a second etching process. In some embodiments, a second photoresist pattern 220B is used as an etching mask to etch the second dielectric layer 230A. Specifically, a second etchant (not shown) is used to remove the uncovered portions of the second dielectric layer 230A to expose portions of the first termination layer 210. In some embodiments, the second etchant may be the same as the first etchant. Thus, a second dielectric layer 230B includes a plurality of second dielectric features 230 and a plurality of openings 232, and is formed on the first termination layer 210. In some embodiments, the second dielectric features 230 are connected to the second photoresist features 220, and the openings 232 communicate with the openings 222.

[0136] Please refer to Figure 15 ,in accordance with Figure 3Step S117 involves performing a second photoresist removal process. After the second etching process is completed, the second photoresist pattern 220B can be removed. In some embodiments, since the second photomask MA2 is a reverse photomask of the first photomask MA1, a first spacing P1 exists in the second dielectric layer 230B, wherein the first spacing P1 is equal to the distance from one of the second dielectric features 230 to an adjacent second dielectric feature 230 plus the width of the second dielectric feature 230.

[0137] Please refer to Figure 16 ,in accordance with Figure 3 Step S119 involves performing a first spacer deposition. In some embodiments, a spacer layer 240A may be conformally formed on the second dielectric layer 230B and the first termination layer 210. In some embodiments, the spacer layer 240A may be formed using a CVD process or an atomic layer deposition (ALD) process. In some embodiments, the spacer layer 240A has a thickness X, which is precisely controlled by the deposition conditions. In some embodiments, the spacer layer 240A may comprise various dielectric materials having a high dielectric constant (hogh-k). For example, the dielectric material may include silicon oxide (SiO), silicon nitride, silicon oxynitride, metal oxides such as hafnium oxide (HfO), or other suitable materials selected for compatibility, but this disclosure is not limited thereto.

[0138] Please refer to Figure 16 and Figure 17 ,in accordance with Figure 3 Step S121 involves performing a first spacer etching process. In some embodiments, the first spacer etching is an isotropic etching process that removes some horizontal portions 240' of the spacer layer 240A and through the first termination layer 210. Therefore, a plurality of spacers 240, including a thickness X, remain on the first termination layer 210 to cover the sidewalls of the second dielectric feature 230. Furthermore, during the first spacer etching process, the main feature 110 is partially etched, thereby forming a plurality of openings 242. In some embodiments, some portions of the first termination layer 210 are interposed between the first dielectric feature 130 and the second dielectric feature 230, and other portions of the first termination layer 210 are interposed between the spacers 240 and the main feature 110.

[0139] Please refer to Figure 18 ,in accordance with Figure 3Step S123 involves performing a first conductive material deposition. In some embodiments, the first conductive material deposition is an electroplating process. Specifically, a conductive material is deposited to fill the opening 242 and completely cover the second dielectric feature 230 and the spacer 240. In some embodiments, the first conductive material may include a low-resistance material, such as copper or a copper-based alloy. Alternatively, the first conductive material may include various materials, such as tungsten (W), aluminum (Al), gold (Au), silver (Ag), and the like. After the opening 242 is completely filled with the first conductive material, a CMP process is performed to remove a portion of the first conductive material, thereby exposing the second dielectric feature 230 and the spacer 240. At this time, a plurality of first conductive features 250 filling the opening 242 are formed. In some embodiments, each first conductive feature 250 is surrounded by the spacer 240. Furthermore, the spacer 240 can be used as a hard mask to control the width of the opening 242 according to the thickness X of the spacer 240. Therefore, the thickness X of the spacer 240 can be used to adjust the width Y of the first conductive feature 250. For example, please refer to... Figure 18 The width Y of the first conductive feature 250 is equal to (B - 2X), meaning B = (2X + Y). In some embodiments, the second dielectric feature 230, the spacer 240, and the first conductive feature 250 have coplanar upper surfaces, forming a flat upper surface S2. In some embodiments, before the deposition of the first conductive material, a diffusion barrier layer (not shown) may be conformally formed in the openings 232 and 242. The diffusion barrier layer arranged along the openings 232 and 242 serves as an insulation to prevent metal diffusion and as an adhesive layer between the first conductive material and the dielectric material. The material of the diffusion barrier layer includes TaN, Ta, Ti, TiN, TiSiN, WN, or combinations thereof. After the diffusion barrier layer is formed, a seed layer (not shown) is formed on the diffusion barrier layer. In some embodiments, when the first conductive material is a copper-containing material, the seed layer may be a copper seed layer, which is formed by a physical vapor deposition (PVD) process.

[0140] Please refer to Figure 19 ,in accordance with Figure 3 In step S125, a second termination layer 310 and a third dielectric layer 330A are formed on the upper surface S2. In some embodiments, the second termination layer 310 may contain the same material as the first termination layer 210. In some embodiments, the second termination layer 310 may be used as an etch stop layer to improve planarization. In some embodiments, the second termination layer 310 is thin, preferably less than [a certain thickness]. Thickness, but this disclosure is not limited thereto. Please refer to [other sources]. Figure 19A third dielectric layer 330A is deposited to completely cover the second termination layer 310. In some embodiments, the third dielectric layer 330A may contain the same material as the substrate 10. A CMP process is performed to planarize the third dielectric layer 330A prior to the next process.

[0141] Please refer to Figure 20 and Figure 21 ,in accordance with Figure 3 Step S127 involves performing a third lithography process. First, please refer to... Figure 20 A third photoresist layer 320A is deposited to completely cover the third dielectric layer 330A. Next, using a first photomask MA1 and a lithography system, the third photoresist layer 320A is exposed to a third radiation hv3. In some embodiments, the third radiation hv3 may include deep ultraviolet light, but is not limited thereto. The exposure induces a photochemical reaction that alters the chemical properties of some portions of the third photoresist layer 320A. In some embodiments, a PEB process can be performed after the third photoresist layer 320A is exposed.

[0142] Next, please refer to Figure 21 A suitable developer is used to rinse the exposed portions of the third photoresist layer 320A. The exposed portions of the third photoresist layer 320A react with the developer and can be easily removed. After the development process is completed, a third photoresist pattern 320B is formed on the third dielectric layer 330A. The third photoresist pattern 320B includes a plurality of third photoresist features 320 and a plurality of openings 322, the openings 322 being configured together with the third photoresist features 320. In some embodiments, the third photoresist features 320 and the openings 322 correspond respectively as follows: Figure 20 The first opaque portion O1 and the first transparent portion T1 of the first photomask MA1 are shown. Some portions of the third dielectric layer 330A are not covered by the third photoresist feature 320.

[0143] Please refer to Figure 22 ,in accordance with Figure 3 Step S129 in the process involves performing a third etching process. In some embodiments, such as Figure 21As shown, a third photoresist pattern 320B is used as an etching mask to etch the third dielectric layer 330A. Specifically, a third etchant (not shown) is used to remove the uncovered portions of the third dielectric layer 330A to expose portions of the second termination layer 310. In some embodiments, the third etchant may be the same as the first or second etchant. Therefore, a third dielectric layer 330B includes a plurality of third dielectric features 330 and a plurality of openings 332, and is formed on the second termination layer 310. In some embodiments, the third dielectric features 330 are connected to the third photoresist feature 320, and the openings 332 communicate with the openings 322.

[0144] Please refer to Figure 23 ,in accordance with Figure 3 Step S131 involves performing a third photoresist removal process. After the third etching process is completed, the third photoresist pattern 320B can be removed. In some embodiments, because the third lithography process uses a first photomask MA1, a first spacing P1 exists in the third dielectric layer 330B, wherein the first spacing P1 is equal to the width from one of the third dielectric features 330 to an adjacent third dielectric feature 330 plus the width of the third dielectric feature 330.

[0145] Please refer to Figure 24 ,in accordance with Figure 3 Step S133 involves performing a second spacer deposition. In some embodiments, a spacer layer 340A may be conformally formed on the third dielectric layer 330B and on portions of the second termination layer 310 that are exposed by the third dielectric layer 330B. The spacer layer 340A may include a plurality of horizontal portions 340' and a plurality of vertical portions 341, the horizontal portions 340' covering each upper surface of the third dielectric feature 330 and portions of the second termination layer 310 not occupied by the third dielectric feature 330, and the vertical portions 341 covering each sidewall of the third dielectric feature 330. In some embodiments, the spacer layer 340A may be formed using a CVD process or an ALD process. In some embodiments, the spacer layer 340A has the same thickness X as the spacer layer 240A. In some embodiments, the spacer layer 340A may contain the same material as the spacer layer 240A.

[0146] Please refer to Figure 25 ,in accordance with Figure 3 Step S135 involves performing a second spacer etching process. In some embodiments, such as Figure 24As shown, the second spacer etching process is an isotropic etching process, which removes the horizontal portion 340' of the spacer layer 340A and some portions of the second termination layer 310 that are not protected by the vertical portion 341 of the spacer layer 340A. Therefore, a plurality of spacers 340, including a thickness X, remain on the second termination layer 310 to cover the sidewalls of the third dielectric feature 330. During the second spacer etching, a plurality of openings 312 are formed through the second termination layer 310, thereby exposing the second dielectric feature 230. In some embodiments, some portions of the second termination layer 310 are interposed between the spacers 340 and the second dielectric feature 230, a portion of the second termination layer 310 is interposed between the third dielectric feature 330 and the spacers 240, and the remaining portion of the second termination layer 310 is interposed between the third dielectric feature 330 and the first conductive feature 250.

[0147] Please refer to Figure 26 ,in accordance with Figure 3 Step S137 involves performing a fourth etching process. In some embodiments, this involves etching the second dielectric feature 230 via, for example... Figure 25 The opening 312 shown exposes a portion of the first termination layer 210. In some embodiments, the fourth etching process and the second spacer etching process may be performed in a single step or in separate steps. In some embodiments, when the fourth etching process and the second spacer etching process are performed in separate steps, the etchant in the second spacer etching process may be properly selected so that the spacer layer 340A and the second termination layer 310 have an etching rate greater than that of the second dielectric feature 230. After the fourth etching process is completed, a plurality of openings 252 are formed to expose the first termination layer 210.

[0148] Please refer to Figure 27 ,in accordance with Figure 3In step S139, a second conductive material deposition is performed. In some embodiments, the second conductive material deposition is an electroplating process. Specifically, a second conductive material is deposited to fill the openings 252 and 312 and completely cover the third dielectric feature 330 and the spacer 340. In some embodiments, the second conductive material may be the same as the first conductive material. After the openings 252 and 312 are completely filled with the second conductive material, a CMP process is performed to remove a portion of the second conductive material, thereby exposing the third dielectric feature 330 and the spacer 340. At this time, a plurality of second conductive features 350 deposited in the openings 252 and 312 are formed, and a semiconductor structure 1000 is generally formed. In some embodiments, the third dielectric feature 330, the 340, and the second conductive feature 350 have coplanar upper surfaces, which form a flat upper surface S3. In some embodiments, a diffusion barrier layer (not shown) may be conformally formed in the openings 252 and 312 before the second conductive material deposition. The diffusion barrier layer arranged along the openings 252 and 312 serves as an insulation to prevent metal diffusion and as an adhesive layer between the second conductive material and the dielectric material. After the diffusion barrier layer is formed, a seed layer (not shown) is formed on the diffusion barrier layer. In some embodiments, when the second conductive material is a copper-containing material, the seed layer may be a copper seed layer, which is formed by a physical vapor deposition process.

[0149] Please refer to the following: Figure 27 In some embodiments, a portion of each second conductive feature 350 is surrounded by the spacer 340. Furthermore, the spacer 340 can be used as a rigid shield to control the width of the openings 252 and 312 based on the thickness X of the spacer 340. Therefore, the thickness of the spacer 340 can be used to adjust the width of the second conductive feature 350. For example, as... Figure 27 As shown, the width of the second conductive feature 305 is equal to (B - 2X), which is also equal to the width Y of the first conductive feature 250. In some embodiments, a second spacing P2 is equal to the distance from one of the first conductive features 250 to the nearest conductive feature 350 plus the width of one of the first or second conductive features 250 or 350. In some embodiments, the second spacing P2 is equal to the width Y of the first conductive feature 250 or the second conductive feature 350 plus twice the width X of the spacer 240 or the spacer 340, that is, P2 = (2X + Y). Because P1 = 2B and B = (2X + Y), P1 = 2P2. Therefore, the second spacing P2 is half of the first spacing P1.

[0150] Fabricating multiple interconnect structures with compact multiple pitches is challenging, especially when the pitch is less than 75 nm. This disclosure provides a multi-patterning method that reduces the pitch of a semiconductor structure and fabricates a compactly pitched semiconductor structure. This disclosure uses a first mask used in first and third lithography processes, and a second mask used in a second lithography process, with the second mask having a reverse tone to the first mask. Furthermore, this disclosure uses multiple spacers as a hard mask and controls the thickness of the spacers to adjust the width of multiple conductive features. Therefore, given a pitch defined by two adjacent principal features (e.g., a gate structure), the final pitch defined by two adjacent conductive features (e.g., a metal line) can be halved, resulting in a reduced minimum feature size.

[0151] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0152] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor structure, comprising: a substrate; a dielectric layer disposed on the substrate; at least one main feature disposed in the dielectric layer and contacting the substrate; at least one first conductive feature disposed in the dielectric layer and on the main feature; at least one first gap sub disposed between the dielectric layer and a portion of the first conductive feature; a plurality of second conductive features disposed in the dielectric layer and on either side of the first conductive feature; and a plurality of second gap subs disposed between the dielectric layer and a portion of the second conductive features; wherein the dielectric layer comprises a plurality of first dielectric features disposed on the substrate and on either side of the main feature, wherein a first pitch is equal to a distance between centerlines of two adjacent first dielectric features, a second pitch is equal to a distance from one of the first conductive features to a nearest second conductive feature plus a width of one of the first or second conductive features, and the second pitch is half of the first pitch.

2. The semiconductor structure of claim 1, wherein the first conductive feature is centered on the main feature.

3. The semiconductor structure of claim 1, wherein the first dielectric features and the main feature have a same first width that is equal to half of the first pitch.

4. The semiconductor structure of claim 1, further comprising a first termination layer covering the first dielectric features and a portion of the main feature, wherein the first termination layer surrounds portions of the first conductive features, and the first gap subs are disposed on the first termination layer and cover portions of the first conductive features disposed on the first termination layer.

5. The semiconductor structure of claim 4, wherein the dielectric layer further comprises a plurality of second dielectric features disposed on the first termination layer.

6. The semiconductor structure of claim 5, wherein the second dielectric features, the first gap subs, and the first conductive features have coplanar upper surfaces that form a first planar upper surface.

7. The semiconductor structure of claim 6, further comprising a second termination layer disposed on the first planar upper surface, wherein portions of the second conductive features are surrounded by the second termination layer.

8. The semiconductor structure of claim 7, wherein the dielectric layer further comprises a plurality of third dielectric features disposed on the second termination layer.

9. The semiconductor structure of claim 8, wherein the second gap subs are disposed on the second termination layer and cover sidewalls of the third dielectric features.

10. The semiconductor structure of claim 9, wherein the third dielectric features, the second gap subs, and the second conductive features have coplanar upper surfaces that form a second planar upper surface.

11. The semiconductor structure of claim 1, wherein the first conductive feature extends into the main feature.

12. The semiconductor structure of claim 1, wherein the first gap subs and the second gap subs have a same thickness.

13. The semiconductor structure of claim 1, wherein the first conductive features and the second conductive features have a same width.

14. A method of fabricating a semiconductor structure, comprising: forming a plurality of main features on a substrate; forming a first dielectric layer on the substrate, wherein the first dielectric layer comprises a plurality of first dielectric features positioned on either side of the main features; forming a first termination layer on the first dielectric features and the main features; forming a second dielectric layer on the first termination layer, wherein the second dielectric layer comprises a plurality of second dielectric features positioned on the first dielectric features; forming a plurality of first spacer features on sidewalls of the second dielectric features; forming a plurality of first openings through portions of the first termination layer not covered by the second dielectric layer and the first spacer features; forming a plurality of first conductive features in the first openings and contacting the main features; forming a second termination layer covering the second dielectric features, the first spacer features, and the first conductive features; forming a plurality of third dielectric features on the first spacer features and the first conductive features; forming a plurality of second spacer features on sidewalls of the third dielectric features; removing the portions of the second termination layer not covered by the third dielectric features and the second spacer features to form a plurality of second openings exposing portions of the second dielectric features; removing the portions of the second dielectric features not covered by the second termination layer and the second spacer features to form a plurality of third openings; and forming a plurality of second conductive features in the second openings, in the third openings, and in a plurality of fourth openings between adjacent second openings.

15. The method of claim 14, wherein the forming of the main features comprises: forming a main layer on the substrate; forming a first photoresist pattern on the main layer; and removing portions of the main layer exposed by the first photoresist pattern to form the plurality of main features.

16. The method of claim 14, wherein the forming of the second dielectric features comprises: forming a second dielectric layer on the first termination layer; forming a second photoresist pattern on the second dielectric layer; and removing portions of the second dielectric layer exposed by the second photoresist pattern to form the plurality of second dielectric features; wherein the forming of the third dielectric features comprises: forming a third dielectric layer on the second termination layer; forming a third photoresist pattern on the third dielectric layer; and removing portions of the third dielectric layer exposed by the third photoresist pattern to form the plurality of third dielectric features; wherein the forming of the second photoresist pattern and the forming of the third photoresist pattern comprise using a first mask, and the forming of the second photoresist pattern comprises using a second mask, and the second mask is a reverse of the first mask.

17. The method of claim 15, wherein the first openings extend into the main features.

18. The method of claim 14, wherein the forming of the first spacer features comprises: depositing a first spacer layer on the second dielectric features and on the portions of the first termination layer exposed by the second dielectric features; and removing the portions of the first termination layer not covered by the second dielectric features and the first spacer layer to form the plurality of first openings. ​ ​ removing some horizontal portions of the first gap sub-layer; wherein the forming of the first opening is concurrently with the removing of the horizontal portions of the first gap sub-layer.

19. The preparation method of claim 14, wherein the forming of the second gap sub includes: depositing a second gap sub-layer on the third dielectric features, and on some portions of the second termination layer exposed via the third dielectric features; and removing some horizontal portions of the second gap sub-layer; wherein the forming of the second opening is concurrently with the removing of the horizontal portions of the second gap sub-layer.

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