Semiconductor device structure, method of forming the same, and semiconductor device

Abstract

The present invention provides a semiconductor device structure, a forming method thereof, and a semiconductor device. The forming method of the semiconductor device structure includes: providing a substrate; forming a first fin-type structure on the substrate, in which K layers of channel materials and K+1 layers of channel isolation materials are alternately stacked; forming source and drain regions of a 1_1 field-effect transistor on the first layer of channel material at the bottom of the first fin-type structure; forming a 1_1 metal interconnect in contact with the source or drain region of the 1_1 field-effect transistor; forming source and drain regions of a 1_2 field-effect transistor on the second layer of channel material at the bottom of the fin-type structure; forming a 1_2 metal interconnect in contact with the source or drain region of the 1_2 field-effect transistor. Repeat the above process as required, and prepare a gate dielectric layer and a metal layer, and finally form a first stacked semiconductor device structure. By inserting the preparation of metal interconnects during the structure preparation process of the stacked semiconductor device structure, the present invention achieves the purpose of increasing the circuit integration degree.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and manufacturing, and particularly to a semiconductor device structure, a method for forming the same, and a semiconductor device. Background Art

[0002] Field effect transistors have the characteristics of high input resistance, low noise, low power consumption, large dynamic range, and easy integration, and are widely used in integrated circuits. With the development of technology, the device fabrication process has approached its physical limit, and the method of simply reducing the device size to increase the circuit integration degree has gradually failed. On the other hand, the traditional metal interconnection method is carried out on the top of the device. Although the process is mature, it occupies a lot of space and also limits the further improvement of the device density.

[0003] To improve the integration degree of integrated circuits, there is an urgent need for a semiconductor device structure, a method for forming the same, and a semiconductor device to improve the above problems. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor device structure, a method for forming the same, and a semiconductor device to achieve the purpose of increasing the circuit integration degree.

[0005] In a first aspect, the present invention provides a method for forming a semiconductor device structure, the method comprising:

[0006] Providing a substrate; forming a first fin structure in which K layers of field effect transistor channel materials and K + 1 layers of field effect transistor channel isolation materials are alternately stacked on the substrate; forming source and drain regions of a 1_1 field effect transistor on the first layer of field effect transistor channel material at the bottom of the first fin structure; forming a 1_1 metal interconnection in contact with the source or drain region of the 1_1 field effect transistor; forming source and drain regions of a 1_2 field effect transistor on the second layer of field effect transistor channel material at the bottom of the first fin structure; forming a 1_2 metal interconnection in contact with the source or drain region of the 1_2 field effect transistor; repeating the above process as required until a total of K source and drain regions of field effect transistors are formed, and metal interconnections in contact with the source or drain regions of the K field effect transistors are formed; removing all field effect transistor channel isolation materials, and simultaneously preparing gate dielectric layers of the K field effect transistors, and preparing gate metals layer by layer from bottom to top according to the requirements of the threshold voltage of each field effect transistor, finally forming a first stacked semiconductor device structure, where K is a positive integer.

[0007] The beneficial effects are as follows: Multiple spatially adjacent stacked semiconductor device structures are formed on the substrate according to the above method. In the present invention, the preparation of metal interconnect lines is interspersed during the preparation process of the stacked semiconductor device structures, realizing local hierarchical interconnection inside a single stacked semiconductor device structure and local hierarchical interconnection between spatially adjacent stacked semiconductor device structures, so as to achieve the purpose of increasing circuit integration density.

[0008] Optionally, before forming the source region and drain region of the 1_1 field-effect transistor on the first-layer field-effect transistor channel material at the bottom of the fin structure, it further includes: forming a metal buried line structure on the substrate; before forming the 1_1 metal interconnect line in contact with the source region or drain region of the 1_1 field-effect transistor, it further includes: forming a 1_3 metal interconnect line around the 1_1 field-effect transistor, wherein the 1_1 metal interconnect line is in contact with the metal buried line through the 1_3 metal interconnect line. The beneficial effects are as follows: When there is a metal buried line structure in the device structure, the 1_1 metal interconnect line is in contact with the metal buried line through the 1_3 metal interconnect line, thereby realizing the contact between the 1_1 field-effect transistor and the metal buried line, and making the top interconnection space of the device more abundant.

[0009] Optionally, before forming the 1_2 metal interconnect line in contact with the source region or drain region of the 1_2 field-effect transistor, it includes: forming a 1_4 metal interconnect line around the 1_2 field-effect transistor, wherein the 1_2 metal interconnect line is in contact with the metal buried line through the 1_4 metal interconnect line. The beneficial effects are as follows: The contact between the 1_2 field-effect transistor and the metal buried line is realized by using the space inside the semiconductor device structure, and the top interconnection space of the device is made more abundant.

[0010] Optionally, a second fin-type structure in which an L-th field-effect transistor channel material and an L+1-th field-effect transistor channel isolation material are alternately stacked is formed on the substrate; a source region and a drain region of a 2_1 field-effect transistor are formed on the first layer of field-effect transistor channel material at the bottom of the second fin-type structure; a 2_1 metal interconnect line in contact with the source region or the drain region of the 2_1 field-effect transistor is formed; a source region and a drain region of a 2_2 field-effect transistor are formed on the second layer of field-effect transistor channel material at the bottom of the second fin-type structure; a 2_2 metal interconnect line in contact with the source region or the drain region of the 2_2 field-effect transistor is formed; the above process is repeated as required until a source region or a drain region of L field-effect transistors is formed in total, and a metal interconnect line in contact with the source region or the drain region of the L field-effect transistors is formed; all the field-effect transistor channel isolation materials are removed, and at the same time, a gate dielectric layer of L field-effect transistors is prepared, and gate metal is prepared layer by layer from bottom to top according to the requirements of the threshold voltage of each field-effect transistor, finally forming a second stacked semiconductor device structure, where L is a positive integer, and there is a gap between the second stacked semiconductor device structure and the first stacked semiconductor device structure; at least one of the K metal interconnect lines in contact with the source region or the drain region in the first stacked semiconductor device structure is connected to the source region or the drain region of the field-effect transistor in the second stacked semiconductor device structure; or, at least one of the L metal interconnect lines in contact with the source region or the drain region in the second stacked semiconductor device structure is connected to the source region or the drain region of the field-effect transistor in the first stacked semiconductor device structure. The beneficial effect is that: the present invention can also form metal interconnect lines between the stacked semiconductor device structures with gaps, and realize the contact between the semiconductor device structures through the metal interconnect lines, so as to improve the integration degree of the integrated circuit composed of the stacked semiconductor device structures with gaps.

[0011] Optionally, before forming the 1_2 metal interconnect line in contact with the source region or the drain region of the 1_2 field-effect transistor, it includes: forming a 1_5 metal interconnect line around the 1_2 field-effect transistor, where the 1_1 metal interconnect line is in contact with the 1_2 metal interconnect line through the 1_5 metal interconnect line. The beneficial effect is that: through the contact between the 1_1 metal interconnect line and the 1_2 metal interconnect line through the 1_5 metal interconnect line, the internal interconnection of the first stacked semiconductor device structure is realized.

[0012] In a second aspect, the present invention provides a semiconductor device structure, including: a substrate; a first stacked semiconductor device structure formed on the substrate, the first stacked semiconductor device structure including K field-effect transistors formed by stacking, and metal interconnect lines in contact with the source region or the drain region of each field-effect transistor, where K is a positive integer.

[0013] The beneficial effects are as follows: By inserting the preparation of metal interconnecting lines during the preparation process of the stacked semiconductor device structure, the flexibility of circuit interconnection methods is increased, and the circuit integration degree is improved.

[0014] Optionally, the first stacked semiconductor device structure further includes a metal buried line structure located on the substrate, and the metal buried line is in contact with the metal interconnecting line. The beneficial effects are as follows: When there is a metal buried line structure in the semiconductor device structure, the metal buried line is in contact with the metal interconnecting line, making the top interconnecting space of the device more abundant and improving the circuit integration degree.

[0015] Optionally, the semiconductor device structure further includes: a second stacked semiconductor device structure formed on the substrate, the second stacked semiconductor device structure includes L field effect transistors formed by stacking, and metal interconnecting lines in contact with the source region or drain region of each field effect transistor, where L is a positive integer; at least one of the K metal interconnecting lines in contact with the source region or drain region in the first stacked semiconductor device structure is connected to the source region or drain region of the field effect transistor in the second stacked semiconductor device structure; or, at least one of the L metal interconnecting lines in contact with the source region or drain region in the second stacked semiconductor device structure is connected to the source region or drain region of the field effect transistor in the first stacked semiconductor device structure. The beneficial effects are as follows: By inserting the preparation of metal interconnecting lines during the preparation process of the stacked semiconductor device structure, local hierarchical interconnection between spatially adjacent stacked semiconductor device structures is achieved, so as to increase the circuit integration degree.

[0016] Optionally, different field effect transistors among the K field effect transistors are locally interconnected through the metal interconnecting lines. The beneficial effects are as follows: By locally interconnecting different field effect transistors among the K field effect transistors through the metal interconnecting lines, metal interconnection inside the stacked semiconductor device structure is realized, and the circuit integration degree is increased.

[0017] In a third aspect, the present invention provides a semiconductor device, including the semiconductor device structure according to any one of the possible ones in any of the above aspects.

[0018] The beneficial effects are that a hierarchical metal interconnection structure is added inside the semiconductor device, which not only increases the flexibility of interconnection methods, but also improves the circuit integration degree. Description of the Drawings

[0019] Figure 1 It is a schematic flowchart of a method for forming a semiconductor device structure provided by an embodiment of the present application;

[0020] Figure 2A and Figure 2BCross-sectional schematic diagram of the formation process of a semiconductor device structure provided by an embodiment of the present application;

[0021] Figure 3 Cross-sectional schematic diagram of a semiconductor device structure provided by an embodiment of the present application;

[0022] Figure 4 Another cross-sectional schematic diagram of a semiconductor device structure provided by an embodiment of the present application;

[0023] Figure 5 Another cross-sectional schematic diagram of a semiconductor device structure provided by an embodiment of the present application;

[0024] Figure 6 Still another cross-sectional schematic diagram of a semiconductor device structure provided by an embodiment of the present application. Detailed implementation manners

[0025] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art to which the present invention pertains. The words such as "including" used herein mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0026] A stacked semiconductor device structure is a three-dimensional electronic device formed by at least two field effect transistors (FETs) stacked vertically together. A stacked semiconductor device structure has at least two field effect transistors longitudinally at the same time. For planar field effect transistors, currently, only metal interconnections are made through their tops, but this design has limitations for stacked semiconductor device structures and also wastes the space between stacked semiconductor device structures. To further improve the circuit integration density, the present invention realizes local hierarchical interconnection inside a single stacked semiconductor device structure and local hierarchical interconnection between spatially adjacent stacked semiconductor device structures by interspersing the preparation of metal interconnection lines during the structure preparation process of the stacked semiconductor device structure, so as to achieve the purpose of increasing the circuit integration density.

[0027] To achieve the above-mentioned invention objective, the present invention provides a schematic flowchart of a method for forming a semiconductor device structure, as Figure 1 shown, and the specific steps will be combined with Figure 2A andFigure 2B is described as follows:

[0028] S101, provide a substrate 1, as shown in (a) of Figure 2A .

[0029] S102, form a first fin structure on the substrate 1 with K layers of field-effect transistor channel materials and K + 1 layers of field-effect transistor channel isolation materials stacked alternately, as shown in (b) of Figure 2A , where 2 represents the Kth layer of field-effect transistor channel material and 3 represents the (K + 1)th layer of field-effect transistor channel isolation material.

[0030] S103, form a source region and a drain region of a 1_1 field-effect transistor on the first layer of field-effect transistor channel material at the bottom of the first fin structure, as shown in (c) of Figure 2A , where 4 represents the source region or the drain region of the 1_1 field-effect transistor.

[0031] S104, form a 1_1 metal interconnect 5 that contacts the source region or the drain region of the 1_1 field-effect transistor, as shown in (c) of Figure 2A .

[0032] In this step, the 1_1 metal interconnect 5 can either contact the source region of the 1_1 field-effect transistor or the drain region of the 1_1 field-effect transistor.

[0033] S105, form a source region and a drain region of a 1_2 field-effect transistor on the second layer of field-effect transistor channel material at the bottom of the first fin structure, as shown in (d) of Figure 2A , where 6 represents the source region or the drain region of the 1_2 field-effect transistor.

[0034] S106, form a 1_2 metal interconnect 7 that contacts the source region or the drain region of the 1_2 field-effect transistor, as shown in (d) of Figure 2A .

[0035] In this step, the 1_2 metal interconnect 7 can either contact the source region of the 1_2 field-effect transistor or the drain region of the 1_2 field-effect transistor.

[0036] S107, repeat the above process as needed until a total of K source regions and drain regions of field-effect transistors are formed, and metal interconnects that contact the source regions or the drain regions of the K field-effect transistors are formed.

[0037] As shown in (d) of Figure 2A , 8 represents the source region or the drain region of the Kth field-effect transistor, and 9 represents the 1_K metal interconnect that contacts the source region or the drain region of the Kth field-effect transistor.

[0038] S108, remove all the trench isolation materials, as shown in (e) of Figure 2A , and simultaneously fabricate the gate dielectrics 10 of K field effect transistors, as shown in (f) of Figure 2A . Layer by layer from bottom to top, fabricate the gate metals according to the requirements of the threshold voltages of each field effect transistor, and finally form the first stacked semiconductor device structure, where K is a positive integer.

[0039] In this step, layer by layer from bottom to top, fabricate the gate metals according to the requirements of the threshold voltages of each field effect transistor, as shown in (g) and (h) of Figure 2B . 11 represents the gate metal of the 1_1 field effect transistor, and 12 represents the gate metal of the 1_2 field effect transistor. If the materials of the gate metals required for adjacent field effect transistors are the same, the gate metals on the adjacent field effect transistors can be fabricated simultaneously.

[0040] By the above method, when K is equal to 2, the fabricated semiconductor device structure is as shown in Figure 3 . And the following embodiments will be explained with K equal to 2. The semiconductor device structure includes: a substrate 1, a source or drain region 4 of the 1_1 field effect transistor, a 1_1 metal interconnect 5, a source or drain region 6 of the 1_2 field effect transistor, and a 1_2 metal interconnect 7. And the 1_1 metal interconnect 5 and the 1_2 metal interconnect 6 can be either on the same side or on different sides of the semiconductor device structure. It is worth mentioning that the embodiments of the present application do not limit the number of field effect transistors formed on the substrate. As long as the semiconductor device structure and its forming method mentioned in the embodiments of the present application are adopted, they all fall within the scope protected by the present application.

[0041] In a possible implementation manner, before forming the source and drain regions of the 1_1 field effect transistor on the first layer of the field effect transistor channel material at the bottom of the fin structure, it further includes: forming a metal buried line structure on the substrate; before forming the 1_1 metal interconnect in contact with the source or drain region of the 1_1 field effect transistor, it further includes: forming a 1_3 metal interconnect around the 1_1 field effect transistor; wherein, the 1_1 metal interconnect is in contact with the metal buried line through the 1_3 metal interconnect.

[0042] Based on the description of the above embodiments, the embodiments of the present application provide a semiconductor device structure as shown in Figure 4 . In addition to including all the structures mentioned in Figure 3 , it further includes a metal buried line 13 and a 1_3 metal interconnect 14. The metal buried line 13 is in contact with the 1_1 metal interconnect 5 through the 1_3 metal interconnect 14.

[0043] In still another possible implementation, before forming the 1_2 metal interconnect line that contacts the source region or the drain region of the 1_2 field effect transistor, it includes: forming a 1_4 metal interconnect line around the 1_2 field effect transistor, wherein the 1_2 metal interconnect line contacts the metal buried line through the 1_4 metal interconnect line.

[0044] In the embodiments of the present application, all field effect transistors can be interconnected with the metal buried line through the metal interconnect line contacting the metal buried line, and the circuit composed of the semiconductor device structure has an increased integration degree by contacting the metal interconnect line with the metal buried line.

[0045] In yet another possible implementation, before forming the 1_2 metal interconnect line that contacts the source region or the drain region of the 1_2 field effect transistor, it includes: forming a 1_5 metal interconnect line around the 1_2 field effect transistor, wherein the 1_1 metal interconnect line contacts the 1_2 metal interconnect line through the 1_5 metal interconnect line. By the 1_1 metal interconnect line contacting the 1_2 metal interconnect line through the 1_5 metal interconnect line, metal interconnection inside the first stacked semiconductor device structure is realized, and different field effect transistors can be interconnected through the metal interconnect line contacts.

[0046] Based on the description of the above embodiments, the embodiments of the present application form a semiconductor device structure as shown in Figure 5 and in addition to including all the structures mentioned in Figure 3 , it further includes: a 1_5 metal interconnect line 15, and the 1_2 metal interconnect line 7 contacts the 1_1 metal interconnect line 5 through the 1_5 metal interconnect line 15.

[0047] In a possible implementation, a second fin-type structure in which L layers of field-effect transistor channel materials and L + 1 layers of field-effect transistor channel isolation materials are alternately stacked is formed on the substrate; source and drain regions of a 2_1 field-effect transistor are formed on the first layer of field-effect transistor channel material at the bottom of the second fin-type structure; a 2_1 metal interconnect line in contact with the source or drain region of the 2_1 field-effect transistor is formed; source and drain regions of a 2_2 field-effect transistor are formed on the second layer of field-effect transistor channel material at the bottom of the second fin-type structure; a 2_2 metal interconnect line in contact with the source or drain region of the 2_2 field-effect transistor is formed; the above process is repeatedly executed as required until a total of L source or drain regions of field-effect transistors are stacked and metal interconnect lines in contact with the source or drain regions of the L field-effect transistors are formed; all field-effect transistor channel isolation materials are removed, and at the same time, gate dielectric layers of L field-effect transistors are prepared, and gate metals are prepared layer by layer from bottom to top according to the requirements of the threshold voltage of each field-effect transistor, finally forming a second stacked semiconductor device structure, where L is a positive integer, and there is a gap between the second stacked semiconductor device structure and the first stacked semiconductor device structure; at least one of the K metal interconnect lines in contact with the source or drain region in the first stacked semiconductor device structure is connected to the source or drain region of the field-effect transistor in the second stacked semiconductor device structure; or, at least one of the L metal interconnect lines in contact with the source or drain region in the second stacked semiconductor device structure is connected to the source or drain region of the field-effect transistor in the first stacked semiconductor device structure.

[0048] In addition, the field-effect transistors or metal interconnect lines in the same layer of the first stacked semiconductor device structure and the second stacked semiconductor device structure can be prepared simultaneously, and the contact between the first stacked semiconductor device structure and the second stacked semiconductor device structure is realized through the metal interconnect lines.

[0049] In this embodiment, when K and L are equal to 2, the formed semiconductor device structure is as Figure 6 shown, in addition to including Figure 3The substrate 1, the source or drain region 4 of the 1_1 field effect transistor, the metal interconnection line 5, the source or drain region 6 of the 1_2 field effect transistor, and the 1_2 metal interconnection line 7 mentioned above further include: the source or drain region 16 of the 2_1 field effect transistor, the 2_1 metal interconnection line 17, the source or drain region 18 of the 2_2 field effect transistor, and the 2_2 metal interconnection line 19. The 2_1 metal interconnection line 17 can either contact the source region of the 2_1 field effect transistor or contact the drain region of the 2_1 field effect transistor; the 2_2 metal interconnection line 19 can either contact the source region of the 2_2 field effect transistor or contact the drain region of the 2_2 field effect transistor, and the 2_1 metal interconnection line 17 and the 2_2 metal interconnection line 19 can either be on the same side of the semiconductor device structure or on different sides of the semiconductor device structure.

[0050] Through the contact between the metal interconnection lines on the first stacked semiconductor device structure and the second stacked semiconductor device structure, the metal interconnection between the semiconductors with gaps is realized, improving the circuit integration degree.

[0051] It is worth mentioning that there can be multiple stacked semiconductor device structures in the semiconductor device structure, and the number of N-type or P-type field effect transistors in the same stacked semiconductor device structure can be inconsistent. The above structures are applicable to the method for establishing interconnections between semiconductor device structures through metal interconnection lines proposed by the present invention. The structures shown in the figures are only examples and do not limit the protection scope of the present invention.

[0052] The embodiment of the present invention further provides a semiconductor device structure and a semiconductor device obtained by the above-mentioned forming method. The semiconductor device structure and the semiconductor device can include the structures mentioned in any of the above embodiments. By realizing the local hierarchical interconnection inside a single stacked semiconductor device structure and the local hierarchical interconnection between spatially adjacent stacked semiconductor device structures, the present invention increases the flexibility of metal interconnection design and improves the circuit integration degree.

[0053] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are all within the scope and spirit of the present invention as defined in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A method for forming a semiconductor device structure, characterized in that, the method includes: providing a substrate; forming a first fin structure on the substrate, in which K layers of field-effect transistor channel materials and K+1 layers of field-effect transistor channel isolation materials are alternately stacked; forming source and drain regions of a 1_1 field-effect transistor on the first layer of field-effect transistor channel material at the bottom of the first fin structure; forming a 1_1 metal interconnect in contact with the source or drain region of the 1_1 field-effect transistor; forming source and drain regions of a 1_2 field-effect transistor on the second layer of field-effect transistor channel material at the bottom of the first fin structure; forming a 1_2 metal interconnect in contact with the source or drain region of the 1_2 field-effect transistor; repeating the above process as required until a total of K source and drain regions of field-effect transistors are formed, and metal interconnects in contact with the source or drain regions of the K field-effect transistors are formed; removing all field-effect transistor channel isolation materials, and simultaneously preparing gate dielectric layers for the K field-effect transistors, and preparing gate metals layer by layer from bottom to top according to the requirements of the threshold voltage of each field-effect transistor, finally forming a first stacked semiconductor device structure, where K is a positive integer.

2. The method according to claim 1, characterized in that, before forming the source and drain regions of the 1_1 field-effect transistor on the first layer of field-effect transistor channel material at the bottom of the fin structure, it further includes: forming a metal buried line structure on the substrate; before forming the 1_1 metal interconnect in contact with the source or drain region of the 1_1 field-effect transistor, it further includes: forming a 1_3 metal interconnect around the 1_1 field-effect transistor, where the 1_1 metal interconnect is in contact with the metal buried line through the 1_3 metal interconnect.

3. The method according to claim 2, characterized in that, before forming the 1_2 metal interconnect in contact with the source or drain region of the 1_2 field-effect transistor, it further includes: forming a 1_4 metal interconnect around the 1_2 field-effect transistor, where the 1_2 metal interconnect is in contact with the metal buried line through the 1_4 metal interconnect.

4. The method according to claim 1, characterized in that, the method further includes: forming a second fin structure on the substrate, in which L layers of field-effect transistor channel materials and L+1 layers of field-effect transistor channel isolation materials are alternately stacked; forming source and drain regions of a 2_1 field-effect transistor on the first layer of field-effect transistor channel material at the bottom of the second fin structure; forming a 2_1 metal interconnect in contact with the source or drain region of the 2_1 field-effect transistor; forming source and drain regions of a 2_2 field-effect transistor on the second layer of field-effect transistor channel material at the bottom of the second fin structure; forming a 2_2 metal interconnect in contact with the source or drain region of the 2_2 field-effect transistor; repeating the above process as required until a total of L source or drain regions of field-effect transistors are stacked and formed, and metal interconnects in contact with the source or drain regions of the L field-effect transistors are formed; Remove all the channel isolation materials, and simultaneously fabricate the gate dielectric layers of L field-effect transistors. Fabricate the gate metals layer by layer from bottom to top according to the requirements of the threshold voltage of each field-effect transistor, and finally form a second stacked semiconductor device structure. L is a positive integer, and there is a gap between the second stacked semiconductor device structure and the first stacked semiconductor device structure; At least one of the K metal interconnects in the first stacked semiconductor device structure that are in contact with the source region or the drain region is connected to the source region or the drain region of the field-effect transistor in the second stacked semiconductor device structure; Alternatively, at least one of the L metal interconnects in the second stacked semiconductor device structure that are in contact with the source region or the drain region is connected to the source region or the drain region of the field-effect transistor in the first stacked semiconductor device structure.

5. The method according to any one of claims 1 to 4, characterized in that, before forming the 1_2 metal interconnects in contact with the source region or the drain region of the 1_2 field-effect transistor, further comprising: forming 1_5 metal interconnects around the 1_2 field-effect transistor, wherein the 1_1 metal interconnects are in contact with the 1_2 metal interconnects through the 1_5 metal interconnects.

6. A semiconductor device structure, characterized in that, comprising: a substrate; a first stacked semiconductor device structure formed on the substrate, the first stacked semiconductor device structure being fabricated by the method according to any one of claims 1 to 5, the first stacked semiconductor device structure comprising K field-effect transistors formed in a stack, and metal interconnects in contact with the source region or the drain region of each field-effect transistor, K being a positive integer.

7. The semiconductor device structure according to claim 6, characterized in that, the first stacked semiconductor device structure further comprises a metal buried line structure located on the substrate, and the metal buried line is in contact with the metal interconnects.

8. The semiconductor device structure according to claim 6 or 7, characterized in that, further comprising: a second stacked semiconductor device structure formed on the substrate, the second stacked semiconductor device structure comprising L field-effect transistors formed in a stack, and metal interconnects in contact with the source region or the drain region of each field-effect transistor, L being a positive integer; at least one of the K metal interconnects in the first stacked semiconductor device structure that are in contact with the source region or the drain region is connected to the source region or the drain region of the field-effect transistor in the second stacked semiconductor device structure; Alternatively, at least one of the L metal interconnects in the second stacked semiconductor device structure that are in contact with the source region or the drain region is connected to the source region or the drain region of the field-effect transistor in the first stacked semiconductor device structure.

9. The semiconductor device structure according to claim 6 or 7, characterized in that, the different field-effect transistors among the K field-effect transistors are locally interconnected through the metal interconnects.

10. A semiconductor device, characterized in that, comprising the semiconductor device structure according to any one of claims 6 to 9.

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