Transmitter circuit

Abstract

The present invention discloses a transmitter circuit suitable for a digital isolator, which receives a data input signal and couples it to an isolation barrier, generates a receiver input signal and transmits it to a receiver circuit to generate a data output signal. The transmitter circuit generates a transmitter output signal according to the rising edge and falling edge of the data input signal. The transmitter circuit includes a rising and falling edge converter that outputs a converted data signal in response to the rising and falling edges of the data input signal, a delay logic unit that receives the converted data signal and generates a carrier signal based on it, and an AND logic gate that receives the converted data signal and the carrier signal to generate the transmitter output signal. Among them, based on the fact that the number of pulses included in the carrier signal is limited and has a definite number, the present invention effectively reduces problems such as power consumption and electromagnetic interference.

Description

Technical Field

[0001] The present invention relates to a circuit architecture of a transmitter, in particular to a transmitter circuit suitable for a digital isolator and capable of effectively reducing its power consumption and electromagnetic interference. Background Art

[0002] The known existing isolation circuit is an intermediate circuit that can provide voltage isolation between two communication blocks, for example, a transmitter circuit (TX) and a receiver circuit (RX). Such isolation circuits are generally used to eliminate avoidable ground loops and achieve the effect of protecting high-voltage sensitive circuits. By using the isolation circuit, not only can the electrical insulation and signal isolation between circuits be ensured, but also reliable data transmission can be established between two different communication circuits, so that the signal can be free from interference by fast transient common mode noise. In practical applications, since common mode noise is usually predictable and the interference caused by user operation is also inevitable, the isolation circuit that can ensure the safety and reliability of the signal during transmission naturally becomes an indispensable intermediate circuit. Currently, it is known that in some industrial applications vulnerable to voltage surges, fast transients, and high noise, isolation circuits have been widely used to ensure the safety and reliability of transmitted signals.

[0003] Please refer to Figure 1 shown, which discloses a schematic diagram of a conventional isolation circuit architecture in the prior art. Among them, two communication blocks: the transmitter circuit 10 and the receiver circuit 20 are respectively connected to a ground voltage V ss1 and V ss2 , and the isolation circuit provided therein is designed to isolate these two ground voltages V ss1 and V ss2 . The transmitter circuit 10 includes transmitters TX_1 and TX_2, and each of the transmitters TX_1 and TX_2 is composed of an oscillator 11 and a mixer 12. As Figure 1As shown, DI is the input signal of the transmitting-end circuit 10, and the transmitting-end output signals TXO_1 and TXO_2 are generated via transmitters TX_1 and TX_2. The isolation capacitors 22 are configured between the transmitting-end circuit 10 and the receiving-end circuit 20 to couple the transmitting-end output signals TXO_1 and TXO_2 from the transmitting end to the receiving end, so as to generate the receiving-end input signals RXIN_1 and RXIN_2 for the receiving-end circuit 20 to receive. The receiving-end circuit 20 includes receivers RX_1, RX_2 and a mixer 21. Among them, the receiver RX_1 receives the receiving-end input signal RXIN_1, the receiver RX_2 receives the receiving-end input signal RXIN_2, and the mixer 21 electrically coupled to the multiple receivers RX_1 and RX_2 generates an output signal RO. Please refer to Figure 2 shown, which is according to Figure 1 the waveforms of the input signal DI, the transmitting-end output signals TXO_1 and TXO_2, the output oscillation signal OSC of the oscillator 11, the receiving-end input signals RXIN_1 and RXIN_2, and the output signal RO in the conventional isolation circuit architecture. Generally speaking, the voltage level of the output signal RO usually follows the voltage level of the input signal DI.

[0004] However, as Figure 1 shown, it is worth noting that in the conventional isolator circuit architecture, the oscillator 11 must usually be configured at the transmitting end. In this case, as long as the isolator circuit is powered on and operates, the oscillator 11 will start to continuously output infinite pulse signals (pulse carriers), as Figure 2 shown by the waveform of the output oscillation signal OSC in. And these endless pulse signals will cause a huge power consumption and serious electromagnetic interference problems. In addition, whether the input signal DI transitions from the logic state "0" to the logic state "1", or from the logic state "1" to the logic state "0", the oscillator 11 is continuously outputting infinite pulse signals, which will also make it very likely that the transmitting-end output signals TXO_1 and TXO_2 will have severe signal jitter problems.

[0005] Furthermore, from Figure 1 the conventional isolator circuit architecture shown, it can be clearly found that in the conventional isolator circuit architecture, at least two sets of signal transmission channels must be set up, that is to say, it is inevitable to include two sets of transmitters TX_1, TX_2 to match the receivers RX_1, RX_2. In this case, the manufacturing cost and area consumption of the circuit also become a major challenge. Therefore, the conventional isolator circuit is not sufficient for use and cannot be effectively and widely utilized in the industry.

[0006] Therefore, in summary, considering the numerous problem points listed above, it is extremely necessary to adopt various considerations. Thus, the present invention proposes an invention with a novel design and effectively improves the above-mentioned deficiencies. It discloses a novel transmitter circuit architecture without a traditional oscillator. Through this innovative transmitter circuit architecture, many long-existing deficiencies in the prior art can be solved, and at the same time, problems such as power consumption and electromagnetic interference in the circuit can be reduced. Its specific architecture and implementation will be described in detail below. Summary of the Invention

[0007] To solve the problems existing in the prior art, an object of the present invention is to provide a novel and highly innovative transmitter circuit, which is suitable for a digital isolator and helps to reduce problems such as power consumption and electromagnetic interference. Therefore, through the circuit architecture disclosed by the present invention, the long-existing deficiencies in the prior art can be effectively solved, while maintaining accurate data transmission results and excellent system robustness.

[0008] On the other hand, another object of the present invention is to disclose a brand-new transmitter circuit. In this transmitter circuit, there is no need to set a traditional oscillator. By designing an innovative circuit composition to replace the existing oscillator. Based on eliminating the configuration and use of the traditional oscillator, this application can effectively eliminate the huge power consumption and electromagnetic interference and other drawbacks that existed in the past. In addition, the jitter problem of the output signal generated at the transmitter end can also be improved.

[0009] On yet another aspect, another object of the present invention is to provide a transmitter circuit composed of an upper and lower edge converter, a delay logic unit, and an AND logic gate. By integrating these circuits with equivalent simplicity, the transmitter circuit architecture disclosed by the present invention can successfully maintain a relatively low circuit complexity, and thus can be widely applied to any related industry.

[0010] In view of the above-mentioned numerous invention objects of the present invention, these are aspects that cannot be achieved and applied by patents or papers that significantly improve the prior art. Therefore, based on achieving the above-mentioned numerous invention objects, the present invention aims to provide a transmitter circuit suitable for a digital isolator, which includes a receiver circuit and an isolation barrier connected between the transmitter circuit and the receiver circuit. The transmitter circuit receives a data input signal and is coupled to the isolation barrier, so that the isolation barrier generates a receiver input signal to the receiver circuit, so that the receiver circuit generates a data output signal accordingly.

[0011] Wherein, a transmitter circuit generates a transmitter output signal (TXO) according to the data input signal, and the transmitter output signal includes a first partial signal and a second partial signal. The transmitter circuit starts generating the first partial signal in response to a first transition of the data input signal from a first logic state to a second logic state, and stops generating the first partial signal when the data input signal remains in the second logic state.

[0012] After that, the transmitter circuit starts generating the second partial signal in response to a second transition of the data input signal from the second logic state to the first logic state, and stops generating the second partial signal when the data input signal remains in the first logic state. According to a preferred embodiment of the present invention, a first operation time of the first partial signal is different from a second operation time of the second partial signal. Meanwhile, based on the fact that the data input signal (DI) is periodic and the voltage level of the transmitter output signal (TXO) follows the voltage level of the data input signal, the transmitter output signal (TXO) disclosed in the present invention is periodic.

[0013] In a preferred embodiment of the present invention, the transmitter circuit includes: an edge converter, a delay logic unit, and an AND logic gate. Wherein, the edge converter receives the data input signal and outputs a conversion data signal in response to a rising edge and a falling edge of the data input signal. The conversion data signal includes a first partition signal and a second partition signal. The edge converter generates the first partition signal in response to the rising edge of the data input signal, and terminates generating the first partition signal before the data input signal reaches the falling edge. After that, the edge converter generates the second partition signal in response to the falling edge of the data input signal, and terminates generating the second partition signal before the data input signal reaches the next rising edge. And, a first working time of the first partition signal is different from a second working time of the second partition signal.

[0014] The delay logic unit is electrically coupled to the edge converter to receive the conversion data signal and generate a carrier signal accordingly. Wherein, between the rising edge and the falling edge of the data input signal, the carrier signal has a plurality of pulses. According to an embodiment of the present invention, the number of the plurality of pulses of the carrier signal is limited and has a definite number.

[0015] The AND logic gate is electrically coupled to the edge converter and the delay logic unit to receive the conversion data signal and the carrier signal, and generate the transmitter output signal.

[0016] According to an embodiment of the present invention, a first transition of the data input signal from the first logic state to the second logic state is in response to the rising edge of the data input signal. A second transition of the data input signal from the second logic state to the first logic state is in response to the falling edge of the data input signal.

[0017] In addition, a first operation time of a first partial signal of the transmitter output signal is equal to a first working time of a first partition signal of the conversion data signal, and a second operation time of a second partial signal of the transmitter output signal is equal to a second working time of a second partition signal of the conversion data signal.

[0018] According to a preferred embodiment of the present invention, the delay logic unit includes: a plurality of delay units, a plurality of multiplexers, and an OR logic gate. The plurality of delay units are connected in series to receive the conversion data signal, sequentially delay the conversion data signal, and output a plurality of delayed signals, wherein a signal delay time of each delay unit is one cycle. Each multiplexer has two input terminals and an output terminal, wherein the two input terminals are electrically coupled to two consecutive ones of the conversion data signal and the plurality of delayed signals to generate a multiplexed signal at the output terminal. The OR logic gate receives the corresponding multiplexed signal from each output terminal of the plurality of multiplexers and generates the carrier signal accordingly.

[0019] According to an embodiment of the present invention, when two consecutive signals among the conversion data signal and the plurality of delayed signals, where the former is a high voltage level and the latter is a low voltage level, the multiplexed signal is turned to the high voltage level.

[0020] On the other hand, regarding the circuit configuration of the edge converter, the present invention designs the edge converter to include an inverter, a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, and a NOR gate, wherein the inverter receives the data input signal and outputs an inverted data input signal, a first input terminal of the NOR gate is electrically coupled to the first transmission gate and the second transmission gate, a second input terminal of the NOR gate is electrically coupled to the third transmission gate and the fourth transmission gate, and the first transmission gate and the third transmission gate are further respectively connected to an input terminal and an output terminal of the inverter.

[0021] Wherein, the data input signal is respectively delayed by a first period and a second period to respectively control the first transmission gate and the fourth transmission gate, and the inverted data input signal is respectively delayed by the first period and the second period to respectively control the second transmission gate and the third transmission gate, such that the NOR gate outputs the conversion data signal.

[0022] In an embodiment of the present invention, when the first period is longer than the second period, the first working time of the first partition signal of the conversion data signal is longer than the second working time of the second partition signal of the conversion data signal.

[0023] In another embodiment of the present invention, when the second period is longer than the first period, the second working time of the second partition signal of the conversion data signal will be longer than the first working time of the first partition signal of the conversion data signal.

[0024] Therefore, in summary, it can be confirmed that the present application provides a transmitter circuit with a well-designed and suitable architecture for a digital isolator. This innovative circuit can be applied to the transmitting end circuit (TX), and has been verified to successfully minimize system power consumption and electromagnetic interference, while maintaining excellent system robustness and accurate data transmission results. Therefore, it can be believed that compared with the prior art, the advantage of the present invention lies in having good system-level control stability and maintaining the ability to precisely control the isolation circuit.

[0025] The following will be further described in detail through specific embodiments in conjunction with the accompanying drawings, and it will be easier to understand the purpose, technical content, features and achieved effects of the present invention. Brief Description of the Drawings

[0026] Figure 1 FIG. is a schematic diagram of a traditional isolation circuit architecture in the prior art.

[0027] Figure 2 For Figure 1 In the traditional isolation circuit architecture, waveforms of its input signal, transmitting end output signal, output oscillation signal of the oscillator, receiving end input signal, and output signal.

[0028] Figure 3 FIG. is a block schematic diagram of a digital isolator according to an embodiment of the present invention.

[0029] Figure 4 For Figure 3 In the digital isolator, waveforms of its data input signal DI, transmitter output signal TXO, receiver input signal RXIN, and data output signal RO.

[0030] Figure 5 FIG. is a detailed circuit schematic diagram of the transmitter circuit disclosed according to an embodiment of the present invention.

[0031] Figure 6 For Figure 5In the shown transmitter circuit, waveform schematic diagrams of its data input signal DI, converted data signal DI_C, carrier signal CS, and transmitter output signal TXO.

[0032] Figure 7 Detailed circuit schematic diagram of an upper and lower edge converter according to a first embodiment of the present invention.

[0033] Figure 8 According to Figure 7 Waveform schematic diagrams of each node in the shown circuit.

[0034] Figure 9 Detailed circuit schematic diagram of an upper and lower edge converter according to a second embodiment of the present invention.

[0035] Figure 10 According to Figure 9 Waveform schematic diagrams of each node in the shown circuit.

[0036] Figure 11 Detailed circuit schematic diagram of a delay logic unit according to an embodiment of the present invention.

[0037] Figure 12 According to Figure 11 Waveform schematic diagrams of each node in the shown circuit.

[0038] Description of reference numerals: 1 - digital isolator; 10 - transmitter circuit; 11 - oscillator; 12 - mixer; 20 - receiver circuit; 21 - mixer; 22 - isolation capacitor; 50 - upper and lower edge converter; 52 - delay logic unit; 54 - AND logic gate; 111A, 111B, 111C, 111N - delay units; 131A, 131B, 131N - multiplexers; 151 - OR logic gate; DI_C_D_1T - first delay signal; DI_C_D_2T - second delay signal; DI_C_D_3T - third delay signal; MUX1_C - first multiplexed signal; MUX2_C - second multiplexed signal; 301 - transmitter circuit; 303 - isolation barrier; 305 - receiver circuit; V ss1 - first ground voltage; V ss2- Second ground voltage; DI - Data input signal; DI_C - Converted data signal; DI_CP1 - First partition signal; DI_CP2 - Second partition signal; t1’ - First working time; t2’ - Second working time; CS - Carrier signal; RXIN - Receiver input signal; RO - Data output signal; TXO - Transmitter output signal; TXO_D1 - First division signal; TXO_D2 - Second division signal; RE - Rising edge; FE - Falling edge; t1 - First operation time; t2 - Second operation time; INV - Inverter; TG1 - First transmission gate; TG2 - Second transmission gate; TG3 - Third transmission gate; TG4 - Fourth transmission gate; NOR - NOR gate; N1 - First input terminal of the NOR gate; N2 - Second input terminal of the NOR gate; DI_B - Inverted data input signal; DI_D - Delayed signal of the data input signal; DI_3D - Delayed signal of the data input signal; DI_DB - Delayed signal of the inverted data input signal; DI_3DB - Delayed signal of the inverted data input signal; DI_C_D_NT - Delayed signal of the converted data signal; MUXN_C - Multiplexing signal; TX_1 - Transmitter; TX_2 - Transmitter; RX_1 - Receiver; RX_2 - Receiver; TXO_1 - Transmitter end output signal; TXO_2 - Transmitter end output signal; RXIN_1 - Receiver end input signal; RXIN_2 - Receiver end input signal; OSC - Output oscillation signal. Detailed implementation

[0039] The above description of the content of the present invention, together with the following embodiments, is used to demonstrate and explain the spirit and principle of the present invention, and to provide a further explanation of the scope of the present invention. Please refer in detail to the preferred embodiments of the present invention, which are illustrated in the accompanying drawings. And, whenever possible, the same reference numerals will be used in the drawings and descriptions of the present invention to refer to the same or similar elements. It should be understood that in the drawings, for clarity and convenience, the present application may be enlarged in terms of shape and thickness, and elements not specifically shown or described may take various forms well known to those skilled in the art. Once informed by the present invention, these various alternative and modified exemplary embodiments will be obvious to those skilled in the art.

[0040] To illustrate the technical content and features of the present invention and enable those skilled in the art to understand, make and use the present invention, the following application cases are exemplified by many embodiments. However, it should be noted that these embodiments are not used to limit the scope of the present invention. Therefore, all equivalent modifications or changes made in accordance with the spirit of the present invention should be included within the protection scope of the present invention.

[0041] Unless otherwise specified, some conditional clauses or words, such as "may" or "might", are generally used to attempt to convey that embodiments of the present invention "have", but can also be interpreted as features, elements, or steps that are not required. In other embodiments, these features, elements, or steps may not be required.

[0042] In the description of the embodiments of the present application, the reference to "one embodiment" or "in one embodiment" means that the specific features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment. Thus, the appearances of "one embodiment" or "in one embodiment" in various places in the description of the present application do not necessarily all refer to the same embodiment.

[0043] In the embodiments and claims of the present application, specific terms are used to refer to specific elements. Those skilled in the art should understand that the same element may be referred to by different names. The present application does not distinguish between elements with different names but the same function. In the description and claims of the present application, "comprising" is used in an open-ended manner and should therefore be interpreted as "including but not limited to". "Coupled to" is intended to cover any indirect or direct connection. In other words, if a first device is disclosed in the present application as being coupled to a second device, it means that the first device can be connected to the second device directly or indirectly through other intermediate devices or connection means by means of electrical connection, wireless communication, optical communication, or other signal connections, whether there is a signal or not.

[0044] The present invention is described in detail by the following embodiments, which are only illustrative examples. Those skilled in the art can easily make appropriate modifications and variations to the devices and methods while retaining the teaching ideas of the present invention. Therefore, what is disclosed in the following of the present invention should be interpreted as being limited only by the boundaries of the claims. Throughout the application and the claims, except for what is clearly described, the meanings of "a" and "the" include "one or at least one" of the element or elements. And, throughout the application and the claims, except where it is obvious from the context that multiple elements are excluded, the singular also includes the description of multiple elements or elements. Throughout the specification and the claims, unless the content clearly defines the meaning of certain terms, the term "wherein" means "among" or "on". Generally speaking, the meaning of each term used in the present claims and the specification refers to the ordinary meaning known to those skilled in the art, unless the meaning is otherwise noted. Some terms used to describe the present invention and which can be used to guide those skilled in the art to understand the present invention will be discussed. Each illustrative example in this specification cannot be used to limit the protection scope of the present invention.

[0045] The terms "substantially", "about", "approximately", and "roughly" may refer to a value within 20% of a given value or range, preferably within 10%. In addition, the quantities or numbers provided in this application may be approximate values, and if not specifically stated, they may be described using the above terms. When a quantity, density, or other parameter includes a specified range, a preferred range, or a listed ideal value, their values may be considered as any number within the given range.

[0046] First, please refer to the drawings of the present invention Figure 3 As shown, it is a block diagram of a digital isolator according to an embodiment of the present invention. As shown, the digital isolator 1 includes a transmitter circuit 301, an isolation barrier 303, and a receiver circuit 305. The transmitter circuit 301 is electrically coupled to a first ground voltage V ss1 , and the receiver circuit 305 is electrically coupled to a second ground voltage V ss2 . The isolation barrier 303 is electrically coupled between the transmitter circuit 301 and the receiver circuit 305. The transmitter circuit 301 disclosed in the present invention is adapted to receive a data input signal DI and couple it to the isolation barrier 303, such that the isolation barrier 303 generates a receiver input signal RXIN for the receiver circuit 305 to receive. Thus, the receiver circuit 305 can process the receiver input signal RXIN and generate a data output signal RO accordingly. According to an embodiment of the present invention, the isolation barrier 303 used, for example, may be composed of at least one isolation capacitor or its equivalent element.

[0047] According to a preferred embodiment of the present invention, the transmitter circuit 301 disclosed in the present invention generates a transmitter output signal TXO according to the data input signal DI. Please also refer to Figure 4 As shown, it is a waveform diagram of the data input signal DI, the transmitter output signal TXO, the receiver input signal RXIN, and the data output signal RO in the digital isolator according to Figure 3 .

[0048] As Figure 4As shown, it can be seen that generally, the voltage level of the transmitter output signal TXO usually follows the voltage level of the data input signal DI. Since the data input signal DI is periodic, the transmitter output signal TXO is also periodic. Specifically, the transmitter output signal TXO includes a first partial signal TXO_D1 and a second partial signal TXO_D2, and the transmitter output signal TXO is periodic. The transmitter circuit 301 starts generating the first partial signal TXO_D1 in response to a first transition of the data input signal DI from a first logic state to a second logic state, and stops generating the first partial signal TXO_D1 when the data input signal DI is still in the second logic state. In this embodiment, the first logic state refers to when the data input signal DI is at a low voltage level, which can be represented as digital logic "0". And the second logic state refers to when the data input signal DI is at a high voltage level, which can be represented as digital logic "1". The "first transition" of the data input signal DI from the first logic state to the second logic state refers to when the data input signal DI transitions from digital logic "0" to digital logic "1", which is in response to a rising edge RE of the data input signal DI. Similarly, the "second transition" of the data input signal DI from the second logic state to the first logic state refers to when the data input signal DI transitions from digital logic "1" to digital logic "0", which is in response to a falling edge FE of the data input signal DI.

[0049] As shown in the figure, the transmitter circuit 301 starts generating the second sub-signal TXO_D2 in response to the second transition of the data input signal DI from the second logic state "1" to the first logic state "0", and stops generating the second sub-signal TXO_D2 when the data input signal DI remains in the first logic state "0". According to a preferred embodiment of the present invention, the first sub-signal TXO_D1 has a first operation time t1, which is the time interval between the start and end of the transmitter circuit 301 generating the first sub-signal TXO_D1. Similarly, the second sub-signal TXO_D2 has a second operation time t2, which is the time interval between the start and end of the transmitter circuit 301 generating the second sub-signal TXO_D2. According to an embodiment of the present invention, the first operation time t1 of the first sub-signal TXO_D1 and the second operation time t2 of the second sub-signal TXO_D2 are different.

[0050] For example, the first operation time t1 of the first sub-signal TXO_D1 can be as Figure 4 shown, slightly longer than the second operation time t2 of the second sub-signal TXO_D2. Or, in other embodiments of the present invention, the second operation time t2 of the second sub-signal TXO_D2 can also be selectively longer than the first operation time t1 of the first sub-signal TXO_D1, but the present invention is not limited to which of the first operation time t1 and the second operation time t2 is longer or shorter.

[0051] Next, please refer to Figure 5 shown, which is a detailed circuit schematic diagram of the transmitter circuit disclosed according to an embodiment of the present invention. As Figure 5 shown, the transmitter circuit 301 disclosed in the present invention includes a rising and falling converter 50, a delay logic unit 52, and an AND logic gate 54. Among them, the rising and falling converter 50 is adapted to receive the data input signal DI and output a converted data signal DI_C accordingly. The delay logic unit 52 is electrically coupled to the rising and falling converter 50 to receive the converted data signal DI_C and generate a carrier signal CS accordingly. The AND logic gate 54 is electrically coupled to the rising and falling converter 50 and the delay logic unit 52 to receive the converted data signal DI_C and the carrier signal CS, and generates and outputs the transmitter output signal TXO through an AND logic algorithm.

[0052] Figure 6 According toFigure 5 In the transmitter circuit shown, waveform diagrams of a data input signal DI, a converted data signal DI_C, a carrier signal CS, and a transmitter output signal TXO. As can be seen from Figure 6 the waveform diagram, the upper and lower edge converter 50 is adapted to receive the data input signal DI and generate the converted data signal DI_C in accordance with and in response to a rising edge RE and a falling edge FE of the data input signal DI. Specifically, the converted data signal DI_C includes a first partition signal DI_CP1 and a second partition signal DI_CP2, and based on the data input signal DI being periodic, the converted data signal DI_C is periodic. According to an embodiment of the present invention, the upper and lower edge converter 50 generates the first partition signal DI_CP1 in response to the rising edge RE of the data input signal DI and terminates generating the first partition signal DI_CP1 before the data input signal DI reaches its falling edge FE. Thereafter, the upper and lower edge converter 50 generates the second partition signal DI_CP2 in response to the falling edge FE of the data input signal DI and terminates generating the second partition signal DI_CP2 before the data input signal DI reaches its next rising edge RE.

[0053] According to a preferred embodiment of the present invention, the first partition signal DI_CP1 has a first operating time t1', and the first operating time t1' is the time interval between when the upper and lower edge converter 50 starts generating the first partition signal DI_CP1 and when it terminates generating the first partition signal DI_CP1. Similarly, the second partition signal DI_CP2 has a second operating time t2', and the second operating time t2' is the time interval between when the upper and lower edge converter 50 starts generating the second partition signal DI_CP2 and when it terminates generating the second partition signal DI_CP2. According to an embodiment of the present invention, the first operating time t1' of the first partition signal DI_CP1 and the second operating time t2' of the second partition signal DI_CP2 are different.

[0054] The delay logic unit 52 is electrically coupled to the upper and lower edge converter 50 to receive the converted data signal DI_C and generate the carrier signal CS therefrom. As can be clearly seen from the waveforms shown in Figure 6 , between the rising edge RE of the data input signal DI and the falling edge FE of the data input signal DI, the carrier signal CS has a plurality of pulses, and the number of these pulses is limited. In other words, according to an embodiment of the present invention, the number of the plurality of pulses of the disclosed carrier signal CS is limited and has a definite number.

[0055] After that, based on the AND logic gate 54 being electrically coupled to the upper and lower edge converters 50 and the delay logic unit 52, and receiving the converted data signal DI_C and the carrier signal CS as the input signals of the AND logic gate 54, the AND logic gate 54 can generate the transmitter output signal TXO at its output end by performing an AND logic operation on the converted data signal DI_C and the carrier signal CS. It should be noted that due to the AND logic provided by the AND logic gate 54, it can control the first operation time t1 of the first partial signal TXO_D1 of the transmitter output signal TXO to be equal to the first working time t1' of the first partition signal DI_CP1 of the converted data signal DI_C, and control the second operation time t2 of the second partial signal TXO_D2 of the transmitter output signal TXO to be equal to the second working time t2' of the second partition signal DI_CP2 of the converted data signal DI_C.

[0056] Furthermore, please refer to Figure 7 as shown, which is a detailed circuit schematic diagram of the upper and lower edge converter according to a first embodiment of the present invention. Figure 8 According to Figure 7 is a waveform schematic diagram of each node in the circuit shown. As shown in the figure, the upper and lower edge converter 50 includes an inverter INV, a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, and a NOR gate NOR. Among them, the inverter INV receives the data input signal DI and outputs an inverted data input signal DI_B. One input terminal (DI) and the output terminal (DI_B) of the inverter INV are respectively connected to the first transmission gate TG1 and the third transmission gate TG3. According to the first embodiment of the upper and lower edge converter disclosed in the present invention, wherein, the data input signal DI is delayed by a first period 3T to form a signal shown as "DI_3D", and the data input signal DI is delayed by a second period 1T to form a signal shown as "DI_D". In this first embodiment, the first period 3T is longer than the second period 1T. And, the delayed signal "DI_3D" formed by delaying the data input signal DI by the first period 3T is used to control the first transmission gate TG1, and the delayed signal "DI_D" formed by delaying the data input signal DI by the second period 1T is used to control the fourth transmission gate TG4.

[0057] Similarly, the inverted data input signal DI_B is delayed by a first period 3T to form a signal shown as "DI_3DB", and the inverted data input signal DI_B is delayed by a second period 1T to form a signal shown as "DI_DB". These delayed signals "DI_3DB" and "DI_DB" are respectively used to control the second transmission gate TG2 and the third transmission gate TG3. A first input terminal N1 of the NOR gate is electrically coupled to the first transmission gate TG1 and the second transmission gate TG2, and a second input terminal N2 of the NOR gate is electrically coupled to the third transmission gate TG3 and the fourth transmission gate TG4. According to an embodiment of the present invention, when the control signals of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are at a high voltage level (digital logic is "1"), the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 can be made conductive; otherwise, when the control signals of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are at a low voltage level (digital logic is "0"), the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 will be made open. Through this design, the present invention can obtain as Figure 8 shown in: the waveform diagrams of the first input terminal N1 and the second input terminal N2. Then, the NOR gate can generate and output a converted data signal DI_C as shown in Figure 8 . It should be noted that in the first embodiment of the edge converter disclosed in the present invention, since the first period 3T is longer than the second period 1T, it can be controlled such that the first working time t1' of the first partition signal DI_CP1 of the converted data signal DI_C is longer than the second working time t2' of the second partition signal DI_CP2 of the converted data signal DI_C.

[0058] On the other hand, please refer to Figure 9 shown, which is a detailed circuit schematic diagram of an edge converter according to a second embodiment of the present invention. Figure 10 For Figure 9Waveform schematic diagrams of each node in the circuit shown. As shown in the figure, the upper and lower edge converter 50 includes an inverter INV, a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, and a NOR gate NOR. Among them, the inverter INV receives a data input signal DI and outputs an inverted data input signal DI_B. A first input terminal N1 of the NOR gate NOR is electrically coupled to the first transmission gate TG1 and the second transmission gate TG2, and a second input terminal N2 of the NOR gate NOR is electrically coupled to the third transmission gate TG3 and the fourth transmission gate TG4. Thus, the NOR gate NOR can generate and output a converted data signal DI_C as shown in Figure 10 as shown. When we compare the upper and lower edge converter of this second embodiment with the previous first embodiment (as shown in Figure 7 ), it can be observed that: in this second embodiment, the first period for delaying the data input signal DI and the inverted data input signal DI_B is 1T, and the second period for delaying the data input signal DI and the inverted data input signal DI_B is 3T. Therefore, in this second embodiment, the control signals of the first transmission gate TG1 and the fourth transmission gate TG4 will be the delay signals "DI_D" and "DI_3D" respectively, and the control signals of the second transmission gate TG2 and the third transmission gate TG3 will be the delay signals "DI_DB" and "DI_3DB" respectively.

[0059] Therefore, in the second embodiment of the upper and lower edge converter disclosed in the present invention, since the second period 3T is longer than the first period 1T, it can be controlled such that the second working time t2' of the second partition signal DI_CP2 of the converted data signal DI_C is longer than the first working time t1' of the first partition signal DI_CP1 of the converted data signal DI_C.

[0060] Therefore, in view of the above Figures 7 - 8 and Figures 9 - 10The disclosed embodiments can effectively prove how the present invention is precisely and ingeniously designed for the upper and lower edge converters, such that the first working time t1' of the first partition signal DI_CP1 of the conversion data signal DI_C is different from the second working time t2' of the second partition signal DI_CP2 of the conversion data signal DI_C. According to the technical solution disclosed by the present invention, the first working time t1' of the first partition signal DI_CP1 is not limited to being longer or shorter than the second working time t2' of the second partition signal DI_CP2. As long as the first working time t1' of the first partition signal DI_CP1 and the second working time t2' of the second partition signal DI_CP2 are different from each other, such that the first operation time t1 of the first sub-signal TXO_D1 of the transmitter output signal TXO is also different from the second operation time t2 of the second sub-signal TXO_D2 of the transmitter output signal TXO, the present invention can be successfully implemented as an ideal digital isolator and its transmitter circuit structure. At the same time, compared with the prior art, it is more conducive to reducing the power consumption and electromagnetic interference problems in the system.

[0061] Therefore, in summary, according to the technical solution taught by the present invention, those with ordinary knowledge in the art can make modifications or variations according to the specifications and requirements of their actual circuits without departing from the spirit and intention of the present invention. However, in the case of equivalent variations of the present invention, they should still fall within the scope of the present invention. In other words, the present invention should not be limited to the above-mentioned several illustrative examples.

[0062] In addition, regarding how the present invention designs a delay logic unit, which can be used to replace the oscillator part that must be used in the traditional transmitter circuit structure, the applicant further provides a detailed internal circuit schematic diagram of the delay logic unit, which is described in detail as follows.

[0063] Please refer to Figure 11 as shown, which is a detailed circuit schematic diagram of a delay logic unit according to an embodiment of the present invention. Figure 12 For Figure 11 the waveform schematic diagrams of each node in the circuit shown. As shown in the figure, the delay logic unit 52 includes a plurality of delay units 111A, 111B, 111C... 111N, a plurality of multiplexers 131A, 131B... 131N, and an OR logic gate 151.

[0064] Among them, the multiple delay units 111A, 111B, 111C... 111N are connected in series with each other to receive the converted data signal DI_C, delay the converted data signal DI_C in sequence, and output multiple delayed signals DI_C_D_1T, DI_C_D_2T, DI_C_D_3T... DI_C_D_NT. According to an embodiment of the present invention, the signal delay time of each of the delay units 111A, 111B, 111C... 111N is one period "T". Therefore, the first delay unit 111A receives the converted data signal DI_C, delays the converted data signal DI_C by one period "T", and outputs it as a first delayed signal DI_C_D_1T. The second delay unit 111B receives the first delayed signal DI_C_D_1T, delays the first delayed signal DI_C_D_1T by one more period "T", and outputs it as a second delayed signal DI_C_D_2T. The third delay unit 111C receives the second delayed signal DI_C_D_2T, delays the second delayed signal DI_C_D_2T by one more period "T", and outputs it as a third delayed signal DI_C_D_3T, and so on.

[0065] Each multiplexer 131A, 131B... 131N has two input terminals and one output terminal. Among them, the two input terminals are electrically coupled to two consecutive ones of the converted data signal and the multiple delayed signals, so as to generate a multiplexed signal at its output terminal. For example, the two input terminals of the multiplexer 131A are electrically coupled to the converted data signal DI_C and the first delayed signal DI_C_D_1T, and generate a first multiplexed signal MUX1_C at its output terminal.

[0066] The two input terminals of the multiplexer 131B are electrically coupled to the second delayed signal DI_C_D_2T and the third delayed signal DI_C_D_3T, and generate a second multiplexed signal MUX2_C at its output terminal, and so on.

[0067] Specifically, please refer to Figure 12 the waveform schematic diagram of the multiplexed signal shown. According to an embodiment of the present invention, when the converted data signal DI_C and two consecutive signals among the multiple delayed signals DI_C_D_1T, DI_C_D_2T, DI_C_D_3T..., where the former is at a high voltage level and the latter is at a low voltage level, the multiplexed signal will be turned to a high voltage level. Therefore, the present invention can generate waveform schematic diagrams of several multiplexed signals MUX1_C, MUX2_C... as shown in Figure 12 the figure.

[0068] Afterwards, the OR logic gate 151 can receive the multiplexed signals MUX1_C, MUX2_C, …, MUXN_C from the output terminals of the multiplexers 131A, 131B, …, 131N, and generate a carrier signal CS accordingly. From Figure 12 From the disclosed waveform diagram, it can be confirmed that the carrier signal CS designed and generated by the present invention has multiple pulses, and the number of these pulses is finite and has a definite quantity. In view of this, the present invention generates a carrier signal CS with a finite and definite number of pulses by designing a delay logic unit 52, and successfully uses the delay logic unit 52 to replace the existing oscillator that continuously outputs continuous and uninterrupted pulses in the prior art. Through such improvements and replacements, the present invention can effectively reduce the huge power consumption and serious electromagnetic interference problems in the prior art. In addition, the present invention can also maintain an accurate data output signal while avoiding signal jitter problems.

[0069] Therefore, according to the embodiments disclosed above, it can be believed that the transmitter circuit disclosed by the present invention is novel and unprecedented. It is composed of an edge converter, a delay logic unit, an AND logic gate, etc. to replace the oscillator that must be configured in the prior art. Through the ingenious design of the present invention, the transmitter circuit can generate its transmitter output signal (TXO) according to the data input signal (DI) and in response to the rising edge and falling edge of the data input signal (DI). Under this architecture, the use of a traditional oscillator can be saved, enabling the present invention to effectively facilitate improvements in power consumption and electromagnetic interference. At the same time, it also ensures the accuracy of data transmission and maintains the robustness of the system output voltage.

[0070] Therefore, in view of the above, compared with the prior art, it is obvious that through the embodiments and circuit architectures disclosed by the present invention, it can effectively solve many deficiencies existing in the prior art and present more efficient circuit performance. And based on the technical solutions disclosed by the present invention, it can be applied not only to common electronic components, but also more widely to various electronic circuit components such as the semiconductor industry, the integrated circuit industry, or power electronics. It is obvious that the technical solutions of the present invention indeed have excellent industrial applicability and competitiveness. At the same time, through various experimental data and empirical data, etc., it is verified that the technical features, methods, and achieved effects disclosed by the present invention are significantly different from the current solutions and are not easily achievable by those familiar with this technology.

[0071] The above-described embodiments are only for illustrating the technical ideas and features of the present invention, and their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. It should not be used to limit the scope of the present invention. That is, all equivalent changes or modifications made in accordance with the spirit disclosed by the present invention should still be covered within the scope of the present invention.

Claims

1. A transmitter circuit, characterized in that, Suitable for a digital isolator, the digital isolator includes a receiver circuit and an isolation barrier connected between the transmitter circuit and the receiver circuit. The transmitter circuit receives a data input signal and is coupled to the isolation barrier, causing the isolation barrier to generate a receiver input signal to the receiver circuit, so that the receiver circuit generates a data output signal accordingly; Wherein, the transmitter circuit generates a transmitter output signal according to the data input signal. The transmitter output signal includes a first partial signal and a second partial signal. The transmitter circuit starts to generate the first partial signal in response to a first transition of the data input signal from a first logic state to a second logic state, and stops generating the first partial signal when the data input signal is still in the second logic state. The first transition of the data input signal from the first logic state to the second logic state is in response to a rising edge of the data input signal, so that the generation of the first partial signal is synchronized with the rising edge of the data input signal; and Wherein, the transmitter circuit starts to generate the second partial signal in response to a second transition of the data input signal from the second logic state to the first logic state, and stops generating the second partial signal when the data input signal is still in the first logic state. The second transition of the data input signal from the second logic state to the first logic state is in response to a falling edge of the data input signal, so that the generation of the second partial signal is synchronized with the falling edge of the data input signal; and Wherein, a first operation time of the first partial signal and a second operation time of the second partial signal are different.

2. The emitter circuit according to claim 1, wherein Based on the data input signal being periodic, the transmitter output signal is periodic.

3. The transmitter circuit according to claim 1, characterized in that, The transmitter circuit includes: An edge converter that receives the data input signal and outputs a converted data signal in response to the rising edge and the falling edge of the data input signal. The converted data signal includes a first partition signal and a second partition signal. The edge converter generates the first partition signal in response to the rising edge of the data input signal and terminates generating the first partition signal before the data input signal reaches the falling edge. The edge converter generates the second partition signal in response to the falling edge of the data input signal and terminates generating the second partition signal before the data input signal reaches the next rising edge, and a first working time of the first partition signal and a second working time of the second partition signal are different; A delay logic unit electrically coupled to the edge converter to receive the converted data signal and generate a carrier signal accordingly. Between the rising edge of the data input signal and the falling edge of the data input signal, the carrier signal has a plurality of pulses; and An AND logic gate electrically coupled to the edge converter and the delay logic unit to receive the converted data signal and the carrier signal and generate the transmitter output signal.

4. The transmitter circuit according to claim 3, characterized in that, The number of the plurality of pulses of the carrier signal is finite and has a definite number.

5. The emitter circuit according to claim 3, wherein The first operation time of the first partial signal of the transmitter output signal is equal to the first working time of the first partition signal of the conversion data signal, and the second operation time of the second partial signal of the transmitter output signal is equal to the second working time of the second partition signal of the conversion data signal.

6. The transmitter circuit according to claim 3, wherein The delay logic unit includes: A plurality of delay units connected in series with each other to receive the conversion data signal, sequentially delay the conversion data signal, and output a plurality of delayed signals, wherein the signal delay time of each delay unit is one cycle; A plurality of multiplexers, each multiplexer having two input terminals and one output terminal, wherein the two input terminals are electrically coupled to two consecutive ones of the conversion data signal and the plurality of delayed signals to generate a multiplexed signal at the output terminal; and An OR logic gate that receives the corresponding multiplexed signal from each output terminal of the plurality of multiplexers and generates the carrier signal therefrom.

7. The transmitter circuit according to claim 6, characterized in that, When two consecutive signals among the conversion data signal and the plurality of delayed signals, where the former is a high voltage level and the latter is a low voltage level, the multiplexed signal will be turned to the high voltage level.

8. The transmitter circuit according to claim 3, wherein The edge converter includes an inverter, a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, and a NOR gate, wherein the inverter receives the data input signal and outputs an inverted data input signal, a first input terminal of the NOR gate is electrically coupled to the first transmission gate and the second transmission gate, a second input terminal of the NOR gate is electrically coupled to the third transmission gate and the fourth transmission gate, the first transmission gate and the third transmission gate are further respectively connected to an input terminal and an output terminal of the inverter, wherein the data input signal is respectively delayed by a first period and a second period to respectively control the first transmission gate and the fourth transmission gate, and the inverted data input signal is respectively delayed by the first period and the second period to respectively control the second transmission gate and the third transmission gate, such that the NOR gate outputs the conversion data signal.

9. The transmitter circuit according to claim 8, wherein, When the first period is longer than the second period, the first working time of the first partition signal of the conversion data signal is longer than the second working time of the second partition signal of the conversion data signal.

10. The emitter circuit according to claim 8, characterized in that, When the second period is longer than the first period, the second working time of the second partition signal of the conversion data signal is longer than the first working time of the first partition signal of the conversion data signal.

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