Method and device for real-time online reconstruction of internal digital filter of waveform generator

Abstract

The present invention belongs to the field of waveform generation, and specifically relates to a method and device for real-time online reconstruction of a digital filter inside a waveform generator. The present invention solves the problem that the function of the digital filter inside the waveform generator cannot be updated online in real time by placing the working waveform module separately in another working waveform FPGA and loading the working waveform FPGA program configuration file online. When reconstructing the working waveform module by updating the working FPGA program, the present invention adds a temporary waveform to replace the working waveform, and compensates for the delay difference of different channels through delay correction, so that the normal use of the radar can be not affected during operation, and the function of real-time online reconstruction of the digital filter while working can be achieved.

Description

Technical Field

[0001] The invention belongs to the field of waveform generation, and in particular relates to a method and a device for real-time online reconstruction of an internal digital filter of a waveform generator. Background Art

[0002] As combat scenarios become more complex, the design and improvement of fully digital radars are more urgent. Fully digital radars need to put more functions into digitally controllable devices, among which some mixing and filtering of waveform generators need to be implemented by FPGA.

[0003] When designing the FPGA function module of the traditional waveform generator, a large number of FPGA IP cores are used to simplify the design, especially for digital filters. Many different digital filters have their own corresponding IP cores. However, when using FPGA IP cores to simplify the design of digital filters, since the filter coefficient COE file generated by MATLAB is generally required to be preset when the filter IP core is generated, once the digital filter design is completed and finally configured to the FPGA, the parameters of the digital filter cannot be modified. If the digital filter group method is used to switch the filter channel design method, the internal resources of the FPGA are often insufficient.

[0004] When using the traditional digital filter design method, after the digital filter design inside the waveform generator is completed and finally configured to the FPGA and delivered for use, if you want to modify the digital filter, you can only disassemble the waveform generator and re-burn the FPGA program containing the new digital filter parameters. This method is time-consuming and cumbersome, and it also affects normal use. Therefore, it is very necessary to study a method for real-time online reconstruction of the digital filter inside the waveform generator without interrupting work. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention provides a method and device for real-time online reconstruction of the internal digital filter of a waveform generator. The present invention uses two FPGAs in the waveform generator: one is used as the main control FPGA to perform data encoding and decoding, control instruction operation, data reading and writing, monitoring and reporting, data selection and loading of the update program of another working waveform FPGA, and also completes the generation of temporary waveforms; the other is used as the working waveform FPGA, which is only responsible for the generation of the working waveform. The present invention realizes the function of real-time online reconstruction of the internal digital filter of the waveform generator without interrupting the work.

[0006] The technical solution of the present invention is: a method for real-time online reconstruction of the internal digital filter of the waveform generator, comprising the following steps:

[0007] Step 1: Store the working waveform module in the radar waveform generator separately in a working waveform FPGA of the waveform generator, generate different FPGA filter IP cores in advance according to the filter parameters corresponding to different waveforms required by the working waveform module, and generate multiple program configuration files together with the FPGA project of the entire working waveform module, and store them in the wave control extension;

[0008] Step 11: Calculate the corresponding filter parameters in advance according to the various waveforms required for work, and use MATLAB to generate the corresponding filter coefficient COE file according to these filter parameters;

[0009] Step 12: Import the COE file generated in step 11 into the IP core setting tool of the FPGA design software to generate the filter IP core, and use the FPGA design software to synthesize the IP core and the entire FPGA project to obtain the program configuration file;

[0010] Step 13: Store the program configuration file generated in step 12 in the wave control extension according to the corresponding different waveforms;

[0011] Step 2: According to the waveform that needs to be switched, the wave control extension sends the filter reconstruction instruction and sends the program configuration file corresponding to the filter to the DDR3 of the main control FPGA;

[0012] Step 3: According to the filter reconstruction instruction, the main control FPGA replaces the working waveform module with its own temporary waveform module to prevent the radar waveform from being interrupted, and corrects the delay parameters of different channels, and then reads the working waveform module program configuration data in DDR3 to update the working waveform FPGA program;

[0013] Step 4: After the working waveform FPGA program is updated and the working waveform is regenerated, the main control FPGA replaces the temporary waveform with the working waveform to complete the filter reconstruction.

[0014] The present invention also discloses a device for real-time online reconstruction of the internal digital filter of the waveform generator, which is characterized by comprising a wave control extension and a waveform generator, wherein the waveform generator comprises a photoelectric conversion module, a main control FPGA, a working waveform FPGA, DDR3, FLASH and a D / A conversion module, the wave control extension comprises a computer with a human-machine interactive interface and a photoelectric adapter board, the photoelectric conversion module is used to send and receive wave control optical signals, and to perform data transmission between the wave control extension and the main control FPGA,

[0015] The main control FPGA is used to receive and process the data from the wave control extension, control the configuration of the working waveform FPGA, and generate temporary waveforms;

[0016] The working waveform FPGA is used to generate the working waveform; DDR3 is used to store the demodulated waveform data and program configuration data sent by the wave control extension; FLASH is used to store the program configuration data of the main control FPGA and the working waveform FPGA;

[0017] The main control FPGA includes a data processing module, a temporary waveform module and a data selection module;

[0018] The temporary waveform module includes NCO mixing, FIR and CIC filters, and waveform form control. NCO mixing generates point frequency data through the digital control oscillator IP core and mixes with the waveform to complete frequency adjustment. FIR and CIC filters perform interpolation filtering on the mixing data to filter out the image frequency generated by the mixing, and adjust the data rate of the mixing data to be consistent with the temporary waveform DAC data.

[0019] The working waveform module loaded inside the working waveform FPGA is consistent with the temporary waveform module. The FIR and CIC filters in the working waveform FPGA set the filter order, insertion loss, sampling rate, cutoff frequency and amplitude attenuation at the cutoff frequency according to different mixing processes. The filter coefficient COE file is generated according to these parameters in the MATLAB software. The file is imported into the IP core setting tool of the FPGA design software to generate the filter IP core, and the FPGA design software is used to integrate the IP core and the entire FPGA project to obtain the program configuration file, which is finally burned into the working waveform FPGA to implement the setting of these parameters.

[0020] According to the device for real-time online reconstruction of the internal digital filter of the waveform generator as described above, it is characterized in that: the data processing module includes a data encoding and decoding module, a control instruction operation module, a data reading and writing module, a program loading module, and a monitoring and reporting module; the data encoding and decoding module includes encoding and decoding functions, and during decoding, the waveform data, waveform form parameters, program configuration data, delay data and control information are decoded through the frame header and the command control word according to the custom communication protocol, and the reporting status and reporting parameters are packaged and uploaded during encoding; the control instruction operation module completes various required tasks according to the decoded control information; the data reading and writing module caches the decoded data into DDR3 and the main control FPGA, and when outputting the waveform, the waveform data is read from the external DDR3 and sent to the temporary waveform module and the working waveform module together with the control information, and when reconfiguring the working waveform FPGA, the program configuration data is read from the external DDR3 and sent to the program loading module; the program loading module is used to operate the program loading process of the working waveform FPGA; the monitoring and reporting module is used to detect the state of the waveform generator, and report the state and feedback some parameters;

[0021] According to the above-mentioned device for real-time online reconstruction of the internal digital filter of the waveform generator, it is characterized in that: the data selection module includes a channel delay correction module and a waveform channel switching module; the channel delay correction module completes the delay correction of the temporary waveform channel and the working waveform channel; the waveform channel switching module completes the channel switching;

[0022] According to the device for real-time online reconstruction of the internal digital filter of the waveform generator as described above, it is characterized in that: when the waveform generator is powered on, the main control FPGA reads its own program configuration data from FLASH to complete the power-on program loading. After the loading is completed, the program configuration data of the working waveform FPGA is read from FLASH to complete the program loading of the working waveform FPGA; after the waveform generator completes the program loading, it receives the terminal waveform data, waveform form parameters and control information sent by the wave control extension to generate the working waveform.

[0023] The beneficial effects of the present invention are as follows: First, by placing the working waveform module separately in another working waveform FPGA and loading the working waveform FPGA program configuration file online, the problem of the original inability to update the internal digital filter of the waveform generator online in real time is solved. Second, by updating the working FPGA program to reconstruct the working waveform module, a temporary waveform is added to replace the working waveform, and the delay difference of different channels is compensated by delay correction, so that the normal use of the radar can be not affected during operation, and the function of real-time online reconstruction of the digital filter can be achieved while working. Third, optical fiber is used for online loading, so that the loading process of data and programs can be completed online at high speed, avoiding the trouble of disassembling the equipment to burn the FPGA program during debugging and use, improving reliability, saving time, and facilitating use under harsh outdoor conditions. Fourth, the function of reconstructing the subsequent processing module of digital mixing can be realized, so that designers do not need to consider the digital structure of subsequent processing of digital mixing during design, which can make the design more flexible and changeable. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is the system principle block diagram.

[0025] Figure 2 It is a structural diagram of the data processing module.

[0026] Figure 3 It is a structural diagram of the temporary waveform module.

[0027] Figure 4 This is a structural diagram of the data selection module.

[0028] Figure 5 This is a structural diagram of the working waveform FPGA. DETAILED DESCRIPTION

[0029] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0030] like Figure 1 As shown, the hardware of the present invention includes a wave control extension and a waveform generator, wherein the waveform generator includes an optoelectronic conversion module, a main control FPGA, a working waveform FPGA, DDR3, FLASH and a D / A conversion module, and the wave control extension includes a computer with a human-machine interface and an optoelectronic adapter board. The optoelectronic conversion module is used to send and receive wave control optical signals and to transmit data between the wave control extension and the main control FPGA. To ensure the transmission rate, a device with a speed of more than 2.5Gb / s is generally selected. The main control FPGA is used to receive and process the data of the wave control extension, control the configuration of the working waveform FPGA, and generate a temporary waveform. The working waveform FPGA is used to generate a working waveform. DDR3 is used to store the demodulated waveform data and program configuration data sent by the wave control extension. FLASH is composed of multiple chips and is used to store the program configuration data of the main control FPGA and the working waveform FPGA. The D / A conversion module generally uses a high-speed DAC chip with a sampling rate exceeding 4GSPS to achieve a high frequency band and a large bandwidth.

[0031] The main control FPGA contains three digital modules: data processing module, temporary waveform module and data selection module. The main function of the main control FPGA is to receive the program configuration data of the working waveform FPGA online and reconfigure the working waveform FPGA. At the same time, it provides a temporary waveform in the reconfiguration process to avoid the radar from failing to work.

[0032] like Figure 2 As shown, the data processing module is a software module, including a data encoding and decoding module, a control instruction operation module, a data reading and writing module, a program loading module, and a monitoring and reporting module. The data encoding and decoding module includes encoding and decoding functions. When decoding, the waveform data, waveform form parameters, program configuration data, delay data and control information are decoded through the frame header and command control word according to the custom communication protocol. When encoding, the reporting status and reporting parameters are packaged and uploaded. The control instruction operation module completes various required tasks according to the decoded control information. The data reading and writing module caches the decoded data into DDR3 and the main control FPGA. When outputting the waveform, the waveform data is read from the external DDR3 and sent to the temporary waveform module and the working waveform module together with the control information. When reconfiguring the working waveform FPGA, the program configuration data is read from the external DDR3 and sent to the program loading module. The program loading module is used to operate the program loading process of the working waveform FPGA. The monitoring and reporting module is used to detect the state of the waveform generator, and report the state and feedback some parameters.

[0033] like Figure 3As shown in the figure, the temporary waveform module includes NCO mixing, FIR and CIC filters, and waveform form control. NCO mixing generates point frequency data through the digital control oscillator IP core and mixes with the waveform to complete frequency adjustment. FIR and CIC filters perform interpolation filtering on the mixing data to filter out the image frequency generated by the mixing, and adjust the data rate of the mixing data to be consistent with the temporary waveform DAC data. The waveform form control completes the adjustment of some parameters such as waveform bandwidth, pulse width, period, and number of pulses.

[0034] like Figure 4 As shown, the data selection module includes a channel delay correction module and a waveform channel switching module. The channel delay correction module completes the delay correction of the temporary waveform channel and the working waveform channel. The waveform channel switching module completes the channel switching.

[0035] like Figure 5 As shown, the working waveform FPGA mainly loads the working waveform module, and the overall software structure is consistent with the temporary waveform module, but the FPGA where the working waveform module is located can be reconfigured online in real time to complete the modification of internal parameters.

[0036] The FIR and CIC filters in the working waveform FPGA need to set parameters such as filter order, insertion loss, sampling rate, cutoff frequency, and amplitude attenuation at the cutoff frequency according to different mixing processes. The filter coefficient COE file is generated in the MATLAB software based on these parameters, and the file is imported into the IP core setting tool of the FPGA design software to generate the filter IP core. The IP core and the entire FPGA project are integrated and implemented using the FPGA design software to obtain the program configuration file, which is finally burned into the working waveform FPGA to implement the setting of these parameters.

[0037] When the waveform generator is powered on, the main control FPGA reads its own program configuration data from FLASH to complete the power-on program loading. After the loading is completed, the program configuration data of the working waveform FPGA is read from FLASH to complete the program loading of the working waveform FPGA. After the waveform generator completes the program loading, it receives the terminal waveform data, waveform form parameters and control information sent by the wave control extension to generate the working waveform.

[0038] When it is necessary to modify the parameters such as the filter order, insertion loss, sampling rate, cutoff frequency and amplitude attenuation at the cutoff frequency of the FIR and CIC filters in the working waveform FPGA, since the FPGA IP core is used in the filter design and these parameters are preset during the design when the IP core is set, it can only be achieved by modifying the working waveform module as a whole, which requires reconfiguring the working waveform FPGA. The wave control extension sends the working waveform FPGA program configuration data containing the new waveform parameters to the main control FPGA, and the data processing module of the main control FPGA decodes and completes the reconfiguration process of the working waveform FPGA through the program loading module. At the same time, the wave control extension sends instructions to control the data selection module to switch to the temporary waveform DAC data channel to replace the working waveform DAC data, and sends delay data to correct the delay parameters of the working waveform channel. After the main control FPGA waits for the working waveform FPGA to be reconfigured and the working waveform is generated normally, it reports the current status to the wave control extension. After confirmation and feedback of the instruction, it controls the data selection module to switch to the working waveform DAC data channel to complete the reconstruction of the waveform module. The delay data of two channels needs to be sent through the waveform extension, and the delay correction is completed in the channel delay correction module of the data selection module.

[0039] A method for real-time online reconstruction of a digital filter inside a waveform generator of the present invention comprises the following steps:

[0040] Step 1: Store the working waveform module in the radar waveform generator separately in a working waveform FPGA of the waveform generator, and implement other functional modules by another master FPGA. Generate different FPGA filter IP cores in advance according to the filter parameters corresponding to different waveforms required by the working waveform module, and generate multiple program configuration files together with the FPGA project of the entire working waveform module, and store them in the waveform control extension;

[0041] Step 11: Calculate the corresponding filter parameters in advance according to the various waveforms required for work, and use MATLAB to generate the corresponding filter coefficient COE file according to these filter parameters;

[0042] Step 12: Import the COE file generated in step 11 into the IP core setting tool of the FPGA design software to generate the filter IP core, and use the FPGA design software to synthesize the IP core and the entire FPGA project to obtain the program configuration file;

[0043] Step 13: Store the program configuration file generated in step 12 in the wave control extension according to the corresponding different waveforms;

[0044] Step 2: According to the waveform that needs to be switched, the wave control extension sends the filter reconstruction instruction and sends the program configuration file corresponding to the filter to the DDR3 of the main control FPGA;

[0045] Step 3: According to the filter reconstruction instruction, the main control FPGA replaces the working waveform module with its own temporary waveform module to prevent the radar waveform from being interrupted, and corrects the delay parameters of different channels, and then reads the working waveform module program configuration data in DDR3 to update the working waveform FPGA program;

[0046] Step 4: After the working waveform FPGA program is updated and the working waveform is regenerated, the main control FPGA replaces the temporary waveform with the working waveform to complete the filter reconstruction.

[0047] The present invention uses a master control FPGA to receive the filter reconstruction instruction and the working waveform FPGA program configuration file corresponding to the filter under the wave control extension. When the working waveform FPGA program configuration file is loaded online, the present invention uses the master control FPGA to generate a temporary waveform to replace the working waveform, and then switches to the working waveform after the loading is completed, so as to complete the reconstruction of the digital filter inside the waveform generator without interrupting the work. When switching waveforms, the present invention will correct the waveforms output by different FPGAs to have the same time delay so that switching channels will not affect the work. When loading the program, the present invention will also store the program configuration data in the FLASH chip to achieve automatic loading when power is turned on.

Claims

1. A method for real-time online reconstruction of a digital filter inside a waveform generator, characterized in that: The following steps are involved: Step 1: Store the working waveform module in the radar waveform generator separately in a working waveform FPGA of the waveform generator, generate different FPGA filter IP cores in advance according to the filter parameters corresponding to different waveforms required by the working waveform module, and generate multiple program configuration files together with the FPGA project of the entire working waveform module, and store them in the wave control extension; Step 2: According to the waveform that needs to be switched, the wave control extension sends the filter reconstruction instruction and sends the program configuration file corresponding to the filter to the DDR3 of the main control FPGA; Step 3: According to the filter reconstruction instruction, the main control FPGA replaces the working waveform module with its own temporary waveform module to prevent the radar waveform from being interrupted, and corrects the delay parameters of different channels, and then reads the working waveform module program configuration data in DDR3 to update the working waveform FPGA program; Step 4: After the working waveform FPGA program is updated and the working waveform is regenerated, the main control FPGA replaces the temporary waveform with the working waveform to complete the filter reconstruction.

2. The method for real-time online reconstruction of a digital filter inside a waveform generator according to claim 1, characterized in that: The specific steps of step 1 are: Step 11: Calculate the corresponding filter parameters in advance according to the various waveforms required for work, and use MATLAB to generate the corresponding filter coefficient COE file according to these filter parameters; Step 12: Import the COE file generated in step 11 into the IP core setting tool of the FPGA design software to generate the filter IP core, and use the FPGA design software to synthesize the IP core and the entire FPGA project to obtain the program configuration file; Step 13: Store the program configuration file generated in step 12 in the wave control extension according to the corresponding different waveforms.

3. A device for real-time online reconstruction of a digital filter inside a waveform generator, characterized in that: It includes a wave control extension and a waveform generator, wherein the waveform generator includes an optoelectronic conversion module, a main control FPGA, a working waveform FPGA, DDR3, FLASH and a D / A conversion module, and the wave control extension includes a computer with a human-machine interface and an optoelectronic adapter board. The optoelectronic conversion module is used to send and receive wave control optical signals and perform data transmission between the wave control extension and the main control FPGA. The main control FPGA is used to receive and process the data from the wave control extension, control the configuration of the working waveform FPGA, and generate temporary waveforms; Working waveform FPGA is used to generate working waveform; DDR3 is used to store the demodulated waveform data and program configuration data sent by the wave control extension; FLASH is used to store the program configuration data of the main control FPGA and the working waveform FPGA; The main control FPGA includes a data processing module, a temporary waveform module and a data selection module; The temporary waveform module includes NCO mixing, FIR and CIC filters, and waveform form control. NCO mixing generates point frequency data through the digital control oscillator IP core and mixes with the waveform to complete frequency adjustment. FIR and CIC filters perform interpolation filtering on the mixing data to filter out the image frequency generated by the mixing, and adjust the data rate of the mixing data to be consistent with the temporary waveform DAC data. The working waveform module loaded inside the working waveform FPGA is consistent with the temporary waveform module. The FIR and CIC filters in the working waveform FPGA set the filter order, insertion loss, sampling rate, cutoff frequency and amplitude attenuation at the cutoff frequency according to different mixing processes. The filter coefficient COE file is generated according to these parameters in the MATLAB software. The file is imported into the IP core setting tool of the FPGA design software to generate the filter IP core, and the FPGA design software is used to integrate the IP core and the entire FPGA project to obtain the program configuration file, which is finally burned into the working waveform FPGA to implement the setting of these parameters.

4. The device for real-time online reconstruction of the internal digital filter of a waveform generator according to claim 3, characterized in that: The data processing module includes a data encoding and decoding module, a control instruction operation module, a data reading and writing module, a program loading module, and a monitoring and reporting module; the data encoding and decoding module includes encoding and decoding functions. When decoding, the waveform data, waveform form parameters, program configuration data, delay data and control information are decoded through the frame header and command control word according to the custom communication protocol, and the reporting status and reporting parameters are packaged and uploaded during encoding; the control instruction operation module completes various required tasks according to the decoded control information; the data reading and writing module caches the decoded data into DDR3 and the main control FPGA, and when outputting the waveform, the waveform data is read from the external DDR3 and sent to the temporary waveform module and the working waveform module together with the control information. When reconfiguring the working waveform FPGA, the program configuration data is read from the external DDR3 and sent to the program loading module; The program loading module is used to operate the program loading process of the working waveform FPGA; The monitoring and reporting module is used to detect the state of the waveform generator, and report the state and feedback some parameters.

5. The device for real-time online reconstruction of the internal digital filter of a waveform generator according to claim 3, characterized in that: The data selection module includes a channel delay correction module and a waveform channel switching module; the channel delay correction module completes the delay correction of the temporary waveform channel and the working waveform channel; the waveform channel switching module completes the channel switching.

6. The device for real-time online reconstruction of the internal digital filter of a waveform generator according to claim 3, characterized in that: When the waveform generator is powered on, the main control FPGA reads its own program configuration data from FLASH to complete the power-on program loading. After the loading is completed, the program configuration data of the working waveform FPGA is read from FLASH to complete the program loading of the working waveform FPGA. After the waveform generator completes the program loading, it receives the terminal waveform data, waveform form parameters and control information sent by the wave control extension to generate the working waveform.

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