Six-stage pipeline CPU based on RISC-V instruction set

Abstract

The invention discloses a six-stage pipeline CPU based on RISC-V instruction set, which can implement RV32I basic instruction set, multiplication instruction, CSR read and write instruction, and set interrupt register to suspend pipeline; the remarkable feature of CPU is that it has six-stage pipeline structure, namely IF level, FD level, CSG level, EXE level, MEM level, WB level, with higher main frequency; relevant circuits are designed to solve the risk problems in pipeline; data risk is solved by internal forward push, load_use risk is solved by suspending pipeline, and control risk is solved by static prediction. The CPU has the characteristics of small area, low power consumption and multi-function, and can be widely used in the field of Internet of Things and embedded system.

Description

Technical Field

[0001] The present invention belongs to the field of processor design, and in particular is a six-stage pipeline CPU based on a RISC-V instruction set. Background Art

[0002] RISC-V ISA is an open instruction set architecture completed by a team from the University of California, Berkeley. RISC stands for Reduced Instruction Set Computer and V stands for the fifth generation, so this architecture is built on the principle of reduced instruction set computing. Compared with most instruction sets, the RISC-V instruction set is completely free and open source, allowing anyone to design, manufacture and sell chips and software based on the RISC-V instruction set. Today, microprocessors based on the RISC-V instruction set are widely used in IoT terminals due to their low power consumption and open source advantages.

[0003] There are many studies on the RISC-V instruction set abroad, and a variety of open source RISC-V processors have been designed and widely used. For the design of RISC-V processors in China, we have to mention the Hummingbird E203, which is the first fully open source low-power processor based on the RISC-V instruction set in China. Based on the design goal of ultra-low power embedded applications, the designer Hu Zhenbo and others adopted a pipeline structure with a two-stage sequential pipeline as the main body and other components with variable pipeline lengths, taking into account the compromise requirements of power consumption and performance. Finally, by running the running program test and comparing it with the ARM Cortex-M microcontroller, the comparison results show that this work can also be applied to low-power scenarios of IoT. In addition, many research teams have designed a variety of microprocessors based on the RISC-V instruction set, including out-of-order execution processors, floating-point processors, and dedicated metering processors.

[0004] Although there are many kinds of domestic processors, the division of pipeline levels is not detailed enough, which greatly affects the execution efficiency of the CPU, and the CPU's main frequency and instruction throughput will be greatly reduced. For example, the popular domestic Hummingbird E203 processor has only a two-stage pipeline structure, which makes the CPU's main frequency and throughput low. Therefore, in order to obtain a higher main frequency and higher instruction throughput, the CPU with a multi-stage pipeline structure has become the focus of research. Summary of the invention

[0005] The object of the present invention is to provide a six-stage pipeline CPU based on the RISC-V instruction set.

[0006] The technical solution to achieve the purpose of the present invention is: a six-stage pipeline CPU based on the RISC-V instruction set, comprising:

[0007] Instruction fetching circuit, used to generate the next instruction address and fetch the instruction of the current address;

[0008] A field decoding circuit, used to decode instruction fields and detect load_use hazards;

[0009] A control signal generating circuit, used for generating a control signal of an instruction and reading a general register according to the rs1 and rs2 field addresses;

[0010] Instruction execution circuit, used to perform instruction operations and resolve data hazards and control hazards;

[0011] Memory access circuit, used to access memory, mainly for load and store instructions;

[0012] The result write-back circuit is used to write the data result into the register file, read and write the CSR register, and generate an interrupt signal.

[0013] Compared with the prior art, the present invention has the following significant advantages:

[0014] (1) It has a six-stage pipeline structure, and the division of each stage of the circuit is more detailed, so the execution time of each stage of the circuit is greatly reduced, and the CPU main frequency will be greatly improved;

[0015] (2) 20CPU has higher execution efficiency and higher instruction throughput, and can execute more instructions at the same time compared to other processors;

[0016] (3) Static prediction structure is used to solve control risks. The circuit is simple and easy to control.

[0017] The present invention is further described in detail below in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the circuit diagram of the pipeline IF stage.

[0019] Figure 2 This is the circuit diagram of the pipeline FD stage.

[0020] Figure 3 This is the pipeline CSG level circuit diagram.

[0021] Figure 4 This is the pipeline EXE level circuit diagram.

[0022] Figure 5 This is the WB stage circuit diagram of the pipeline.

[0023] Figure 6 This is the circuit diagram of a six-stage pipeline CPU.

[0024] Figure 7 This is the circuit diagram of the first three stages of the pipeline CPU.

[0025] Figure 8 This is the circuit diagram of the last three stages of the pipeline CPU. DETAILED DESCRIPTION

[0026] A six-stage pipeline CPU based on the RISC-V instruction set is divided into a six-stage pipeline structure, namely, instruction fetch (IF) level, field decoding (FD) level, control signal generation (CSG) level, instruction execution (EXE) level, memory access (MEM) level, and result write back (WB) level.

[0027] The instruction fetches the IF level circuit, generates the next instruction address and fetches the instruction of the current address;

[0028] The field decoding FD level circuit decodes the instruction field and detects load_use hazards;

[0029] The control signal generating CSG level circuit generates a control signal for the instruction and reads a general register according to the rs1 and rs2 field addresses;

[0030] The instruction executes the EXE level circuit, performs the instruction operation, and solves the data hazard and the control hazard;

[0031] The memory access MEM level circuit accesses the memory, mainly for load and store instructions;

[0032] The result is written back to the WB level circuit, the data result is written into the register file, the CSR register is read and written, and an interrupt signal is generated.

[0033] Further, the IF stage circuit comprises:

[0034] Instruction address generation module: the current pc and jump pc are both added with 4 and input to the data selector imux1. The pc_sel generation module generates the control signal pc_sel of imux1, and imux1 outputs the next instruction address to the pc counter.

[0035] Instruction fetch module: a selector imux2, selects the appropriate address as the ITCM address input, and the instruction memory ITCM stores program instructions;

[0036] PC buffer: As the inter-segment register between the IF level and the FD level, it outputs the PC value of the IF level to the next FD level.

[0037] Furthermore, the FD stage circuit includes:

[0038] Instruction output module: select cached instructions or current instructions for the decoding module to use. When a load_use risk occurs and a pause is required, the cached instructions are output. If there is no risk, the output instructions of ITCM are directly used.

[0039] Decoding module: receives the instruction signal from the instruction module and performs field decoding, and outputs the decoding signal; load_use detection unit: detects load_use hazards and outputs the stall signal and the discard signal. The stall signal pauses the IF level and FD level, and the discard signal discards the CSG level instruction.

[0040] Furthermore, the CSG-level circuit includes:

[0041] Register reading module: The two register reading modules output register reading signals rf_rs1 and rf_rs2 according to the decoding signals crs1 and crs2 transmitted from the FD stage and the register stack related signals transmitted from the WB stage.

[0042] Control component module: Generates five control signals according to the instruction operation code opcode, and outputs them to the inter-segment register CSG / EXE reg, which flows into the EXE level in the next clock cycle.

[0043] Further, the EXE level circuit includes:

[0044] Push-forward circuit: It consists of two selectors and a bypass detection unit. The bypass detection unit determines the occurrence of data hazards based on the relevant signals returned by the WB level and the MEM level, and outputs the control signals of the two selectors. The data selector selects different data outputs based on the control signal. The bypass detection unit detects data hazards, and the data hazards occurring with the MEM level are called MEM-level hazards, and the data hazards occurring with the WB level are called WB-level hazards. The conditions for the occurrence of MEM-level data hazards are as follows: the MEM-level instruction has the function of writing to the register stack, and the destination address is equal to the source address of the EXE-level instruction (not zero). The conditions for the occurrence of WB-level data hazards are as follows: the WB-level instruction has the function of writing to the register stack, and the destination address is equal to the source address of the EXE-level instruction (not zero).

[0045] ALU component: performs instruction calculations, selects different operations according to different instructions, and outputs the calculation results to the next level.

[0046] Static prediction circuit: Determine the jump address and jump execution at the EXE level, where the jump address generation module generates the jump address pc_jump, and the jump_en generation module generates the jump execution signal jump_en, and delays the two signals to the next level. At the MEM level, the jump address signal and the jump execution signal are transmitted to the IF level, so that the IF level fetches instructions according to the jump address. At this time, the three instructions following the jump instruction have entered the pipeline, and these three instructions need to be discarded. To discard an instruction, you only need to clear the control signal of the instruction to prevent the instruction from rewriting the CPU state and achieve the purpose of discarding it. Clearing the control signal requires three steps: bit splicing, judgment, and operation.

[0047] Furthermore, the MEM-level circuit includes:

[0048] Data memory: Data memory DTCM stores data used by load and lw instructions.

[0049] Furthermore, the WB-level circuit includes:

[0050] Register file: 32 general-purpose integer registers.

[0051] Interrupt register minterrupt: register address 0x000, minterrupt outputs interrupt signal intr_done to the control end of the PC counter, so that the output of the PC counter remains unchanged, thereby achieving the purpose of pausing the pipeline.

[0052] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0053] Example

[0054] See the attached pipeline IF stage circuit Figure 1 , which consists of an instruction address generation module, an instruction fetch module, and a pc cache module. The working process of the IF level circuit is as follows: In the instruction address generation module, the current pc and the jump pc are both added with 4 and input to the data selector imux1, the pc_sel generation module generates the control signal pc_sel of imux1, and imux1 outputs the next instruction address to the PC counter. In the instruction fetch module, the selector imux2 selects the appropriate address as the ITCM address input, and ITCM outputs instructions based on the input address. The PC cache can also be used as an inter-segment register between the IF level and the FD level, outputting the PC value of the IF level to the next level FD level.

[0055] See the attached pipeline FD stage circuit Figure 2, which consists of a load_use detection unit, an instruction output module, and a decoding module. The FD level circuit workflow is as follows: the load_use detection unit detects load_use hazards and outputs a stall signal and a discard signal. The stall signal pauses the IF level and FD level, and the discard signal discards the CSG level instruction. The instruction output module selects appropriate instructions for the decoding module to use. When a load_use hazard occurs and a pause is required, the cache instruction is output. If there is no hazard, the output instruction of the ITCM is directly used. The decoding module receives the instruction signal from the instruction module and performs field decoding, outputs the decoding signal, and writes it into the inter-segment register FD / CFP reg at the end of the cycle (at the rising edge of the clock).

[0056] See the attached pipeline CSG level circuit Figure 3 , which consists of rs1 register read module, rs2 register read module and control unit. The CSG level circuit workflow is as follows: the two register read modules output register read signals rf_rs1 and rf_rs2 according to the decoding signals crs1 and crs2 from the FD level and the register stack related signals from the WB level; the control unit generates five control signals according to the instruction operation code opcode, namely register stack write signal, memory read and write signal, ALU calculation signal, CSR read and write instruction signal, WB level data selection signal, and outputs them to the inter-segment register CSG / EXE reg.

[0057] See the attached pipeline EXE level circuit Figure 4 , which consists of a push-forward circuit, a static prediction circuit, and an ALU calculation circuit. The working process of the EXE-level circuit is as follows: the push-forward circuit detects data hazards through the bypass detection unit, and outputs appropriate data as the source operand of the ALU component according to the detection result; the ALU performs instruction operations, selects different operations according to different instructions, and outputs the operation results to the next level; the static prediction circuit solves the control hazard, and when the hazard occurs, the control signal of the instruction at this level is cleared; in addition, the CSR module generates CSR register-related signals.

[0058] The forward push circuit consists of two selectors and a bypass detection unit. The bypass detection unit determines the occurrence of data hazards based on the relevant signals returned by the WB level and the MEM level, and outputs control signals for the two selectors. The data selector selects different data outputs based on the control signals.

[0059] The bypass detection unit detects data hazards. Data hazards occurring at the MEM level are called MEM-level hazards, and data hazards occurring at the WB level are called WB-level hazards.

[0060] The two data selectors are muxa and muxb. muxa selects the input data of ALU port a, and directly selects the rs1 register to read the content when there is no data hazard. muxb selects the input data of ALU port b, and directly selects the rs2 register to read the content when there is no data hazard.

[0061] The static prediction circuit determines the jump address and jump execution at the EXE level, where the jump address generation module generates the jump address pc_jump, and the jump_en generation module generates the jump execution signal jump_en, delaying the two signals to the next level. At the MEM level, the jump address signal and the jump execution signal are transmitted to the IF level, so that the IF level fetches instructions according to the jump address. At this time, the three instructions following the jump instruction have entered the pipeline, and these three instructions need to be discarded. To discard an instruction, you only need to clear the control signal of the instruction to prevent the instruction from rewriting the CPU state and achieve the purpose of discarding it. Clearing the control signal requires three steps: bit splicing, judgment, and operation.

[0062] The pipeline MEM-level circuit is composed of a data register DTCM to implement access to the data memory.

[0063] See attached for the pipeline WB stage circuit Figure 5 , which consists of a register stack write module and an interrupt register write module. For the interrupt register write module, if it is a CSR read / write instruction, the read / write address is 0x000, the minterrupt interrupt register will be written, and the interrupt signal intr_done will be output to pause the pipeline.

[0064] The register file write module is composed of a register file, a data selector, and a regfile_en generation module. The data selector selects appropriate data as the write data of the register file, and the regfile_en generation module generates a control signal for the register file. The register file writes the data at the end of the cycle (at the rising edge of the clock).

[0065] The two two-choice data selectors are wmux1 and wmux2. The control signal aluormem_sel is used as the selection signal of wmux1, the control signal wcsr_wr is used as the selection signal of wmux2, and the output wmux2_out of the wmux2 selector is used as the write data of the register file. The regfile_en generation module outputs the enable signal regfile_en of the register file according to the destination address wrd of the instruction and the control signal wregfile_wr. The register file writes data at the rising edge of the clock and outputs the value of each register.

[0066] The overall circuit of the pipeline CPU is attached. Figure 6 , 7 , 8, including Figure 7It is the first three circuits, attached Figure 8 It is the last three levels of circuits. Each level of circuit performs different functions and outputs related signals to the next level through the intersegment register. The intersegment register connects each level of circuits in sequence, making the execution of instructions orderly and efficient. The entire pipeline CPU workflow is as follows: the IF level fetches instructions and outputs the address of the next instruction; the FD level decodes the instruction field and outputs it to the next level; the CSG level generates the control signal of the instruction based on the decoding signal, and the control signal affects the operation of the subsequent circuit components; the EXE level completes the calculation task of the instruction based on the decoding and control signals; the MEM level completes the instruction's access to the memory; the WB level writes the previous calculation result or reading result of the instruction into the register stack. In addition, the addition of data hazard processing circuits and control hazard processing circuits effectively solves the occurrence of hazards. It can be seen that the pipeline divides the execution content of the instruction in detail, and the front and back are closely related, ensuring the efficient execution of the CPU.

[0067] When the pipeline is full of instructions, at each rising edge of the clock, the WB stage completes the execution of the instructions and the IF stage inputs new instructions. At the same time, six instructions are being processed in the pipeline, and the CPU execution speed is greatly improved.

[0068] It should be pointed out that ordinary technicians in this technical field can make several improvements and equivalent substitutions without departing from the principles of the present invention. These technical solutions after improvements and equivalent substitutions to the claims of the present invention all fall within the protection scope of the present invention.

Claims

1. A six-stage pipeline CPU based on the RISC-V instruction set, characterized in that: include: Instruction fetching circuit, used to generate the next instruction address and fetch the instruction of the current address; A field decoding circuit, used to decode instruction fields and detect load_use hazards; A control signal generating circuit, used for generating a control signal of an instruction and reading a general register according to the rs1 and rs2 field addresses; Instruction execution circuit, used to perform instruction operations and resolve data hazards and control hazards; Memory access circuit, used to access memory, mainly for load and store instructions; The result write-back circuit is used to write the data result into the register file, read and write the CSR register, and generate an interrupt signal.

2. The six-stage pipeline CPU based on the RISC-V instruction set according to claim 1, characterized in that: The instruction fetching circuit comprises: Instruction address generation module: the current pc and jump pc are both added with 4 and input to the data selector imux1. The pc_sel generation module generates the control signal pc_sel of imux1, and imux1 outputs the next instruction address to the pc counter. Instruction fetch module: uses a selector imux2 to select the appropriate address as the ITCM address input. The instruction memory ITCM stores program instructions. PC buffer: As an inter-segment register between the instruction fetch circuit and the field decoding circuit, it outputs the PC value of the instruction fetch circuit to the next-level field decoding circuit.

3. The six-stage pipeline CPU based on the RISC-V instruction set according to claim 2, characterized in that: The field decoding circuit comprises: Instruction output module: select cached instructions or current instructions for the decoding module to use. When a load_use risk occurs and a pause is required, the cached instructions are output. If there is no risk, the output instructions of ITCM are directly used. Decoding module: receives the command signal from the command module, performs field decoding, and outputs the decoding signal; load_use detection unit: detects load_use hazards and outputs a stall signal and a discard signal. The stall signal pauses the instruction fetching circuit and the field decoding circuit, and the discard signal discards the control signal generation circuit instruction.

4. The six-stage pipeline CPU based on the RISC-V instruction set according to claim 3, characterized in that: The control signal generating circuit comprises: Register reading module: two register reading modules output register reading signals rf_rs1 and rf_rs2 according to the decoding signals crs1 and crs2 transmitted from the field decoding circuit and the register stack related signals transmitted from the WB level; Control component module: Generates five control signals according to the instruction operation code opcode, and outputs them to the inter-segment register CSG / EXEreg, which flows into the instruction execution circuit in the next clock cycle.

5. The six-stage pipeline CPU based on the RISC-V instruction set according to claim 4, characterized in that: The instruction execution circuit comprises: Forward circuit: It consists of two selectors and a bypass detection unit. The bypass detection unit determines the occurrence of data hazards based on the relevant signals returned by the result write-back circuit and the memory access circuit, and outputs control signals for the two selectors. The selectors select different data outputs based on the control signals. The bypass detection unit detects data hazards, and the data hazards occurring with the memory access circuit are called MEM-level hazards, and the data hazards occurring with the result write-back circuit are called WB-level hazards. ALU unit: performs instruction calculations, selects different operations according to different instructions, and outputs the calculation results to the next level; Static prediction circuit: determine the jump address and jump execution in the instruction execution circuit, where the jump address generation module generates the jump address pc_jump, and the jump_en generation module generates the jump execution signal jump_en, and delays the two signals to the next level; in the memory access circuit, the jump address signal and the jump execution signal are transmitted to the instruction fetch circuit, so that the instruction fetch circuit fetches instructions according to the jump address; at this time, the three instructions following the jump instruction have entered the pipeline, and these three instructions need to be discarded; the discarding of the instruction only requires clearing the control signal of the instruction to prevent the instruction from rewriting the CPU state; clearing the control signal requires three steps: bit splicing, judgment, and operation.

6. The six-stage pipeline CPU based on the RISC-V instruction set according to claim 1, characterized in that: The memory access circuit comprises: Data memory: Data memory DTCM stores data used by load and lw instructions.

7. The six-stage pipeline CPU based on the RISC-V instruction set according to claim 1, characterized in that: The result writing back circuit comprises: Register file: 32 general-purpose integer registers; Interrupt register minterrupt: register address 0x000, minterrupt outputs interrupt signal intr_done to the control end of the pc counter, so that the output of the pc counter remains unchanged, thereby pausing the pipeline.

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