Method, device and simulation verification method for generating array device simulation netlist

Abstract

The present invention belongs to the technical field of arrayed devices, and discloses a method, device and simulation verification method for generating a simulation netlist of an arrayed device. The generation method includes: selecting a basic unit module in the arrayed device as the origin of the coordinate system, establishing a two-dimensional coordinate system to mark the coordinates of all modules, using the coordinate mark of the basic unit module as the instantiation name of the basic unit module, using the coordinate mark of the non-basic unit module and the name of the non-basic unit module as the instantiation name, obtaining a Verilog hardware netlist, and filtering the Verilog hardware netlist according to a preset resource log to retain the modules whose instantiation names are recorded in the resource log, and obtaining a first netlist corresponding to the simulation case. Beneficial effect: The simulation netlist generation method of the present invention can effectively reduce the scale of the netlist in the simulation process, thereby greatly reducing the compilation time and the required storage space in the simulation verification process, and greatly improving the efficiency of simulation verification.

Description

Technical Field

[0001] The present invention relates to the technical field of arrayed devices, and in particular to a method and device for generating a simulation netlist of an arrayed device, and a simulation verification method. Background Art

[0002] With the continuous upgrading of micro-nano process technology nodes, the scale of various chips is gradually developing towards higher integration, greater density, and smaller basic unit. However, as the scale increases, it becomes more difficult to verify the correctness of its internal functions, especially for array devices that have strong correlations with each other, such as FPGA, DSP, SOC+FPGA / DSP and other general-purpose chips. At the scale of tens of millions or even hundreds of millions of gates, the verification of its correctness is particularly difficult.

[0003] In the existing verification process, since the netlist of the chip itself is very large, it will expand by one to two orders of magnitude after compilation, occupying a lot of storage space. A large amount of storage space is required for storage. At the same time, the waveform files generated by the simulation after compilation occupy a lot of storage space and the processing speed is slow. According to the verification method of the prior art, it takes at least three hours to compile once and at least one and a half hours to simulate once, which seriously reduces the verification efficiency.

[0004] Therefore, it is necessary to improve the verification method in the prior art, reduce the information storage requirements during the verification process, increase the speed of compilation and verification, and improve the efficiency of correctness verification. Summary of the invention

[0005] The purpose of the present invention is to improve the verification method in the prior art, reduce the information storage requirements during the verification process, increase the speed of compilation and verification, and improve the efficiency of correctness verification.

[0006] In order to achieve the above object, the present invention provides a method for generating a simulation netlist of an arrayed device, comprising:

[0007] A basic unit module in the arrayed device is selected as the origin of the coordinate system, and the coordinates of all remaining basic unit modules are marked with the origin of the coordinate system to obtain the coordinates of all basic unit modules; the arrayed device includes basic unit modules and non-basic unit modules, and the basic unit module is the module with the most arraying times and the smallest physical area in the arrayed device.

[0008] The coordinates of the adjacent non-basic unit modules are marked according to the coordinate marks of the basic unit modules. Any non-basic unit module must be adjacent to at least one non-basic unit module.

[0009] The coordinate mark of the basic unit module is used as the instantiation name of the basic unit module, and the coordinate mark of the non-basic unit module and the name of the non-basic unit module are used as the instantiation name to obtain a Verilog hardware netlist.

[0010] The Verilog hardware netlist is screened according to a preset resource log to retain the modules whose instantiation names are recorded in the resource log, and a first netlist corresponding to the simulation case is obtained, wherein the resource log is compiled according to the simulation case.

[0011] Furthermore, the basic unit module is an array module, and the non-basic unit module includes: an IP module and an IO module.

[0012] Furthermore, the selection of a basic unit module in the arrayed device as the origin of the coordinate system is specifically:

[0013] It is determined whether the modules at the four corners of the arrayed device are basic unit modules. If a module at one of the four corners is a basic unit module, the basic unit module at the corner is used as the origin of the coordinate system.

[0014] If the modules in the four corners are all non-basic unit modules, the first basic unit module on the left or right side of the non-basic unit module in the corner is used as the origin of the coordinate system.

[0015] Furthermore, the coordinates of all remaining basic unit modules are marked with the origin of the coordinate system, specifically:

[0016] The origin of the coordinate system is denoted as x0y0; in the horizontal direction, the x-coordinates of the basic unit modules on the right side of the origin of the coordinate system increase, and the x-coordinates of the basic unit modules on the left side of the origin of the coordinate system decrease; in the vertical direction, the y-coordinates of the basic unit modules on the upper side of the origin of the coordinate system increase, and the y-coordinates of the basic unit modules on the lower side of the origin of the coordinate system decrease.

[0017] Furthermore, the coordinate marking of the adjacent non-basic unit modules according to the coordinate marking of the basic unit modules is specifically as follows:

[0018] When a non-basic unit module is adjacent to multiple basic unit modules, the coordinate mark of the basic unit module at the lower left corner of the non-basic unit module is used as the coordinate mark of the non-basic unit module.

[0019] If there is no basic unit module at the lower left corner of the non-basic unit module, the coordinate mark of the basic unit module at the lower right corner of the non-basic unit module is used as the coordinate mark of the non-basic unit module.

[0020] Furthermore, the resource log is compiled according to the simulation case, specifically:

[0021] A plurality of simulation cases are written according to the verification requirements, and each simulation case can correspond to a single preset function.

[0022] The prepared multiple simulation cases are input into the software for compilation. After the software is compiled, resource selection is performed and a resource list of the required devices is generated. The resource names in the resource list match the instantiation names in the Verilog hardware netlist.

[0023] Generate resource logs based on resource lists.

[0024] Further, the Verilog hardware netlist is screened according to the preset resource log to retain the modules whose instantiation names are recorded in the resource log, and a first netlist corresponding to the simulation case is obtained, which is specifically:

[0025] Get the instantiation name of the required module from the resource log.

[0026] Traverse each instantiation name of the Verilog hardware netlist and determine whether the instantiation name is in the resource log. If so, retain the module corresponding to the instantiation name; if not, delete the module corresponding to the instantiation name.

[0027] After the traversal is completed, the first netlist uniquely corresponding to the simulation case is generated.

[0028] The present invention also discloses a device for generating a simulation netlist of an arrayed device, comprising: a first coordinate marking module, a second coordinate marking module, an instantiation name module, and a netlist generating module.

[0029] The first coordinate marking module is used to select a basic unit module in the arrayed device as the origin of the coordinate system, and mark the coordinates of all remaining basic unit modules with the origin of the coordinate system to obtain the coordinates of all basic unit modules; the arrayed device includes basic unit modules and non-basic unit modules, and the basic unit module is the module with the most arraying times and the smallest physical area in the arrayed device.

[0030] The second coordinate marking module is used to mark the coordinates of adjacent non-basic unit modules according to the coordinate markings of the basic unit modules. Any non-basic unit module must be adjacent to at least one non-basic unit module.

[0031] The instantiation name module is used to use the coordinate mark of the basic unit module as the instantiation name of the basic unit module, and use the coordinate mark of the non-basic unit module and the name of the non-basic unit module as the instantiation name to obtain a Verilog hardware netlist.

[0032] The netlist generation module is used to filter the Verilog hardware netlist according to a preset resource log, retain the module whose instantiation name is recorded in the resource log, and obtain a first netlist corresponding to the simulation case. The resource log is compiled according to the simulation case.

[0033] Furthermore, the basic unit module is an array module, and the non-basic unit module includes: an IP module and an IO module.

[0034] The present invention also discloses a simulation verification method for arrayed devices, which uses the first netlist to recompile and perform simulation verification.

[0035] Compared with the prior art, the method, device and simulation verification method for generating a simulation netlist for an arrayed device in an embodiment of the present invention have the beneficial effect that the application of the simulation netlist generation method of the present invention can effectively reduce the size of the netlist in the simulation process, thereby greatly reducing the compilation time and the required storage space in the simulation verification process, and greatly improving the efficiency of simulation verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a flow chart of a method for generating a simulation netlist of an arrayed device according to the present invention;

[0037] Figure 2 It is a schematic diagram of an implementation method of establishing a two-dimensional coordinate system for an array device of the present invention;

[0038] Figure 3 is a schematic diagram of a process of obtaining a first netlist according to a simulation case in the present invention;

[0039] Figure 4 It is a schematic diagram of an implementation method of a resource log of the present invention;

[0040] Figure 5 is a schematic diagram of an implementation of a first netlist of the present invention;

[0041] Figure 6 It is a comparison diagram of the effects of applying the simulation verification method of the present invention and the verification method of the prior art;

[0042] Figure 7 The present invention is a schematic diagram of the structure of a device for generating a simulation netlist of an arrayed device. DETAILED DESCRIPTION

[0043] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0044] Explain the English abbreviations that appear in this application: FPGA (Field Programmable Gate Array) Field Programmable Gate Array; DSP (Digital Signal Processor) Digital Signal Processor; SOC (System On Chip) System on Chip; IP core (Intellectual Property core); IO (Input Output) Input and output.

[0045] The technical issues mentioned in the background technology are further explained.

[0046] In this application, the applicant has studied the prior art and found that as the chip size increases, it becomes increasingly difficult to verify the correctness of its internal functions, especially for array devices that have strong correlations with each other, such as FPGA, DSP, SOC+FPGA / DSP and other general-purpose chips. The scale of these chips is often in the tens of millions or even hundreds of millions of gates, and the verification of their correctness is particularly difficult.

[0047] The applicant will use an FPGA device with a logic capacity of 400k as an example for a more detailed description. The problems encountered by the FPGA device with a logic capacity of 400k are:

[0048] 1. The netlist of the chip itself is very large. It only includes the most basic programmable logic units and programmable winding units in the FPGA. The netlist itself is already 900Mb in size (excluding other modules such as input and output (IO) / block memory (BRAM) / digital signal processor (DSP) / clock network (Clock Tree)).

[0049] 2. A chain reaction caused by 1 is that the database is extremely large after compilation, close to 30Gb.

[0050] 3. The chain problem caused by 2 is that each time the waveform simulated after compilation is used, even if the detailed waveform inside any module is not loaded (dumped), the waveform file will be nearly 5Gb in size.

[0051] 4. The problem caused by 3 is that when the number of dumped modules is relatively small, the time to open a signal waveform is 5 minutes; when the number of dumped modules is relatively large, the time to open a signal is much longer than 10 minutes.

[0052] 5. The problems mentioned in 1-4 above will cause each compilation to take at least 3 hours and the simulation to take 1.5 hours.

[0053] Due to the many objective problems mentioned above, other problems will arise during the entire chip verification, including:

[0054] 1. There is not enough memory space to store netlists / compiled files / waveform files under different simulation cases; if they are forced to be stored, it will greatly waste precious storage resources.

[0055] 2. When the simulation case is not verified once, or the design is modified, the case must be re-run to ensure that the design modification or case modification is correct. Each run takes nearly 4.5 hours. When the design is not correct once, the running time may be longer, and far more than 4.5 hours. This is the time cost of modifying once. When there are too many modifications, it may take longer.

[0056] 3. When the number of simulation cases increases, this approach becomes very time-consuming. Assuming that the compiled files can be reused each time, each case simulation will take at least 1.5 hours. When there are many cases, it will be difficult to complete them in a short period of time.

[0057] 4. When the simulation case only uses some of the resources, even if the compilation is completed, it still takes 1.5 hours of simulation time, which is not worth the cost and wastes precious testing time.

[0058] Based on the above problems, it can be seen that the size of the netlist has a direct impact on a series of subsequent problems. If the size of the netlist can be effectively reduced, the efficiency of simulation verification can be fundamentally improved and the data capacity in the simulation verification process can be greatly saved.

[0059] Therefore, in Example 1, the present invention first proposes a method for generating a simulation netlist, which can fundamentally reduce the scale of the simulation netlist, fundamentally improve the simulation efficiency, and reduce the data capacity during the simulation process.

[0060] Embodiment 1:

[0061] like Figure 1 As shown, the present invention discloses a method for generating a simulation netlist of an arrayed device, comprising:

[0062] Step S1, select a basic unit module in the arrayed device as the origin of the coordinate system, mark the coordinates of all remaining basic unit modules with the origin of the coordinate system, and obtain the coordinates of all basic unit modules; the arrayed device includes basic unit modules and non-basic unit modules, and the basic unit module is the module with the most arraying times and the smallest physical area in the arrayed device.

[0063] Step S2: Mark the coordinates of adjacent non-basic unit modules according to the coordinate marks of the basic unit modules. Any non-basic unit module must be adjacent to at least one non-basic unit module.

[0064] Step S3, using the coordinate mark of the basic unit module as the instantiation name of the basic unit module, and using the coordinate mark of the non-basic unit module and the name of the non-basic unit module as the instantiation name, to obtain a Verilog hardware netlist.

[0065] Step S4, screening the Verilog hardware netlist according to a preset resource log to retain the modules whose instantiation names are recorded in the resource log, and obtaining a first netlist corresponding to the simulation case, wherein the resource log is compiled according to the simulation case.

[0066] In order to better understand the technical solution, a basic introduction to array devices is given, refer to Figure 2 The arrayed device is provided with several small modules, including basic unit modules and non-basic unit modules. The basic unit modules are generally the modules with the most array times and the smallest physical area, and the non-basic unit modules are the complement of the basic unit modules.

[0067] In this embodiment, an optional implementation of an array device is provided, wherein the basic unit module is an array module, and the non-basic unit module includes an IP module and an IO module. Those skilled in the art can select corresponding basic unit modules and non-basic unit modules according to the actual array device.

[0068] In this embodiment, it should be emphasized that the length or width of the non-basic unit module is an integer multiple of the length or width of the basic unit module. Therefore, it can be known that the length and width of the IP module and the IO module are integer multiples of the length and width of the array module. Specifically: the length of the IP module is twice that of the array module and the width is three times that of the array module, and the length of the IO module is 1 times that of the array module and the width is twice that of the array module. Those skilled in the art can adjust the size of the non-basic module according to actual needs, including but not limited to the above examples.

[0069] In step S1, a basic unit module in the arrayed device is selected as the origin of the coordinate system, and the coordinates of all remaining basic unit modules are marked with the origin of the coordinate system to obtain the coordinates of all basic unit modules. The arrayed device includes basic unit modules and non-basic unit modules. The basic unit module is the module with the largest number of arraying times and the smallest physical area in the arrayed device.

[0070] In this embodiment, the selection of a basic unit module in the arrayed device as the origin of the coordinate system is specifically:

[0071] Determine whether the modules at the four corners of the arrayed device are basic unit modules. If a module at one of the four corners is a basic unit module, take the basic unit module at the corner as the origin of the coordinate system.

[0072] If the modules in the four corners are all non-basic unit modules, the first basic unit module on the left or right side of the non-basic unit module in the corner is used as the origin of the coordinate system.

[0073] In this embodiment, the modules are converted into two-dimensional coordinates when making the netlist, which is beneficial to the synchronization of software and hardware and is easy to process.

[0074] Establishing a better coordinate system origin can better mark the coordinates of each module in the arrayed device, and can also reduce the complexity of storing data. Therefore, the preferred coordinate system origin should be the basic unit modules at the four corners of the arrayed device. The most preferred one should be the basic unit module at the lower left corner, so that the entire arrayed device falls into the first quadrant of the coordinate system, reducing the complexity of coordinate expression and avoiding the appearance of negative signs.

[0075] In this embodiment, the coordinates of all remaining basic unit modules are marked with the origin of the coordinate system, specifically:

[0076] The origin of the coordinate system is denoted as x0y0; in the horizontal direction, the x-coordinates of the basic unit modules on the right side of the origin of the coordinate system increase, and the x-coordinates of the basic unit modules on the left side of the origin of the coordinate system decrease; in the vertical direction, the y-coordinates of the basic unit modules on the upper side of the origin of the coordinate system increase, and the y-coordinates of the basic unit modules on the lower side of the origin of the coordinate system decrease.

[0077] In step S2, coordinates of adjacent non-basic unit modules are marked according to the coordinates of the basic unit modules. Any non-basic unit module must be adjacent to at least one non-basic unit module.

[0078] In this embodiment, the coordinate marking of the adjacent non-basic unit modules according to the coordinate marking of the basic unit modules is specifically as follows:

[0079] When a non-basic unit module is adjacent to multiple basic unit modules, the coordinate mark of the basic unit module at the lower left corner of the non-basic unit module is used as the coordinate mark of the non-basic unit module;

[0080] If there is no basic unit module at the lower left corner of the non-basic unit module, the coordinate mark of the basic unit module at the lower right corner of the non-basic unit module is used as the coordinate mark of the non-basic unit module.

[0081] In order to better explain step 1 and step 2, Figure 2 The array device is used as an example to illustrate the actual Figure 2In the design of the netlist of the arrayed device, the module with the most array times and the smallest physical area - the array module is taken as the most basic unit, and the length and width of the array module are taken as the minimum coordinate measurement units. The basic unit in the lower left corner of the whole chip except the IO module array is used as the origin of the coordinate system to construct a two-dimensional rectangular coordinate system, and the origin of the coordinate is recorded as x0y0. In the horizontal direction, the x coordinate of each basic unit increases one by one to the right and decreases one by one to the left. In the vertical direction, the coordinates of each basic unit increase one by one upward and decrease one by one downward. In the full chip netlist, regardless of any digital intellectual property core (IP core) / array module / input and output (IO), the coordinate position must be set, and its coordinates are consistent with the array basic unit closest to its lower left corner. In this application, all circuit modules must exist independently, cannot contain basic repeating units, and cannot be combined with modules with other unrelated functions to form a new module that appears in the netlist. When an IP / IO module is at the leftmost side of the chip and there is no array module in the lower left corner, the coordinates of the array module in its lower right corner are the coordinates of the module. Figure 2 Take the IOB module on the left as an example. The closest basic unit is x0y0, so its coordinate is x0y0. Because the height of an IOB occupies the size of 2 basic units, its y coordinate increases by 2 every two basic units. Other modules also follow this rule to select coordinates.

[0082] In step S3, the coordinate mark of the basic unit module is used as the instantiation name of the basic unit module, and the coordinate mark of the non-basic unit module and the name of the non-basic unit module are used as the instantiation name to obtain a Verilog hardware netlist.

[0083] In this embodiment, refer to Figure 2 , the instantiation name of the array module in the netlist is the same as its coordinate name, and the instantiation name of the IP module / IO in the netlist is the module name + "_" + coordinate name, based on which the Verilog hardware netlist is generated. In this embodiment, adding "_" can easily distinguish the name and coordinate name, which is a more preferred technical solution.

[0084] In step S4, the Verilog hardware netlist is screened according to a preset resource log to retain the modules whose instantiation names are recorded in the resource log, and a first netlist corresponding to the simulation case is obtained, wherein the resource log is compiled according to the simulation case.

[0085] In this embodiment, refer to Figure 3 , the resource log is compiled according to the simulation case, specifically:

[0086] Write multiple simulation cases according to the verification requirements, each of which can correspond to a single preset function;

[0087] Input the prepared multiple simulation cases into the software for compilation. After the software is compiled, resource selection is performed and a resource list of the required device is generated. The resource names in the resource list match the instantiation names in the Verilog hardware netlist.

[0088] Generate resource logs based on resource lists.

[0089] In this embodiment, the resource names in the resource list match the instantiation names in the Verilog hardware netlist, specifically: the software directly generates a hardware resource list based on the optimization results of the case, and the names correspond to the instantiation names of the hardware one by one. This processing method can bring the following beneficial effects:

[0090] (1) The software determines whether hardware resources are used, which greatly improves the accuracy of hardware resource operations.

[0091] (2) The resource list generated by the software has the same name as the hardware instantiation, which greatly improves the correctness and rationality of the operation.

[0092] (3) Using software to operate can greatly improve the flexibility of netlist operations.

[0093] In this embodiment, refer to Figure 4 , Figure 4 A schematic diagram of an implementation of a resource log.

[0094] In this embodiment, refer to Figure 3 , the Verilog hardware netlist is screened according to the preset resource log to retain the modules whose instantiation names are recorded in the resource log, and a first netlist corresponding to the simulation case is obtained, specifically:

[0095] Get the instantiation name of the required module based on the resource log;

[0096] Traverse each instantiation name of the Verilog hardware netlist and determine whether the instantiation name is in the resource log. If so, keep the module corresponding to the instantiation name; if not, delete the module corresponding to the instantiation name.

[0097] After the traversal is completed, the first netlist uniquely corresponding to the simulation case is generated.

[0098] In this implementation, hardware resources not used by the software are directly deleted for simulation, which directly simplifies the size of the netlist and optimizes the simulation time.

[0099] Reference Figure 5 , Figure 5 A schematic diagram of an implementation of a first netlist.

[0100] Based on the above steps, it can be seen that the technical solution of the present application obtains a netlist containing very few modules, which greatly reduces the size of the netlist. Those skilled in the art can undoubtedly infer that when the size of the netlist is greatly reduced, the speed of compilation and simulation will be greatly improved.

[0101] Reference Figure 6 , Figure 6 Taking the device scale of 400k minimum array module as a reference, a comparison chart of simulation + compilation time / netlist size / compilation by-product size of the simulation netlist obtained by applying the above simulation netlist generation method and the unmodified netlist is shown.

[0102] In summary, the method for generating an array device simulation netlist of the present application can significantly reduce the size of the netlist, thereby significantly reducing the compilation time and compilation by-products during the simulation verification process, and greatly improving the efficiency of simulation verification.

[0103] In this embodiment, no matter what kind of case, this method can be used when doing verification, which can directly reduce the time cost and storage cost.

[0104] Embodiment 2:

[0105] Reference Figure 7 Based on Example 1, the present application also discloses a device for generating a simulation netlist of an arrayed device, including: a first coordinate marking module 101, a second coordinate marking module 102, an instantiation name module 103, and a netlist generation module 104.

[0106] The first coordinate marking module 101 is used to select a basic unit module in the arrayed device as the origin of the coordinate system, and mark the coordinates of all remaining basic unit modules with the origin of the coordinate system to obtain the coordinates of all basic unit modules; the arrayed device includes basic unit modules and non-basic unit modules, and the basic unit module is the module with the most arraying times and the smallest physical area in the arrayed device.

[0107] The second coordinate marking module 102 is used to mark the coordinates of adjacent non-basic unit modules according to the coordinate markings of the basic unit modules. Any non-basic unit module must be adjacent to at least one non-basic unit module.

[0108] The instantiation name module 103 is used to use the coordinate mark of the basic unit module as the instantiation name of the basic unit module, and use the coordinate mark of the non-basic unit module and the name of the non-basic unit module as the instantiation name to obtain a Verilog hardware netlist.

[0109] The netlist generation module 104 is used to filter the Verilog hardware netlist according to a preset resource log, retain the modules whose instantiation names are recorded in the resource log, and obtain a first netlist corresponding to the simulation case. The resource log is compiled according to the simulation case.

[0110] In this embodiment, the basic unit module is an array module, and the non-basic unit module includes: an IP module and an IO module.

[0111] Embodiment 2 is written on the basis of Embodiment 1, and Embodiment 2 includes all the technical features of the embodiment. The limitation and improvement of the method for generating a simulation netlist in Embodiment 1 are also applicable to the device for generating a simulation netlist in Embodiment 2.

[0112] Embodiment 3:

[0113] On the basis of Example 1, the present invention further discloses a simulation verification method for an arrayed device, and the first netlist obtained by the method for generating a simulation netlist for an arrayed device in Example 1 is recompiled and simulated and verified.

[0114] In summary, the embodiments of the present invention provide a method and device for generating a simulation netlist of an arrayed device and a simulation verification method, which have the following beneficial effects:

[0115] (1) The simulation netlist generation method of the present invention can effectively reduce the size of the netlist in the simulation process, thereby greatly reducing the compilation time and required storage space in the simulation verification process, and greatly improving the efficiency of simulation verification.

[0116] (2) The present invention tests different simulation cases separately. Once an error occurs, only this simulation case needs to be tested, which greatly improves the troubleshooting efficiency. If a large number of cases are compressed into one test stimulus, multiple cases can be traversed in one simulation. If one of the many cases is wrong, the design will be modified every time an error is found, and the subsequent compilation / simulation will continue to iterate. When a new error is caused after correcting the previous error, the case must be repeated over and over again. The cycle is repeated, and the time spent on simulation will be very huge.

[0117] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and substitutions can be made without departing from the technical principles of the present invention. These improvements and substitutions should also be regarded as the scope of protection of the present invention.

Claims

1. A method for generating a simulation netlist of an arrayed device, characterized in that: include: A basic unit module in the arrayed device is selected as the origin of the coordinate system, and the coordinates of all the remaining basic unit modules are marked with the origin of the coordinate system to obtain the coordinates of all the basic unit modules; the arrayed device includes a basic unit module and a non-basic unit module, the basic unit module is a module with the largest number of arraying times and the smallest physical area in the arrayed device, and the length or width of the non-basic unit module is an integer multiple of the length or width of the basic unit module; Mark the coordinates of adjacent non-basic unit modules according to the coordinate marks of the basic unit modules. Any non-basic unit module must be adjacent to at least one non-basic unit module. The coordinate mark of the basic unit module is used as the instantiation name of the basic unit module, and the coordinate mark of the non-basic unit module and the name of the non-basic unit module are used as the instantiation name to obtain a Verilog hardware netlist; The Verilog hardware netlist is screened according to a preset resource log to retain the modules whose instantiation names are recorded in the resource log, and a first netlist corresponding to the simulation case is obtained, wherein the resource log is compiled according to the simulation case; The coordinate marking of the adjacent non-basic unit modules according to the coordinate marking of the basic unit modules is specifically as follows: When a non-basic unit module is adjacent to multiple basic unit modules, the coordinate mark of the basic unit module at the lower left corner of the non-basic unit module is used as the coordinate mark of the non-basic unit module; If there is no basic unit module at the lower left corner of the non-basic unit module, the coordinate mark of the basic unit module at the lower right corner of the non-basic unit module is used as the coordinate mark of the non-basic unit module.

2. The method for generating a simulation netlist of an arrayed device according to claim 1, characterized in that: The basic unit module is an array module, and the non-basic unit module includes: an IP module and an IO module.

3. The method for generating a simulation netlist of an arrayed device according to claim 1, characterized in that: The method of selecting a basic unit module in the array device as the origin of the coordinate system is specifically: Determine whether the modules at the four corners of the arrayed device are basic unit modules. If a module at one of the four corners is a basic unit module, take the basic unit module at the corner as the origin of the coordinate system. If the modules in the four corners are all non-basic unit modules, the first basic unit module on the left or right side of the non-basic unit module in the corner is used as the origin of the coordinate system.

4. The method for generating a simulation netlist of an arrayed device according to claim 1, characterized in that: The coordinates of all remaining basic unit modules are marked with the origin of the coordinate system, specifically: The origin of the coordinate system is denoted as x0y0; in the horizontal direction, the x-coordinate of the basic unit module on the right side of the coordinate system origin increases, and the x-coordinate of the basic unit module on the left side of the coordinate system origin decreases; in the vertical direction, the y-coordinate of the basic unit module on the upper side of the coordinate system origin increases, and the y-coordinate of the basic unit module on the lower side of the coordinate system origin decreases.

5. The method for generating a simulation netlist of an arrayed device according to claim 1, characterized in that: The resource log is compiled according to the simulation case, specifically: Write multiple simulation cases according to the verification requirements, each of which can correspond to a single preset function; Input the prepared multiple simulation cases into the software for compilation. After the software is compiled, resource selection is performed and a resource list of the required device is generated. The resource names in the resource list match the instantiation names in the Verilog hardware netlist. Generate resource logs based on resource lists.

6. The method for generating a simulation netlist of an arrayed device according to claim 1, characterized in that: The Verilog hardware netlist is screened according to the preset resource log to retain the modules whose instantiation names are recorded in the resource log, and a first netlist corresponding to the simulation case is obtained, which is specifically: Get the instantiation name of the required module based on the resource log; Traverse each instantiation name of the Verilog hardware netlist and determine whether the instantiation name is in the resource log. If so, keep the module corresponding to the instantiation name; if not, delete the module corresponding to the instantiation name. After the traversal is completed, the first netlist uniquely corresponding to the simulation case is generated.

7. A device for generating a simulation netlist of an arrayed device, characterized in that: include: A first coordinate marking module, a second coordinate marking module, an instantiation name module, and a netlist generation module; The first coordinate marking module is used to select a basic unit module in the arrayed device as the origin of the coordinate system, and mark the coordinates of all the remaining basic unit modules with the origin of the coordinate system to obtain the coordinates of all the basic unit modules; the arrayed device includes basic unit modules and non-basic unit modules, the basic unit module is the module with the most arraying times and the smallest physical area in the arrayed device, and the length or width of the non-basic unit module is an integer multiple of the length or width of the basic unit module; The second coordinate marking module is used to mark the coordinates of adjacent non-basic unit modules according to the coordinate markings of the basic unit modules. Any non-basic unit module must be adjacent to at least one non-basic unit module. The instantiation name module is used to use the coordinate mark of the basic unit module as the instantiation name of the basic unit module, and the coordinate mark of the non-basic unit module and the name of the non-basic unit module as the instantiation name to obtain a Verilog hardware netlist; The netlist generation module is used to filter the Verilog hardware netlist according to a preset resource log, retain the modules whose instantiation names are recorded in the resource log, and obtain a first netlist corresponding to the simulation case, wherein the resource log is compiled according to the simulation case; The second coordinate marking module performs coordinate marking on adjacent non-basic unit modules according to the coordinate marking of the basic unit module, specifically: When a non-basic unit module is adjacent to a plurality of basic unit modules, the second coordinate marking module uses the coordinate mark of the basic unit module at the lower left corner of the non-basic unit module as the coordinate mark of the non-basic unit module; If there is no basic unit module at the lower left corner of the non-basic unit module, the second coordinate marking module uses the coordinate mark of the basic unit module at the lower right corner of the non-basic unit module as the coordinate mark of the non-basic unit module.

8. The device for generating a simulation netlist of an arrayed device according to claim 7, characterized in that: The basic unit module is an array module, and the non-basic unit module includes: an IP module and an IO module.

9. A simulation verification method for an array device, characterized in that: The first netlist in the method for generating a simulation netlist for an arrayed device according to any one of claims 1 to 6 is recompiled and simulated for verification.

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