Trigger-based wiring method, system, device and storage medium

Abstract

The present invention discloses a wiring method based on triggers, including obtaining the layout results of each design unit and storing them in a netlist; screening the key driving sources of the design unit according to the layout results; judging whether the current layout position of the key driving source is at the long-line implementation position of the logic unit wiring resource; if it is at the long-line implementation position of the logic unit wiring resource, marking the long-line implementation of the logic unit as occupied; if it is not at the long-line implementation position of the logic unit wiring resource, adjusting the layout according to a preset wiring adjustment strategy until the key driving source is at the long-line implementation position of the logic unit wiring resource; traversing all key driving sources in turn to obtain wiring results. By adjusting the implementation position of the CLB layout, the wiring resources are reasonably allocated when the driving source is far away from the load, so as to improve the efficiency of the use of timing and wiring resources. The present application also provides a wiring system, device and computer-readable storage medium based on triggers, which have the above-mentioned beneficial effects.

Description

Technical Field

[0001] The present invention relates to the technical field of field programmable gate array (FPGA) integrated circuits, and in particular to a wiring method, system, device and storage medium based on triggers. Background Art

[0002] FPGA chips are mainly composed of three components: logic units (CLB, Configurable Logic Blocks), input / output units (IO) and wiring resources (SRB, Switch Route Box). Figure 1 As shown, CLBs primarily consist of hardware units such as lookup tables (LUTs) and flip-flops (FFs). Layout is the process of properly planning and placing individual instances of user-designed units, such as LUTs and FFs in the design netlist, in legal, non-conflicting locations on the CLB.

[0003] Most current mainstream timing-driven layout algorithms are derived from the simulated annealing algorithm. This algorithm primarily adjusts layout results based on wirelength estimates, and through continuous iteration, it ultimately converges to a layout with optimal wirelength. Derivative algorithms also incorporate other factors, such as timing estimation. The ultimate goal is to ensure that all logic instances in the design are mapped to the chip's hardware CLBs while ensuring the legitimacy of the layout results, while also optimizing congestion, wirelength, and timing. Timing estimates vary slightly for different implementation locations on the CLB where the design instance is currently located. However, due to the architectural characteristics of FPGA chips, different implementations on the same CLB can significantly impact subsequent routing results.

[0004] Typically, the placement algorithm only focuses on which CLB the design unit is placed on, while the specific implementation mapped inside the CLB is often ignored, which greatly reduces the efficiency of wiring resource utilization. Summary of the Invention

[0005] Based on this, the present invention provides a trigger-based wiring method, system, device and storage medium, which solves the problem that when the driving source is far away from the load in the existing wiring algorithm, the internal implementation position of the CLB is ignored, resulting in low wiring resource utilization efficiency, large timing loss and low path timing.

[0006] An embodiment of the present invention provides a trigger-based wiring method, the method comprising:

[0007] Obtaining layout results of each design unit; storing the layout results in a netlist;

[0008] screening key driving sources of design units according to the layout results;

[0009] Determining whether the current layout position of the key driving source is at a long-line implementation position of a logic unit wiring resource;

[0010] If the long-line implementation position of the logic unit routing resource is occupied, the long-line implementation of the logic unit is marked as occupied;

[0011] If the key driving source is not at the long-line realization position of the logic unit wiring resource, adjusting the layout according to a preset wiring adjustment strategy until the key driving source is at the long-line realization position of the logic unit wiring resource;

[0012] All the key driving sources are traversed in sequence to obtain the wiring results.

[0013] Furthermore, when the current layout position of the key driving source is not at the long-line implementation position of the logic unit wiring resource, the layout is adjusted according to the preset wiring adjustment strategy as follows:

[0014] The key driving source is exchanged with the original driving source position at the long line realization position of the logic unit wiring resource.

[0015] Furthermore, screening the key driving sources of the design units according to the layout results includes:

[0016] Evaluate the post-routing timing violation risk of all sub-paths between design units based on the distance between them.

[0017] Compare the estimated timing violation risk with the timing constraints. The driving source whose estimated timing violation risk is higher than the timing constraints is the driving source of the design unit in the first screening.

[0018] Sort the first screened design unit driver sources in descending order of violation risk;

[0019] The sorting results are traversed according to the connection of the design unit in the netlist to obtain the distance between the driving source and all loads. If the distance between the two exceeds 16 wiring resources, the driving source is the key driving source of the design unit.

[0020] Furthermore, the timing constraint is [worst slack, worst slack+threshold], wherein worst slack is the minimum value of the difference between the timing violation risk of all sub-paths after routing between the design units and the timing constraint, and threshold is the adjustment threshold.

[0021] An embodiment of the present invention further provides a trigger-based wiring system, the system comprising:

[0022] An acquisition module is used to obtain the layout results of each design unit and store the layout results in a netlist;

[0023] A screening module, configured to screen key driving sources of design units according to the layout results;

[0024] A judgment module, configured to judge whether the current layout position of the key driving source is at a long-line realization position of a logic unit wiring resource;

[0025] The position adjustment module is used to adjust the layout according to a preset wiring adjustment strategy when the current layout position of the key driving source is not at the long-line implementation position of the logic unit wiring resource, until the key driving source is at the long-line implementation position of the logic unit.

[0026] Furthermore, the position adjustment module includes:

[0027] The driving source adjustment module is used to exchange the key driving source with the original driving source position at the long-line realization position of the logic unit wiring resource when the current layout position of the key driving source is not at the long-line realization position of the logic unit wiring resource.

[0028] Furthermore, the screening module includes:

[0029] The first sub-screening module is used to evaluate the post-routing timing violation risk of all sub-paths between design units based on the distance between the design units;

[0030] Compare the estimated timing violation risk with the timing constraints. The driving source whose estimated timing violation risk is higher than the timing constraints is the driving source of the design unit in the first screening.

[0031] Sort the first screened design unit driver sources in descending order of violation risk;

[0032] The second sub-screening module is used to traverse the distance between the driving source and all loads according to the connection of the design unit in the netlist based on the sorting results. If the distance between the two exceeds 16 wiring resources, the driving source is the key driving source of the design unit.

[0033] Furthermore, the first sub-screening module includes:

[0034] A constraint module is used to determine the timing that satisfies the timing constraint [worst slack, worst slack + threshold], where worst slack is the minimum value of the difference between the timing violation risk of all sub-paths after routing between design units and the timing constraint, and threshold is the adjustment threshold.

[0035] An embodiment of the present invention further provides a trigger-based wiring device, the device comprising:

[0036] Memory for storing computer programs;

[0037] A processor is configured to execute the computer program to implement the steps of any of the trigger-based wiring methods described above.

[0038] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the trigger-based wiring method as described above are implemented.

[0039] The technical solution provided by the embodiments of this application adjusts the implementation position of the CLB layout, preferentially connecting long-distance output ports to the long-line ports of the SRB. This achieves long-line implementation, rationally allocating wiring resources when the driver source is farther away than the load, effectively reducing timing loss, improving path timing, and enhancing the efficiency of wiring resource utilization. This application also provides a trigger-based wiring system, device, and computer-readable storage medium, all of which have the aforementioned beneficial effects and are not further elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 is a schematic diagram of a logic unit;

[0042] Figure 2 A flowchart of a trigger-based wiring method provided by an embodiment of the present invention;

[0043] Figure 3 Provide an idea for the network after the layout is completed;

[0044] Figure 4 for Figure 3 Schematic diagram of the signal transmission path from the driving source to the load; (a) shows the driving source trigger driving the load through multiple short lines, and (b) shows the driving source trigger driving the load through a short line and a long line;

[0045] Figure 5 Schematic diagram for implementing internal switching FFs within CLB;

[0046] Figure 6 A structural diagram of a trigger-based wiring system provided in an embodiment of the present application;

[0047] Figure 7 A structural diagram of another trigger-based wiring system provided in an embodiment of the present application;

[0048] Figure 8 A structural diagram of a trigger-based wiring device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0050] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0051] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0052] Please refer to Figure 2 , Figure 2 A flowchart of a trigger-based wiring method provided in an embodiment of the present application.

[0053] It specifically includes the following steps:

[0054] S101: Obtain layout results of each design unit; store the layout results in a netlist;

[0055] The FPGA software process includes logic synthesis, place and route, timing and power analysis, and bitstream generation for the user's design. Place and route are two submodules, and this solution is implemented between these two stages, optimizing the layout results and feeding them into the subsequent routing process.

[0056] The layout result mentioned here may specifically be one or more layout results specified by the user or the generation manufacturer, and this application does not specifically limit the layout result.

[0057] After completing the layout algorithm process for all design units in the design netlist, each design unit has a clear placement position on the chip, that is, a mapping relationship between the design unit and the hardware unit is formed, such as Figure 3 As shown in the figure, the design units mapped to specific locations on the chip are shown as black rectangles. At this point, no wiring has been performed, so the connections between them are flying wires, that is, the dotted lines in the figure. At this time, the layout results stored in the form of a netlist are obtained.

[0058] S102: Screening key driving sources of design units according to the layout results;

[0059] Optionally, screening the key driving sources of the design units according to the layout results includes:

[0060] Evaluate the post-routing timing violation risk of all sub-paths between design units based on the distance between them.

[0061] After the layout is completed, all design units have a clear physical location on the chip. Then, based on the distance between the design units, the timing violation risk of all sub-paths between the design units after routing is evaluated;

[0062] Compare the assessed timing violation risk with the timing constraints. The path whose assessed timing violation risk is higher than the timing constraint is considered a high-risk path, and its corresponding driving source is the driving source of the design unit screened in the first round.

[0063] Optionally, the timing constraint is [worst slack, worst slack+threshold], where worstslack is the minimum value of the difference between the timing violation risk of all sub-paths after routing between design units and the timing constraint, and threshold is the adjustment threshold.

[0064] Sort the first screened design unit driver sources in descending order of violation risk;

[0065] The sorting results are traversed according to the connection of the design unit in the netlist to obtain the distance between the driving source and all loads. If the distance between the two exceeds the distance of a long line, that is, 16 SRBs, then the driving source is the key driving source of the design unit.

[0066] FPGA chips are composed of many logic units and wiring resources arranged in an array. Short lines are usually circuit lines connecting two to four adjacent SRBs, while long lines are circuit lines that can connect SRBs that are 16 apart.

[0067] S103: Determine whether the current layout position of the key driving source is at the long-line implementation position of the logic unit wiring resource;

[0068] If yes, proceed to step S104; if no, proceed to step S105;

[0069] S104: If the long line implementation position of the logic unit routing resource is occupied, mark the long line implementation of the logic unit as occupied;

[0070] S105: If the key driving source is not at the long-line implementation position of the logic unit wiring resource, adjusting the layout according to a preset wiring adjustment strategy until the key driving source is at the long-line implementation position of the logic unit wiring resource;

[0071] Optionally, when the current layout position of the key driving source is not at the long-line implementation position of the logic unit wiring resource, the layout is adjusted according to a preset wiring adjustment strategy as follows:

[0072] The key driving source is exchanged with the original driving source position at the long line realization position of the logic unit wiring resource.

[0073] All the key driving sources are traversed in sequence to obtain the wiring results.

[0074] Figure 3 In the example, it is assumed that the driving source is trigger A, which can be mapped to 8 locations, which are marked as FF0 to FF7 from bottom to top. The driving source transmits the signal to the load trigger B which is relatively far away, such as Figure 4 As shown in the figure, the original position FF3 of the driving source is suitable for short and medium distance transmission, while the implementation FF1 is suitable for long distance transmission. If the driving source is changed from the original implementation FF3 to the implementation FF1, then when wiring, the signal output from the implementation FF1 can be connected to the long line port of the adjacent SRB first. After confirming that the load is outside a certain distance threshold, it can be directly driven to the load through the long line port on the second path. In contrast, the original implementation FF3 needs to go through multiple stages of SRBs before it can be driven to the load. Figure 5 As shown, if another driving source has been placed at the FF1 position, it will be swapped with the key driving source.

[0075] Because key drivers are sorted by timing violation risk when they are collected, the priority long-line implementation locations on the CLB are swapped for drivers with high violation risk. The CLB is also marked to indicate that its long-line implementation location is occupied. A CLB typically has multiple target implementation locations, and drivers mapped to these locations are prioritized for long-line routing, not just for triggers. In short, reasonable secondary planning of the layout results—that is, this solution swaps the implementation locations of driver sources already placed on the CLB—helps improve the timing performance of the final Place & Route.

[0076] Another common characteristic of FPGA chip architectures is that different trigger element positions have different effects on the efficiency of signal output through the long line. Only some output ports are more conducive to direct connection to the SRB's long-line output ports, while other ports require multiple SRB stages before connecting to the long-line ports. For long-distance loads, specific trigger element positions on the CLB can directly output through adjacent SRB long-line ports, for example, with a path like: drive source - long line - short line - load. In other implementations, the path is: drive source - short line - short line - short line - short line - load, resulting in significant timing loss.

[0077] Traverse the collected driving sources and determine the implementation currently used by the driving source. If the driving source is not placed on the long-line implementation of the CLB where it is located - that is, it is conducive to the implementation of the long line directly, and the long-line implementation of the CLB is not occupied, in order to make it easier to route the long line, it is necessary to swap the layout position of the driving source with the driving source on the target implementation, and record the CLB to mark that the long-line implementation of the CLB is occupied. For example, the CLB contains 4 LUTs and 8 FFs, the implementation of the key driving source is FF0, and it is currently placed on the FF2 implementation. The driving source on the FF2 implementation needs to be swapped with the driving source on the FF0 implementation. After performing the same process on all key driving sources, this wiring optimization solution is completed.

[0078] See also Figure 6 , Figure 6 An embodiment of the present application provides a trigger-based wiring system, the system comprising:

[0079] An acquisition module 100 is configured to acquire layout results of each design unit and store the layout results in a netlist;

[0080] A screening module 200 is used to screen key driving sources of design units according to the layout results;

[0081] A judgment module 300 is used to judge whether the current layout position of the key driving source is at a long-line implementation position of a logic unit wiring resource;

[0082] The position adjustment module 400 is used to adjust the layout according to a preset wiring adjustment strategy when the current layout position of the key driving source is not at the long-line implementation position of the logic unit wiring resource, until the key driving source is at the long-line implementation position of the logic unit.

[0083] See also Figure 7 , Figure 7 In another trigger-based wiring system provided in an embodiment of the present application, the position adjustment module 400 includes:

[0084] The driving source adjustment module is used to exchange the key driving source with the original driving source position at the long-line realization position of the logic unit wiring resource when the current layout position of the key driving source is not at the long-line realization position of the logic unit wiring resource.

[0085] The screening module 200 includes:

[0086] The first sub-screening module is used to evaluate the post-routing timing violation risk of all sub-paths between design units based on the distance between the design units;

[0087] Compare the estimated timing violation risk with the timing constraints. The driving source whose estimated timing violation risk is higher than the timing constraints is the driving source of the design unit in the first screening.

[0088] Sort the first screened design unit driver sources in descending order of violation risk;

[0089] The second sub-screening module is used to traverse the distance between the driving source and all loads according to the connection of the design unit in the netlist based on the sorting results. If the distance between the two exceeds 16 wiring resources, the driving source is the key driving source of the design unit.

[0090] The first sub-screening module includes:

[0091] A constraint module is used to determine the timing that satisfies the timing constraint [worst slack, worst slack + threshold], where worst slack is the minimum value of the difference between the timing violation risk of all sub-paths after routing between design units and the timing constraint, and threshold is the adjustment threshold.

[0092] Since the embodiments of the system part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the system part, and will not be repeated here.

[0093] See also Figure 8 , Figure 8 A structural diagram of a trigger-based wiring device provided in an embodiment of the present application.

[0094] The FPGA routing device 500 can vary significantly depending on its configuration or performance. It may include one or more processors (central processing units, CPUs) 501 (e.g., one or more processors), memory 502, and one or more storage media 505 (e.g., one or more mass storage devices) storing applications 503 or data 504. The memory 502 and storage media 505 may be either transient or persistent storage. The program stored in the storage medium 505 may include one or more modules (not shown), each of which may include a series of instruction operations within the device. Furthermore, the processor 501 may be configured to communicate with the storage medium 505 to execute the series of instruction operations stored in the storage medium 505 on the FPGA routing device 500.

[0095] The FPGA placement and routing device 500 may also include one or more power supplies 506, one or more wired or wireless network interfaces 507, one or more input and output interfaces 508, and / or one or more operating systems 509, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0096] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0097] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0098] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A wiring method based on triggers, characterized in that: include: Obtain the layout results of each design unit; storing the layout result in a netlist; screening key driving sources of design units according to the layout results; Determining whether the current layout position of the key driving source is at a long-line implementation position of a logic unit wiring resource; If the long-line implementation position of the logic unit routing resource is occupied, the long-line implementation of the logic unit is marked as occupied; If the key driving source is not at the long-line realization position of the logic unit wiring resource, adjusting the layout according to a preset wiring adjustment strategy until the key driving source is at the long-line realization position of the logic unit wiring resource; Traversing all the key driving sources in sequence to obtain wiring results; The screening of key driving sources of the design unit according to the layout result includes: Evaluate the post-routing timing violation risk of all sub-paths between design units based on the distance between them. Compare the estimated timing violation risk with the timing constraints. The driving source whose estimated timing violation risk is higher than the timing constraints is the driving source of the design unit in the first screening. Sort the first screened design unit driver sources in descending order based on violation risk; The sorting results are traversed according to the connection of the design unit in the netlist to obtain the distance between the driving source and all loads. If the distance between the two exceeds 16 wiring resources, the driving source is the key driving source of the design unit.

2. A wiring method based on triggers according to claim 1, characterized in that: When the current layout position of the key driving source is not in the long-line implementation position of the logic unit wiring resource, the layout is adjusted according to a preset wiring adjustment strategy, specifically: The key driving source is exchanged with the original driving source position at the long line realization position of the logic unit wiring resource.

3. A wiring method based on triggers according to claim 1, characterized in that: The timing constraint is [worst slack, worst slack + threshold], where worst slack is the minimum value of the difference between the timing violation risk of all sub-paths after routing between design units and the timing constraint, and threshold is the adjustment threshold.

4. A wiring system based on triggers, characterized in that include: An acquisition module is used to obtain the layout results of each design unit; storing the layout result in a netlist; A screening module, configured to screen key driving sources of design units according to the layout results; A judgment module, configured to judge whether the current layout position of the key driving source is at a long-line realization position of a logic unit wiring resource; a position adjustment module, configured to adjust the layout according to a preset wiring adjustment strategy until the key driving source is at the long-line realization position of the logic unit wiring resource when the current layout position of the key driving source is not at the long-line realization position of the logic unit wiring resource; The screening module includes: The first sub-screening module is used to evaluate the post-routing timing violation risk of all sub-paths between design units based on the distance between the design units; Compare the estimated timing violation risk with the timing constraints. The driving source whose estimated timing violation risk is higher than the timing constraints is the driving source of the design unit in the first screening. Sort the first screened design unit driver sources in descending order based on violation risk; The second sub-screening module is used to traverse the distance between the driving source and all loads according to the connection of the design unit in the netlist based on the sorting results. If the distance between the two exceeds 16 wiring resources, the driving source is the key driving source of the design unit.

5. A trigger-based wiring system according to claim 4, characterized in that: The position adjustment module includes: The driving source adjustment module is used to exchange the key driving source with the original driving source position at the long-line realization position of the logic unit wiring resource when the current layout position of the key driving source is not at the long-line realization position of the logic unit wiring resource.

6. A wiring system based on triggers according to claim 4, characterized in that: The first sub-screening module includes: The constraint module is used to determine the timing that meets the timing constraint [worst slack, worst slack + threshold]. Among them, worst slack is the distance between design units, which is the minimum difference between the timing violation risk of all sub-paths between design units after routing and the timing constraint, and threshold is the adjustment threshold.

7. A wiring device based on a trigger, characterized in that include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the trigger-based wiring method according to any one of claims 1 to 3.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the trigger-based wiring method according to any one of claims 1 to 3 are implemented.

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