Non-volatile storage device performing continuous access operation and operation method thereof

Abstract

The present disclosure provides a nonvolatile memory device comprising a memory cell array and a memory control circuit. The memory cell array comprises a plurality of sub-arrays, each of which comprises a plurality of memory cells coupled to a plurality of bit lines. The memory control circuit sequentially couples to at least one bit line provided in each sub-array based on a single read command signal to sequentially access the memory cells coupled to at least one of the bit lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0092988 filed on July 27, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference as if fully set forth. Technical Field

[0003] Various embodiments relate to an integrated circuit technology, and more particularly, to a nonvolatile memory device and a semiconductor system including the same. Background Art

[0004] Each electronic device includes many electronic components, and the computer system in these electronic devices includes many electronic components each including a semiconductor. The computer system may include a storage device. Dynamic random access memory (DRAM) can store and output data at a high and constant speed, and can be randomly accessed. These advantages make DRAM widely used as a common storage device. However, DRAM includes memory cells each composed of capacitors, which makes DRAM volatile, that is, when the power is cut off, the data stored therein is lost. In order to overcome this shortcoming of DRAM, a flash memory device has been developed. The flash memory device includes memory cells each composed of floating gates, which makes the flash memory device non-volatile, that is, the data stored therein will be retained even when the power is cut off. However, the speed at which the flash memory device stores and outputs data is lower than that of DRAM, and random access is not possible.

[0005] Recently, next-generation memory devices with high operating speeds and non-volatile properties have been developed. Examples of next-generation memory devices include phase change memory (PCM), magnetic RAM (MRAM), resistive RAM (ReRAM), and ferroelectric RAM (FRAM). Next-generation memory devices are capable of high-speed operation and non-volatile properties. Specifically, PRAM includes memory cells formed from chalcogenides and can store data by changing the resistance value of the memory cells. Summary of the Invention

[0006] In one embodiment, a nonvolatile memory device may include a memory cell array and a memory control circuit. The memory cell array may include multiple sub-arrays, each sub-array including multiple memory cells coupled to multiple bit lines. The memory control circuit may sequentially couple to at least one bit line provided in each sub-array based on a single read command signal to sequentially read data from the memory cells coupled to the at least one bit line.

[0007] In one embodiment, a method for operating a nonvolatile memory device may include: charging a global bit line and a local bit line coupled to the global bit line based on a single read command signal. The method may include: coupling the local bit line to a first bit line provided in a first subarray and reading data from a memory cell coupled to the first bit line. The method may also include: coupling the local bit line to a second bit line provided in a second subarray and reading data from a memory cell coupled to the second bit line.

[0008] In one embodiment, a nonvolatile memory device may include: a controller, a column selection circuit, a column control circuit, and a plurality of sense amplifiers. The controller may generate a column address signal based on an address signal, and sequentially enable a plurality of different local column selection signals when a global column selection signal is enabled based on the column address signal. The column selection circuit may select a local bit line to be coupled to a selected global bit line based on the global column selection signal, and couple at least one bit line on a corresponding plurality of sub-arrays to the selected local bit line based on the plurality of local column selection signals. The column control circuit may provide a column access voltage to the selected global bit line based on a read command signal. The plurality of sense amplifiers may be respectively coupled to a plurality of memory cells coupled to at least one bit line on each sub-array, and may read data from the plurality of memory cells to generate output data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram showing a configuration of a nonvolatile memory device according to one embodiment.

[0010] Figure 2 is a diagram showing a configuration of a nonvolatile memory device according to one embodiment.

[0011] Figure 3 It shows Figure 1 A diagram of the configuration of at least a portion of the controller shown in .

[0012] Figure 4 is a timing diagram illustrating the operation of a nonvolatile memory device according to one embodiment.

[0013] Figure 5 is a block diagram illustrating an electronic device including a semiconductor memory device according to one embodiment.

[0014] Figure 6 is a block diagram illustrating a data storage device including a semiconductor memory apparatus according to one embodiment. DETAILED DESCRIPTION

[0015] Figure 1is a diagram showing a configuration of a nonvolatile memory device 100 according to one embodiment. Figure 1 , the nonvolatile memory device 100 may include a memory cell array 110 and a memory control circuit. The memory cell array 110 may include a plurality of memory banks (not shown), each memory bank having a plurality of sub-arrays 111 and 112. A plurality of bit lines BL and a plurality of word lines WL may be provided on each of the plurality of sub-arrays 111 and 112. A plurality of memory cells MC may be coupled to respective intersections between the plurality of bit lines BL and the plurality of word lines WL. For example, Figure 1 Multiple sub-arrays 111 and 112 within a single memory bank are shown. Figure 1 For example, two subarrays within a single memory bank are shown, but a single memory bank may include four, eight, sixteen, thirty-two, or even more subarrays. Each of the plurality of memory cells MC may be a nonvolatile memory cell. Each of the plurality of memory cells MC may include a storage element and a switching element coupled to each other. Even without a refresh or rewrite operation, the storage element can maintain the physical state corresponding to the data stored therein for a long period of time. When a voltage higher than a threshold voltage is applied to a corresponding switching element coupled to the corresponding storage element, each of the plurality of memory cells MC can be accessed. When a voltage higher than the threshold voltage is applied, the switching element can turn on and / or snap back, and the memory cell MC is ready to allow current to flow. The storage element may include a floating gate of a dual-gate transistor, a phase change material, a variable resistance material, or the like. The nonvolatile memory device 100 may include phase change memory (PCM), resistive RAM (ReRAM), or spin torque transfer magnetoresistive RAM (STT-MRAM). The switching element may include a diode, a bidirectional threshold switch, a tunnel junction, or a two-terminal switching element, such as a mixed ion and electron conductor. In one embodiment, the switching element may include a three-terminal switching element, such as a field effect transistor (FET) or a bipolar junction transistor (BJT).

[0016] The memory cell array 110 may include a hierarchical connection structure. A plurality of global bit lines GBL and a plurality of local bit lines (not shown) may be provided on the memory cell array 110. Each of the plurality of global bit lines GBL may be coupled to a plurality of local bit lines coupled to a plurality of bit lines BL, respectively. Therefore, each of the plurality of memory cells MC of the memory cell array 110 may be accessed by sequentially selecting the plurality of global bit lines GBL, the plurality of local bit lines, and the plurality of bit lines BL. A plurality of global word lines GWL and a plurality of local word lines (not shown) may be provided on the memory cell array 110. Each of the plurality of global word lines GWL may be coupled to a plurality of local word lines coupled to a plurality of word lines WL, respectively. Therefore, each of the plurality of memory cells MC of the memory cell array 110 may be accessed by sequentially selecting the plurality of global word lines GWL, the plurality of local word lines, and the plurality of word lines WL.

[0017] The memory control circuit can access multiple memory cells MC of the memory cell array 110. The memory control circuit can read data from the multiple memory cells MC of the memory cell array 110. The memory control circuit can write data to the multiple memory cells MC of the memory cell array 110. The memory control circuit can receive a command signal CMD and an address signal ADD from an external device (not shown). The external device can be a host such as a memory controller, which is configured to control the operation of the non-volatile memory device 100. However, it is not limited to this, and the command signal CMD may include a read command signal and a write command signal. In response to the read command signal, the memory control circuit can read data from the multiple memory cells MC of the memory cell array 110 and provide the read data to the external device. In response to the write command signal, the memory control circuit can store the data provided from the external device into the multiple memory cells MC of the memory cell array 110.

[0018] The memory control circuit may generate a column address signal and a row address signal based on the address signal ADD. The memory control circuit may generate a column select signal based on the column address signal. The column select signal may include a global column select signal GY and a local column select signal LY. The memory control circuit may select a specific global bit line from a plurality of global bit lines GBL, a specific local bit line from a plurality of local bit lines, and a specific bit line from a plurality of bit lines BL based on the column select signal to access a specific memory cell MC. The memory control circuit may couple the specific global bit line and the specific local bit line to each other based on the global column select signal GY. The memory control circuit may couple the specific local bit line and the specific bit line to each other based on the local column select signal LY. The memory control circuit may generate a row select signal based on the row address signal. The row select signal may include a global row select signal GX and a local row select signal LX. The memory control circuitry can select a specific global word line from a plurality of global word lines GWL, a specific local word line from a plurality of local word lines, and a specific word line from a plurality of word lines WL based on a row select signal to access a specific memory cell from a plurality of memory cells MC. The memory control circuitry can couple the specific global word line and the specific local word line to each other based on a global row select signal GX. The memory control circuitry can couple the specific local word line and the specific word line to each other based on a local row select signal LX.

[0019] Based on a read command signal, the memory control circuitry may apply a first voltage to a selected global bit line and a second voltage to a selected global word line. The first voltage may be a column access voltage, and the second voltage may be a row access voltage. The voltage level difference between the first and second voltages may correspond to the voltage level of a read voltage applied across the accessed memory cell. In response to a write command signal, the memory control circuitry may apply one of a third and fourth voltages to the selected global bit line and a fifth voltage to the selected global word line. Each of the third and fourth voltages may be a column access voltage, and the fifth voltage may be a row access voltage. The voltage level difference between one of the third and fourth voltages and the fifth voltage may correspond to the voltage level of a write voltage applied across the accessed memory cell. The voltage level difference between the third and fifth voltages may correspond to the voltage level of a reset write voltage. The voltage level difference between the fourth and fifth voltages may correspond to the voltage level of a set write voltage. The memory control circuitry may apply a reset write voltage and / or a reset write current to the accessed memory cell to program the accessed memory cell to a reset state and / or a high-resistance state. The memory control circuit may apply a set write voltage and / or a set write current to the accessed memory cell to program the accessed memory cell to a set state and / or a low resistance state. The fourth voltage may have a voltage level lower than the third voltage and higher than the first voltage. The second voltage may have a voltage level higher than the fifth voltage and lower than the first voltage.

[0020] In response to a single command signal, the memory control circuit can continuously perform multiple access operations to sequentially access multiple memory cells MC. For example, in response to a single read command signal, the memory control circuit can sequentially couple to multiple bit lines BL and sequentially read data from multiple memory cells MC coupled to the multiple bit lines BL. The memory control circuit can sequentially couple to the respective bit lines provided in each sub-array 111 and 112. Based on the address signal ADD provided along with the single read command signal, the memory control circuit can sequentially couple to the respective bit lines provided in each sub-array 111 and 112. For example, based on a column address signal generated based on the address signal ADD, the memory control circuit can generate a global column select signal GY and a local column select signal LY. Based on the global column select signal GY, the memory control circuit can select a single global bit line and a single local bit line. Based on the local column select signal LY, the memory control circuit can couple the selected local bit line to at least one specific bit line provided in the first sub-array 111 to read data from the memory cell coupled to the specific bit line. After reading data from the memory cells in first sub-array 111, the memory control circuitry may change the logic level of the column address signal. For example, the memory control circuitry may increase or decrease the code value of a portion of the bits in the column address signal. The portion of the bits in the column address signal may contain information for selecting a specific sub-array among the plurality of sub-arrays 111 and 112. Based on the changed column address signal, the memory control circuitry may couple the selected local bit line to at least one specific bit line provided in second sub-array 112 to read data from the specific memory cell coupled to the specific bit line.

[0021] The memory control circuit may include a controller 121, a column selection circuit 122, a column control circuit 123, a row selection circuit 124, and a row control circuit 125. The controller 121 may receive a command signal CMD and an address signal ADD provided from an external device. The controller 121 may decode the command signal CMD to generate a read signal RD and a write signal WT. When the command signal CMD is a read command signal, the controller 121 may decode the command signal CMD to generate a read signal RD. When the command signal CMD is a write command signal, the controller 121 may decode the command signal CMD to generate a write signal WT.

[0022] The controller 121 may latch and / or decode the address signal ADD to generate a column address signal. The controller 121 may generate a column select signal based on the column address signal. The column select signal may include a global column select signal GY and a local column select signal LY. The controller 121 may enable a single global column select signal GY based on the column address signal. The controller 121 may change the code value of the column address signal at each predetermined time interval. For example, the controller 121 may change the code value of the column address signal a number of times equal to a threshold value. The controller 121 may sequentially generate multiple different local column select signals LY at each predetermined time interval. Thus, when the single global column select signal GY is enabled, the controller 121 may sequentially enable multiple different local column select signals LY. The multiple different local column select signals LY may be uniquely enabled. As used herein with respect to a parameter (such as a predetermined time interval), the term "predetermined" means that the value of the parameter is determined before the parameter is used in a process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0023] The controller 121 may latch and / or decode the address signal ADD to generate a row address signal. The controller 121 may generate a row select signal based on the row address signal. The row select signal may include a global row select signal GX and a local row select signal LX. For example, the controller 121 may change the logic value of the row address signal to generate a plurality of row address signals having different code values. The controller 121 may generate a plurality of global row select signals GX and a plurality of local row select signals LX based on the plurality of row address signals.

[0024] The column select circuit 122 may receive a column select signal from the controller 121. Based on the column select signal, the column select circuit 122 may select a local bit line to be coupled to the global bit line GBL and may select a bit line BL to be coupled to the selected local bit line. Based on the global column select signal GY, the column select circuit 122 may select a local bit line to be coupled to the global bit line GBL. Based on the local column select signal LY, the column select circuit 122 may select a bit line BL to be coupled to the selected local bit line. The column control circuit 123 may receive a read signal RD and a write signal WT from the controller 121. Based on the read signal RD and the write signal WT, the column control circuit 123 may apply a voltage and / or current to the global bit line GBL. For example, based on the read signal RD, the column control circuit 123 may apply a first voltage to the selected global bit line GBL to charge the global bit line GBL. Based on the write signal WT, the column control circuit 123 may apply one of a third voltage and a fourth voltage to the selected global bit line GBL to charge the selected global bit line GBL. When the column selection circuit 122 selects a specific bit line BL based on the global column selection signal GY and the local column selection signal LY, the column control circuit 123 can access a specific memory cell MC coupled to the specific bit line BL to read data from or write data into the specific memory cell MC.

[0025] The row selection circuit 124 may receive a row selection signal from the controller 121. Based on the row selection signal, the row selection circuit 124 may select a local word line to be coupled to the global word line GWL, and may select a word line WL to be coupled to the selected local word line. Based on the global row selection signal GX, the row selection circuit 124 may select a local word line to be coupled to the global word line GWL. Based on the local row selection signal LX, the row selection circuit 124 may select a word line WL to be coupled to the selected local word line. The row control circuit 125 may receive a read signal RD and a write signal WT from the controller 121. Based on the read signal RD and the write signal WT, the row control circuit 125 may provide a voltage and / or current to the global word line GWL. For example, based on the read signal RD, the row control circuit 125 may provide a second voltage to the selected global word line GWL. Based on the write signal WT, the row control circuit 125 may provide a fifth voltage to the selected global word line GWL. When the row selection circuit 124 selects a specific word line WL based on the global row selection signal GX and the local row selection signal LX, the row control circuit 125 can access a specific memory cell MC coupled to the specific word line WL to read data from or write data into the specific memory cell MC.

[0026] Figure 2 is a diagram showing a configuration of a nonvolatile memory device 200 according to one embodiment. Figure 2 Shown in Figure 1 Among the elements in the nonvolatile memory device 100 shown in FIG, some elements configured to perform a read operation are shown to clearly describe the read operation of the nonvolatile memory device 100. Figure 2 The nonvolatile memory device 200 may include a memory cell array 210, a bit line control circuit 220, and a plurality of sense amplifiers 230. The memory cell array 210 may include a plurality of memory banks each having a plurality of sub-arrays. For example, Figure 2 A single memory bank having four sub-arrays within a memory cell array 210 is shown. The first to fourth sub-arrays 211, 212, 213, and 214 can have the same configuration and density as one another. The same number of bit lines and the same number of word lines can be provided on the first to fourth sub-arrays 211, 212, 213, and 214, respectively. A plurality of memory cells MC can be coupled to each intersection between the plurality of bit lines and the plurality of word lines. Based on local column select signals LY1, LY2, LY3, and LY4, one of the plurality of bit lines on the first to fourth sub-arrays 211, 212, 213, and 214 can be coupled to a local bit line LBL1. The local bit line LBL1 can be coupled to a global bit line GBL1 based on a global column select signal GY1.

[0027] Although not shown, word lines on the first sub-array 211 can be coupled to a first local word line based on a first local row select signal LX1, and can be coupled to a first global word line based on a first global row select signal GX1. Word lines on the second sub-array 212 can be coupled to a second local word line based on a second local row select signal LX2, and can be coupled to a second global word line based on a second global row select signal GX2. Word lines on the third sub-array 213 can be coupled to a third local word line based on a third local row select signal LX3, and can be coupled to a third global word line based on a third global row select signal GX3. Word lines on the fourth sub-array 214 can be coupled to a fourth local word line based on a fourth local row select signal LX4, and can be coupled to a fourth global word line based on a fourth global row select signal GX4. Multiple sense amplifiers 230 can be coupled to the first to fourth global word lines in a one-to-one manner. The first sense amplifier SA1 may be coupled to the first global word line and may be coupled to one of the word lines on the first sub-array 211 via the first global word line and the first local word line. The second sense amplifier SA2 may be coupled to the second global word line and may be coupled to one of the word lines on the second sub-array 212 via the second global word line and the second local word line. The third sense amplifier SA3 may be coupled to the third global word line and may be coupled to one of the word lines on the third sub-array 213 via the third global word line and the third local word line. The fourth sense amplifier SA4 may be coupled to the fourth global word line and may be coupled to one of the word lines on the fourth sub-array 214 via the fourth global word line and the fourth local word line.

[0028] The bit line control circuit 220 may correspond to Figure 1 . Based on a read signal RD, the bitline control circuit 220 may provide a first voltage to the global bitline GBL1. The bitline control circuit 220 may be coupled to a power supply voltage node 201. Based on the read signal RD, the bitline control circuit 220 may provide a first voltage to the global bitline GBL1 to charge the global bitline GBL1. The bitline control circuit 220 may further receive a read reference voltage VRD. Based on the read reference voltage VRD, the bitline control circuit 220 may control the voltage level of the first voltage provided to the global bitline GBL1.

[0029] The first sense amplifier SA1 can read data from the memory cells MC in the first sub-array 211 via the first global word line. The first sense amplifier SA1 can sense the high resistance state or low resistance state of the accessed memory cells MC via the first global word line to generate output data DOUT<1:4>. For example, the first sense amplifier SA1 can sense the voltage level change of the first global word line and / or the amount of current flowing through the first global word line to generate output data DOUT <1> The second sense amplifier SA2 can read data from the memory cells MC within the second sub-array 212 via the second global word line. The second sense amplifier SA2 can sense a voltage level change of the second global word line and / or an amount of current flowing through the second global word line to generate output data DOUT. <2> The third sense amplifier SA3 can read data from the memory cells MC within the third sub-array 213 via the third global word line. The third sense amplifier SA3 can sense a voltage level change of the third global word line and / or an amount of current flowing through the third global word line to generate output data DOUT. <3> The fourth sense amplifier SA4 can read data from the memory cells MC within the fourth sub-array 214 via the fourth global word line. The fourth sense amplifier SA4 can sense a voltage level change of the fourth global word line and / or an amount of current flowing through the fourth global word line to generate output data DOUT. <4> .

[0030] The nonvolatile memory device 200 may further include a global column selection circuit 240 and a local column selection circuit 250. The global column selection circuit 240 and the local column selection circuit 250 may correspond to Figure 1 One or more partial components within the column selection circuit 122 shown in FIG. The global column selection circuit 240 may include a plurality of global column switches. The global bit line GBL1 may be coupled to "m" local bit lines, where "m" is an integer equal to or greater than 2. The global column selection circuit 240 may include "m" global column switches 241 to 24m. The first global column switch 241 may receive the first bit GY1 of the global column selection signal <1> , to couple the global bit line GBL1 and the local bit line LBL1 to each other. The m-th global column switch 24m may receive the m-th bit GY1 of the global column selection signal <m>, to couple the global bit line GBL1 and the local bit line LBLm to each other, the local bit line LBLm being different from the local bit line LBL1. The local column selection circuit 250 may include a plurality of local column switches. The local bit line LBL1 may be coupled to "n" bit lines provided on each of the first to fourth sub-arrays 211, 212, 213, and 214, where "n" is an integer equal to or greater than 2. The local column selection circuit 250 may include "4n" local column switches. The local column switch 2511 may receive the first bit LY1 of the first local column selection signal <1> , to couple the local bit line LBL1 and the first bit line BL11 on the first sub-array 211 to each other. The local column switch 251n can receive the nth bit LY1 of the first local column selection signal <n>, to couple the local bit line LBL1 and the n-th bit line BL1n on the first sub-array 211 to each other. The local column switch 2521 can receive the first bit LY2 of the second local column selection signal <1> , to couple the local bit line LBL1 to the first bit line BL21 on the second sub-array 212. The local column switch 252n can receive the nth bit LY2 of the second local column select signal. <n>, to couple the local bit line LBL1 to the nth bit line BL2n on the second sub-array 212. The local column switch 2531 can receive the first bit LY3 of the third local column selection signal. <1> , to couple the local bit line LBL1 and the first bit line BL31 on the third sub-array 213 to each other. The local column switch 253n can receive the nth bit LY3 in the third local column selection signal. <n>, to couple the local bit line LBL1 and the nth bit line BL3n on the third sub-array 213 to each other. The local column switch 2541 can receive the first bit LY4 in the fourth local column selection signal <1> , to couple the local bit line LBL1 and the first bit line BL41 on the fourth sub-array 214 to each other. The local column switch 254n can receive the nth bit LY4 in the fourth local column selection signal <n>, so as to couple the local bit line LBL1 and the n-th bit line BL4n on the fourth sub-array 214 to each other.

[0031] Although not shown, the nonvolatile memory device 200 may further include a global row selection circuit and a local row selection circuit. The global row selection circuit and the local row selection circuit may correspond to Figure 1 . The global row selection circuit may include a plurality of global row switches. The local row selection circuit may include a plurality of local row switches. The global row selection circuit may include at least four global row switches configured to receive first to fourth global row selection signals GX1, GX2, GX3, and GX4. The local row selection circuit may include at least four local row switches configured to receive first to fourth local row selection signals LX1, LX2, LX3, and LX4.

[0032] Figure 3 It shows Figure 1 1 is a diagram of a configuration of at least a portion of the controller 121 shown in FIG. Figure 3 1 shows some components related to the address signal ADD among the components in the controller 121. Figure 3 , the controller 121 may include an address decoder 310, a column select signal generator 320, and a row select signal generator 330. The address decoder 310 may receive an address signal ADD to latch the address signal ADD. The address decoder 310 may decode the address signal ADD to generate column address signals CADD<1:j> and row address signals RADD<1:k>. Each of "j" and "k" may be an integer equal to or greater than 2, and "j" and "k" may be the same as or different from each other. The address decoder 310 may decode some bits within the address signal ADD to generate column address signals CADD<1:j>, and may decode the remaining bits within the address signal ADD to generate row address signals RADD<1:k>. In one embodiment, the address decoder 310 may decrypt the address signal ADD according to a first scheme to generate column address signals CADD<1:j>, and may decrypt the address signal ADD according to a second scheme to generate row address signals RADD<1:k>. In one embodiment, the address decoder 310 may decode a first combination of the address signals ADD to generate column address signals CADD<1:j>, and may decode a second combination of the address signals ADD to generate row address signals RADD<1:k>.

[0033] The column select signal generator 320 may receive the column address signals CADD<1:j> provided from the address decoder 310. The column select signal generator 320 may generate a global column select signal GY1 and first to fourth local column select signals LY1, LY2, LY3, and LY4 based on the code values of the column address signals CADD<1:j>. Based on the column address signals CADD<1:j>, the column select signal generator 320 may enable the global column select signal GY1 and may sequentially enable the first to fourth local column select signals LY1, LY2, LY3, and LY4. The column select signal generator 320 may include a column address counter 321. The column address counter 321 may change the code values of the column address signals CADD<1:j>. The column address counter 321 may change the code values of the column address signals CADD<1:j> by as many times as a threshold value at each predetermined time interval. The predetermined time interval may be from when a read voltage is applied to a single memory cell to when output data is generated via a sense amplifier coupled to the single memory cell. The threshold number may be the number of sub-arrays coupled to a single local bit line, and may be an integer equal to or greater than 2. In one embodiment, the column address counter 321 may detect the completion of a read operation on a memory cell accessed based on the column address signal CADD<1:j> provided from the address decoder 310 to change the code value of the column address signal CADD<1:j>. The column address counter 321 may detect the completion of a read operation on a memory cell accessed based on the changed column address signal CADD<1:j> to change the code value of the column address signal CADD<1:j> to another value. The column address counter 321 may change the logic value of a portion of the bits within the column address signal CADD<1:j> to change the code value of the column address signal CADD<1:j>. The portion of the bits within the column address signal CADD<1:j> may have a logic value for Figure 2 Column address counter 321 may be configured to select a specific sub-array from among the first to fourth sub-arrays 211, 212, 213, and 214 shown in FIG. Therefore, column address counter 321 may allow at least one bit line in each of the first to fourth sub-arrays 211, 212, 213, and 214 to be sequentially coupled to local bit line LBL1 at each predetermined time interval. In one embodiment, column address counter 321 may change the logic value of a greater number of bits than a portion of the bits in column address signals CADD<1:j> to change the code value of column address signals CADD<1:j>. Column address counter 321 may allow different sequences of bit lines in each of the first to fourth sub-arrays 211, 212, 213, and 214 to be sequentially coupled to local bit line LBL1 at each predetermined time interval. For example, the column address counter 321 may allow the first bit line BL11 on the first sub-array 211 to be coupled to the local bit line LBL1 , and then the column address counter 321 may allow the nth bit line BL2 n on the second sub-array 212 to be coupled to the local bit line LBL1 .

[0034] The row select signal generator 330 may receive the row address signals RADD<1:k> provided from the address decoder 310. The row select signal generator 330 may generate first to fourth global row select signals GX1, GX2, GX3, and GX4 and first to fourth local row select signals LX1, LX2, LX3, and LX4 based on the code values of the row address signals RADD<1:k>. The row select signal generator 330 may substantially simultaneously enable the first to fourth global row select signals GX1, GX2, GX3, and GX4 and the first to fourth local row select signals LX1, LX2, LX3, and LX4. The row select signal generator 330 may include a row address counter 331. The row address counter 331 may change the code values of the row address signals RADD<1:k> to generate four row address signals having different code values. Based on the four row address signals, the row select signal generator 330 can substantially simultaneously enable the first to fourth global row select signals GX1, GX2, GX3, and GX4 and the first to fourth local row select signals LX1, LX2, LX3, and LX4. In one embodiment, the row select signal generator 330 can simultaneously enable the first to fourth global row select signals GX1, GX2, GX3, and GX4 and the first to fourth local row select signals LX1, LX2, LX3, and LX4. As used herein, the term "simultaneously" with respect to an occurrence refers to the occurrence of the events at overlapping time intervals. For example, if a first event occurs within a first time interval and a second event occurs within a second time interval, the first and second intervals at least partially overlap, such that there is a time when both the first and second events occur.

[0035] Figure 4 is a timing diagram showing the operation of the nonvolatile memory device 200 according to one embodiment. Figures 2 to 4 The operation of the nonvolatile memory device 200 according to one embodiment is described below. When the read signal RD is enabled based on the read command signal, the bit line control circuit 220 may charge the global bit line GBL1 to a first voltage. Based on the column address signal CADD<1:j> provided from the address decoder 310, the column select signal generator 320 may enable the first bit GY1 in the global column select signal GY1. <1> , and the global bit line GBL1 may be coupled to the local bit line LBL1 via the first global column switch 241. Therefore, the local bit line LBL1 may be charged to the first voltage.

[0036] Based on the row address signal RADD<1:k> provided from the address decoder 310, the row select signal generator 330 can enable the first to fourth global row select signals GX1, GX2, GX3, and GX4, and the first to fourth global word lines can be coupled to the first to fourth local word lines, respectively. Based on the row address signal RADD<1:k> provided from the address decoder 310, the row select signal generator 330 can enable the first to fourth local row select signals LX1, LX2, LX3, and LX4, and specific word lines on the first to fourth subarrays 211, 212, 213, and 214 can be coupled to the first to fourth global word lines, respectively.

[0037] When the column address signal CADD<1:j> includes information for selecting the first sub-array 211 among the first to fourth sub-arrays 211, 212, 213, and 214, the column select signal generator 320 can enable one of the bits of the first local column select signal LY1<1:n> based on the column address signal CADD<1:j> provided from the address decoder 310, and the specific bit line can be coupled to the local bit line LBL1 via one of the local column switches 2511 to 251n. Therefore, a read voltage can be applied to the memory cell MC coupled between the selected bit line and the selected word line in the first sub-array 211. When the first local column select signal LY1<1:n> is enabled, the first sense amplifier SA1 can be activated. The first sense amplifier SA1 can sense a voltage level change of the first global word line and / or an amount of current flowing through the first global word line based on the resistance state of the memory cell MC to generate the first output data DOU. <1> .

[0038] When a predetermined amount of time has passed or the first output data DOUT output from the first sub-array 211 is detected <1> Upon generation, the column address counter 321 may change the code value of the column address signal CADD<1:j> provided from the address decoder 310 to a first value. The column select signal generator 320 may disable the first local column select signal LY1<1:n> to decouple the local bit line LBL1 from the bit lines BL11 to BL1n on the first sub-array 211. The column select signal generator 320 may enable one of the bits of the second local column select signal LY2<1:n> based on the changed code value of the column address signal CADD<1:j>, and the specific bit line may be coupled to the local bit line LBL1 via one of the local column switches 2521 to 252n. Therefore, a read voltage may be applied to the memory cell MC coupled between the selected bit line and the selected word line on the second sub-array 212. When the second local column select signal LY2<1:n> is enabled, the second sense amplifier SA2 may be activated. The second sense amplifier SA2 can sense the voltage level change of the second global word line and / or the amount of current flowing through the second global word line according to the resistance state of the memory cell MC to generate the second output data DOUT <2> .

[0039] When a predetermined amount of time has passed again or the second output data DOUT output from the second sub-array 212 is detected <2> Upon generation, the column address counter 321 may change the first value, which is the code value of the column address signal CADD<1:j>, to a second value. The column select signal generator 320 may disable the second local column select signal LY2<1:n> to decouple the local bit line LBL1 from the bit lines BL21 to BL2n on the second sub-array 212. The column select signal generator 320 may enable one of the bits of the third local column select signal LY3<1:n> based on the changed code value of the column address signal CADD<1:j>, and the specific bit line may be coupled to the local bit line LBL1 via one of the local column switches 2531 to 253n. Therefore, a read voltage may be applied to the memory cell MC coupled between the selected bit line and the selected word line on the third sub-array 213. When the third local column select signal LY3<1:n> is enabled, the third sense amplifier SA3 may be activated. The third sense amplifier SA3 may sense a voltage level change of the third global word line and / or an amount of current flowing through the third global word line according to the resistance state of the memory cell MC to generate a third output data DOUT <3> .

[0040] When a predetermined amount of time has passed again or the third output data DOUT output from the third sub-array 213 is detected <3> Upon generation, the column address counter 321 may change the second value, which is the code value of the column address signal CADD<1:j>, to a third value. The column select signal generator 320 may disable the third local column select signal LY3<1:n> to decouple the local bit line LBL1 from the bit lines BL31 to BL3n on the third sub-array 213. The column select signal generator 320 may enable one of the bits of the fourth local column select signal LY4<1:n> based on the changed code value of the column address signal CADD<1:j>, and the specific bit line may be coupled to the local bit line LBL1 via one of the local column switches 2541 to 254n. Therefore, a read voltage may be applied to the memory cell MC coupled between the selected bit line and the selected word line on the fourth sub-array 214. When the fourth local column select signal LY4<1:n> is enabled, the fourth sense amplifier SA4 may be activated. The fourth sense amplifier SA4 can sense the voltage level change of the fourth global word line and / or the amount of current flowing through the fourth global word line according to the resistance state of the memory cell MC to generate the fourth output data DOUT <4> .

[0041] Since the code value of column address signals CADD<1:j> has changed as many times as the threshold value, column select signal generator 320 does not further change the code value of column address signals CADD<1:j>, and fourth local column select signals LY4<1:n> may be disabled, thereby decoupling local bit line LBL1 from bit lines BL41 to BL4n in fourth subarray 214. Bit line control circuit 220 may discharge global bit line GBL1 and local bit line LBL1, and global column select signal GY1, first to fourth global row select signals GX1, GX2, GX3, and GX4, and first to fourth local row select signals LX1, LX2, LX3, and LX4 may be disabled. The read operation of nonvolatile memory device 200 may end with read signal RD disabled.

[0042] Since a global bit line coupled to a bit line control circuit is coupled to multiple local bit lines that are respectively coupled to multiple bit lines, the load on the global bit line and the multiple local bit lines is significantly large. Therefore, a considerable amount of power may be consumed to charge the global bit line. Therefore, during a read operation performed in response to a single read command signal, reading data from a single memory cell within a single sub-array may have a relatively low energy efficiency. According to one embodiment, during a read operation performed in response to a single read command signal, a nonvolatile memory device can sequentially read data from memory cells within multiple sub-arrays. That is, since the read operation is performed after charging a single global bit line and a single local bit line to sequentially read data from multiple memory cells, the energy efficiency of the read operation can be improved. Furthermore, since the nonvolatile memory device can perform a read operation to read data from multiple memory cells in response to a single read command signal, the page size of the nonvolatile memory device can be increased.

[0043] Figure 5 FIG is a block diagram showing an electronic device including a semiconductor memory device according to an embodiment. Figure 5 , the electronic device 4200 may include a processor 4210 , a memory 4220 , and an input / output device (I / O) 4230 . The processor 4210 , the memory 4220 , and the input / output device 4230 may be coupled via a bus 4246 .

[0044] The memory 4220 may receive control signals from the processor 4210. The memory 4220 may store code and data for the operation of the processor 4210. The memory 4220 may be used to store data to be accessed via the bus 4246. The memory 4220 may include at least one of the nonvolatile memory devices 100 and 200 described above. Additional circuits and additional control signals may be provided for specific implementation and modification of the embodiments.

[0045] The electronic device 4200 may be configured as various electronic control devices that require the memory 4220. For example, the electronic device 4200 may be used in a computer system, a wireless communication device, a personal digital assistant (PDA), a laptop computer, a portable computer, a web tablet, a wireless phone, a portable phone, a digital music player, an MPEG audio layer 3 (MP3) player, a navigator, a solid state drive (SSD), a home appliance, or any device capable of transmitting and receiving information in a wireless environment.

[0046] Figure 6 FIG is a block diagram illustrating a data storage device including a semiconductor memory device according to one embodiment. Figure 6 , a data storage device such as a solid state disk (SSD) 4311 may be provided. The solid state disk 4311 may include an interface 4313 , a controller 4315 , a non-volatile memory 4318 , and a buffer memory 4319 .

[0047] Solid-state disk 4311 uses semiconductor devices to store information. Compared to hard disk drives (HDDs), solid-state disk 4311 has the advantages of high operating speed, reduced mechanical delay, low failure rate, low heat generation, low noise generation, small size, and light weight. Solid-state disk 4311 can be widely used in notebook PCs, netbooks, desktop PCs, MP3 players, or portable storage devices.

[0048] The controller 4315 may be provided adjacent to the interface 4313 and may be electrically coupled to the interface 4313. The controller 4315 may be a microprocessor including a memory controller and a buffer controller. The non-volatile memory 4318 may be provided adjacent to the controller 4315 and may be electrically coupled to the controller 4315 via the connection terminal T. The data storage capacity of the solid state disk 4311 may correspond to the non-volatile memory 4318. The buffer memory 4319 may be provided adjacent to the controller 4315 and may be electrically coupled to the controller 4315.

[0049] Interface 4313 may be coupled to host 4302 and may transmit electrical signals, such as data. For example, interface 4313 may operate according to standards such as Serial Advanced Technology Attachment (SATA), Integrated Drive Electronics (IDE), Small Computer System Interface (SCSI), and / or combinations thereof. Non-volatile memory 4318 may be coupled to interface 4313 via controller 4315.

[0050] The nonvolatile memory 4318 may store data received via the interface 4313. As described above, according to one embodiment, the nonvolatile memory 4318 may include at least one of the nonvolatile memory devices 100 and 200. The nonvolatile memory 4318 has a characteristic of retaining data stored therein even if the power supply of the solid state disk 4311 is turned off.

[0051] The buffer memory 4319 may include a volatile memory or a nonvolatile memory. The volatile memory may be a DRAM and / or an SRAM. As described above, according to one embodiment, the nonvolatile memory may include at least one of the nonvolatile memory devices 100 and 200.

[0052] The data processing speed of the interface 4313 may be relatively fast when compared to the operating speed of the non-volatile memory 4318. The buffer memory 4319 may temporarily store data. Data received via the interface 4313 may be temporarily stored in the buffer memory 4319 by the controller 4315, and then may be non-temporarily stored in the non-volatile memory 4318 according to the data writing speed of the non-volatile memory 4318.

[0053] Frequently used data among the data stored in the nonvolatile memory 4318 can be pre-read and temporarily stored in the buffer memory 4319. The buffer memory 4319 can increase the effective operating speed of the solid state disk 4311 and reduce the error rate of the solid state disk 4311.

[0054] Although certain embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely exemplary. Therefore, the non-volatile memory device and method of operating a non-volatile memory device that performs a continuous access operation should not be limited based on the described embodiments. Rather, the non-volatile memory device and method of operating a non-volatile memory device that performs a continuous access operation described herein should be limited only in light of the appended claims in conjunction with the above description and accompanying drawings.< / n> < / n> < / n> < / n> < / m>

Claims

1. A nonvolatile storage device comprising: a memory cell array comprising a plurality of sub-arrays, each of the sub-arrays comprising a plurality of memory cells coupled to a plurality of bit lines; as well as a memory control circuit configured to sequentially couple to at least one bit line provided on each of the sub-arrays coupled to the local bit lines based on a single read command signal to sequentially read data from memory cells coupled to the at least one bit line; The local bit lines are coupled to global bit lines.

2. The nonvolatile memory device according to claim 1, wherein: The memory control circuit includes a column selection circuit configured to couple at least one bit line provided on each of the sub-arrays to the local bit line and to couple the local bit line to the global bit line according to a column selection signal generated based on an address signal provided together with the single read command signal.

3. The nonvolatile memory device according to claim 2, wherein: The memory control circuit is configured to charge the global bit line and the local bit line to a column access voltage based on the single read command signal.

4. The nonvolatile memory device according to claim 2, wherein: The column selection signal includes a global column selection signal and a local column selection signal. The global column selection signal is used to couple the local bit line to the global bit line. The local column selection signal is used to couple the at least one bit line arranged on each of the sub-arrays to the local bit line.

5. The nonvolatile memory device according to claim 1, wherein: The memory control circuit includes a row selection circuit configured to couple word lines coupled to memory cells coupled to at least one bit line provided on each of the sub-arrays to different local word lines and global word lines, respectively, based on an address signal provided together with the single read command signal. The word lines are coupled to memory cells coupled to at least one bit line provided on each of the sub-arrays. The nonvolatile memory device according to claim 5 , wherein: The memory control circuit includes a row control circuit coupled to the global word line and configured to read data from memory cells coupled to at least one bit line provided on each of the sub-arrays.

7. A method for operating a non-volatile memory device, the method comprising: charging a global bit line and a local bit line coupled to the global bit line based on a single read command signal; coupling the local bit line to a first bit line disposed on a first sub-array and reading data from a memory cell coupled to the first bit line; as well as The local bit line is coupled to a second bit line provided on a second sub-array, and data is read from a memory cell coupled to the second bit line.

8. The operating method according to claim 7, wherein: The step of charging the global bit line and the local bit line comprises: coupling the global bit line and the local bit line to each other based on a column address signal generated according to an address signal supplied together with the single read command signal; and A column access voltage is provided to the global bit line and the local bit line.

9. The operating method according to claim 7, wherein: The step of reading data from a memory cell coupled to the first bit line comprises: coupling the local bit line and the first bit line to each other based on a column address signal generated according to an address signal supplied together with the single read command signal; and Output data is generated according to a resistance state of a memory cell coupled to the first bit line.

10. The operating method according to claim 9, wherein: The step of reading data from a memory cell coupled to the second bit line comprises: By changing the code value of the column address signal, the coupling between the local bit line and the first bit line is released, and the local bit line and the second bit line are coupled to each other; and Output data is generated according to a resistance state of a memory cell coupled to the second bit line.

11. The operating method according to claim 7, further comprising: Before or simultaneously with charging the global and local bit lines, a first global word line is coupled to a word line coupled to a memory cell coupled to the first bit line, and a second global word line is coupled to a word line coupled to a memory cell coupled to the second bit line.

12. The operating method according to claim 7, wherein: The step of reading data from a memory cell coupled to the second bit line comprises: Before coupling the local bit line to the second bit line, the local bit line is decoupled from the first bit line.

13. A non-volatile storage device comprising: a controller configured to generate a column address signal based on the address signal and sequentially enable a plurality of different local column select signals when a global column select signal is enabled based on the column address signal; a column selection circuit configured to select a local bit line to be coupled to the selected global bit line based on the global column selection signal, and to couple at least one bit line on a corresponding plurality of sub-arrays to the selected local bit line based on the plurality of local column selection signals; a column control circuit configured to provide a column access voltage to a selected global bit line based on a read command signal; as well as A plurality of sense amplifiers are respectively coupled to a plurality of memory cells coupled to the at least one bit line on each of the sub-arrays, and the plurality of sense amplifiers are configured to read data from the plurality of memory cells to generate output data.

14. The nonvolatile memory device according to claim 13, wherein: The controller is configured to sequentially enable the plurality of local column select signals such that the local column select signals are uniquely enabled relative to each other.

15. The nonvolatile memory device according to claim 13, wherein: The controller is configured to sequentially enable the plurality of local column selection signals by changing information of a column address signal for selecting a specific subarray among the plurality of subarrays.

16. The nonvolatile memory device according to claim 15, wherein: The controller includes a column address counter configured to increase or decrease a code value of a bit of the column address signal corresponding to information for selecting the specific subarray from among the plurality of subarrays.

17. The nonvolatile memory device according to claim 13, wherein: The controller is configured to generate a row address signal based on the address signal, and to generate a plurality of different global row selection signals and a plurality of different local row selection signals based on the row address signal.

18. The nonvolatile memory device according to claim 17 further includes a row selection circuit, wherein the row selection circuit is configured to couple the multiple word lines respectively coupled to the multiple memory cells to different local word lines based on the multiple different local row selection signals, and to couple the different local word lines to different global word lines based on the multiple different global row selection signals.

19. The nonvolatile memory device according to claim 18, wherein: The plurality of sense amplifiers are coupled to the different global word lines in a one-to-one manner.

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