Flash memory controller and method for accessing a flash memory module

Abstract

The present application discloses a method for accessing a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: sending a read instruction to the flash memory module to request data on at least one memory cell; and analyzing state information of a plurality of memory cells of the at least one memory cell based on information from the flash memory module to determine a decoding method used by a decoder. The flash memory module of the present application can output multi-bit information of each memory cell to the flash memory controller in response to a read instruction, and the multi-bit information of each memory cell can indicate the critical voltage or state of the memory cell, thereby greatly improving the reading efficiency; in addition, the decoder of the present application can determine whether the number of the plurality of states is balanced or unbalanced to adopt different decoding mechanisms, thereby improving the decoding efficiency.

Description

[0001] The original application's application date, application number, and invention title.

[0002] This application is a divisional application of Chinese invention application filed on July 17, 2019, with application number 201910647330.2 and entitled "Flash Controller and Method for Accessing Flash Module". Technical Field

[0003] This invention relates to access control of flash memory, and more particularly to a method for managing access to flash memory modules, a related flash memory controller, and an electronic device. Background Technology

[0004] In recent years, due to the continuous development of memory technology, various portable or non-portable memory devices (such as memory cards conforming to SD / MMC, CF, MS, XD, and UFS standards respectively; solid-state drives (SSDs); and embedded memory devices conforming to UFS and eMMC specifications respectively) have been widely implemented in many applications. Therefore, access control of the memory in these memory devices has become a very hot topic.

[0005] Commonly used NAND flash memory can be broadly categorized into two types: single-level cell (SLC) and multiple-level cell (MLC). In single-level cell flash memory, each transistor acting as a memory cell has only two charge values, representing logic 0 and logic 1 respectively. In contrast, in multiple-level cell flash memory, the storage capacity of each transistor acting as a memory cell is fully utilized, driven by higher voltages to record at least two bits of information (such as 00, 01, 11, 10) within a single transistor through different voltage levels. Theoretically, the recording density of multiple-level cell flash memory can be at least twice that of single-level cell flash memory, which is very good news for the NAND flash memory industry, which has previously encountered bottlenecks in its development.

[0006] Compared to single-cell flash memory, multi-cell flash memory quickly became the mainstream choice for memory devices due to its lower cost and ability to provide larger capacity within a limited space. However, problems caused by the instability of multi-cell flash memory also emerged. To ensure that access control of flash memory in memory devices complies with relevant specifications, flash memory controllers typically have certain management mechanisms to properly manage data access.

[0007] According to existing technologies, memory devices with the above-mentioned management mechanisms still have shortcomings. For example, when triple-level cell (TLC) memory devices are used, problems such as increased bit error rates arise. Although traditional sensing schemes for reading data from TLC flash memory have been proposed to address these issues, they are ineffective for memory devices with quadruple-level cell (QLC) flash memory. In particular, traditional sensing schemes are not good for the high-level storage potential per memory cell in QLC flash memory. Therefore, a novel method and related architecture are needed to enhance overall performance with little or no side effects. Summary of the Invention

[0008] One object of the present invention is to disclose a method for managing the access of a memory device, which can efficiently obtain sufficient information for decoding operations even in a high-density storage arrangement, thereby solving the above-mentioned problems.

[0009] One embodiment of the present invention discloses a flash memory controller, wherein the flash memory controller is coupled to a flash memory module, the flash memory module including at least one flash memory chip, each flash memory chip including multiple blocks, and each block including multiple pages. The flash memory controller includes a memory and a microprocessor. The memory is used to store program code. The microprocessor is used to execute the program code to access the flash memory module through control logic. In this process, after the microprocessor sends a read instruction to the flash memory module to request data on at least one memory cell, the control logic determines whether the difference between the number of states of multiple memory cells in the at least one memory cell is within a predetermined range, and generates a determination result. If the determination result indicates that the difference is not within the predetermined range, the control logic receives multiple first specific positions and multiple second specific positions read from the multiple memory cells of the at least one memory cell, and a decoder in the control logic uses a second decoding method to decode using the multiple first specific positions and the multiple second specific positions. If the determination result indicates that the difference is within the predetermined range, the control logic only receives the multiple first specific positions read from the multiple memory cells of the at least one memory cell, and the decoder uses a first decoding method to decode using the multiple first specific positions. Each memory cell of the at least one memory cell is used to store multiple bits, and the multiple states are used to indicate different combinations of the multiple bits, and each memory cell has only one state.

[0010] Another embodiment of the present invention discloses a method for accessing a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes multiple blocks, each block includes multiple pages, and the method includes: sending a read instruction to the flash memory module using a flash memory controller to request data on at least one memory cell; using control logic to determine whether the difference between the number of multiple states of multiple memory cells of the at least one memory cell is within a predetermined range, to generate a determination result; if the determination result indicates that the difference is not within the predetermined range, then the control logic receives multiple first specific locations and multiple second specific locations read from the multiple memory cells of the at least one memory cell, and a decoder in the control logic uses a second decoding method to decode using the multiple first specific locations and the multiple second specific locations; and if the determination result indicates that the difference is within the predetermined range, then the control logic only receives the multiple first specific locations read from the multiple memory cells of the at least one memory cell, and the decoder uses a first decoding method to decode using the multiple first specific locations. Each memory cell of the at least one memory unit is used to store multiple bits, and the multiple states are used to indicate different combinations of the multiple bits, and each memory cell has only one state. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 This is a schematic diagram of a three-dimensional NAND flash memory according to an embodiment of the present invention.

[0013] Figure 3 The illustration is based on an embodiment of the present invention. Figure 2 The diagram shows some partial structures of a three-dimensional NAND flash memory.

[0014] Figure 4 The illustration is based on an embodiment of the present invention. Figure 2 Some implementation details of one of the multiple memory cells in a three-dimensional NAND flash memory shown.

[0015] Figure 5 This is a schematic diagram of multiple states (programmed states) of a memory cell in a fourth-order cell block according to an embodiment of the present invention.

[0016] Figure 6 This is a schematic diagram of a flash memory chip according to an embodiment of the present invention.

[0017] Figure 7 This is a schematic diagram of a sensing amplifier according to a first embodiment of the present invention.

[0018] Figure 8 According to an embodiment of the present invention Figure 7 The timing diagram shows some signals of the sensing amplifier.

[0019] Figure 9 This is a schematic diagram of a counter and a mapping circuit according to an embodiment of the present invention.

[0020] Figure 10 This is a schematic diagram of states S0 to S15 and the corresponding most significant bit and multiple least significant bits according to an embodiment of the present invention.

[0021] Figure 11 This is a timing diagram of the transmission and reading instructions and the most significant bit / least significant bit according to an embodiment of the present invention.

[0022] Figure 12 This is a flowchart of a method for accessing a flash memory module according to an embodiment of the present invention.

[0023] Figure 13 This is a histogram of multiple states of multiple memory cells according to an embodiment of the present invention.

[0024] Figure 14 This is a schematic diagram of a sensing amplifier according to a second embodiment of the present invention.

[0025] Figure 15 According to an embodiment of the present invention Figure 14 The timing diagram shows some signals of the sensing amplifier.

[0026] The reference numerals in the attached figures are explained as follows:

[0027] 10 Electronic devices

[0028] 50 Main Unit

[0029] 52 processor

[0030] 54 Power Supply Circuit

[0031] 100 memory devices

[0032] 110 Memory Controller

[0033] 112 microprocessor

[0034] 112C program code

[0035] 112M Read-Only Memory

[0036] 114 Control Logic Circuit

[0037] 132 encoder

[0038] 134 decoder

[0039] 136 Randomizer

[0040] 138 Derandomizer

[0041] 116 Random Access Memory

[0042] 118 Transmission Interface Circuit

[0043] 120 Flash Module

[0044] 122-1, 122-2, ..., 122-N flash memory chips

[0045] 1200, 1202, 1204, 1206, 1208,

[0046] Steps 1210, 1212, 1214, 1216

[0047] M(1,1,1),M(2,1,1),…,M(Nx,1,1),

[0048] M(1,2,1),…,M(Nx,2,1),…,

[0049] M(1,Ny,1),…,M(Nx,Ny,1),

[0050] M(1,1,2),M(2,1,2),…,M(Nx,1,2),

[0051] M(1,2,2),…,M(Nx,2,2),…,

[0052] M(1,Ny,2),…,M(Nx,Ny,2),…,

[0053] M(1,1,Nz),…,M(Nx,1,Nz),

[0054] M(1,2,Nz),…,M(Nx,2,Nz),…,

[0055] M(1,Ny,Nz),…,M(Nx,Ny,Nz),

[0056] M(nx,ny,nz) memory cells

[0057] MBLS(1,1),…,MBLS(Nx,1),

[0058] MBLS(1,2),…,MBLS(Nx,2),…,

[0059] MBLS(1,Ny),…,MBLS(Nx,Ny) Upper Selection Circuit

[0060] MSLS(1,1),…,MSLS(Nx,1),

[0061] MSLS(1,2),…,MSLS(Nx,2),…,

[0062] MSLS(1,Ny),…,MSLS(Nx,Ny) selects the circuit below.

[0063] BL(1),…,BL(Nx) bit lines

[0064] WL(1,1),WL(2,1),…,WL(Ny,1),

[0065] WL(1,2),WL(2,2),…,WL(Ny,2),…,

[0066] WL(1,Nz),WL(2,Nz),…,WL(Ny, Wordline)

[0067] Nz)

[0068] BLS(1), BLS(2), ..., BLS(Ny) (Select lines above)

[0069] SLS(1), SLS(2), ..., SLS(Ny) (Select lines below)

[0070] SL(1),SL(2),…,SL(Ny) source lines

[0071] PS2D(1), PS2D(2), ..., PS2D(Ny) circuit modules

[0072] S(1,1),…,S(Nx,1),

[0073] S(1,2),…,S(Nx,2),…,

[0074] S(1,Ny),…,S(Nx,Ny) Secondary circuit modules

[0075] Mch rod segment

[0076] The upper side of the Md rod segment

[0077] Ms. lower side of the rod segment

[0078] Mfg First tubular local structure

[0079] Mcg Second Tubular Local Structure

[0080] VR1, VR2, VR3, VR4, VR5

[0081] VR6, VR7, VR8, VR9, VR10

[0082] VR11, VR12, VR13, VR14, VR15 Read Voltage

[0083] S0, S1, S2, S3, S4, S5, S6, S7

[0084] S8, S9, S10, S11, S12, S13, S14, S15 states

[0085] 600 flash memory chips

[0086] 610, 620 memory arrays

[0087] 612, 614, 622, 624 Sensing Amplifiers

[0088] 632, 634 peripheral circuits

[0089] 700, 1400 Sensing Amplifier

[0090] 710, 1410 operational amplifiers

[0091] 712, 1412 Voltage Source

[0092] 714 Control Circuit

[0093] 716 Counter

[0094] 910 Mapping Circuit

[0095] 1414 Digital-to-Analog Converter

[0096] Vout output signal

[0097] Vsen, Vpre, VBL voltage

[0098] VR reading voltage

[0099] CNT count value

[0100] CBL Parasitic Capacitance

[0101] SW1 switch

[0102] I_cell current

[0103] T0, T1, T2 time

[0104] CNT_EN and DAC_EN enable signals Detailed Implementation

[0105] Figure 1 This is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a main device 50 and a memory device 100. The main device 50 may include at least one processor (e.g., one or more processors), collectively referred to as processor 52, and may also include a power supply circuit 54 coupled to processor 52. Processor 52 can be used to control the operation of the main device 50, while power supply circuit 54 can be used to provide power to processor 52 and memory device 100, and output one or more drive voltages to memory device 100. Memory device 100 can be used to provide storage space to the main device 50, and the autonomous device 50 obtains the one or more drive voltages as power for memory device 100. Examples of the main device 50 may include (but are not limited to): multifunctional mobile phones, tablet computers, and personal computers such as desktop computers and laptop computers. Examples of memory device 100 may include (but are not limited to): solid-state drives (SSDs) and various types of embedded memory devices such as embedded memory devices conforming to the Peripheral Component Interconnect Express (PCIe) standard. According to this embodiment, memory device 100 may include a flash memory controller 110 and may also include a flash memory module 120, wherein the flash memory controller 110 is used to control the operation of memory device 100 and access flash memory module 120, and flash memory module 120 is used to store information. Flash memory module 120 may include at least one flash memory chip, such as a plurality of flash memory chips 122-1, 122-2, ... and 122-N, where "N" may represent a positive integer greater than one.

[0106] like Figure 1As shown, the memory controller 110 may include processing circuitry such as a microprocessor 112, a storage unit such as a read-only memory (ROM) 112M, a control logic circuitry 114, a random access memory (RAM) 116, and a transmission interface circuitry 118, wherein these components are coupled to each other via a bus. The RAM 116 is implemented as a static RAM (SRAM), but the invention is not limited thereto. The RAM 116 can be used to provide internal storage space to the flash memory controller 110; for example, the RAM 116 can be used as a buffer memory to buffer data. Additionally, in this embodiment, the read-only memory 112M is used to store program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory module 120. Note that in some examples, the program code 112C may be stored in the RAM 116 or any form of memory. Furthermore, the control logic circuit 114 can be used to control the flash memory module 120 and may include an encoder 132, a decoder 134, a randomizer 136, a de-randomizer 138, and other circuits. The transmission interface circuit 118 may conform to a specific communication standard (such as Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect (PCI), Fast Peripheral Interconnect (HPI), Universal Flash Storage (UFS), etc.) and may communicate according to the specific communication standard, for example, between the memory device 100 and the host device 50. The host device 50 may include a corresponding transmission interface circuit conforming to the specific communication standard to communicate between the host device 50 and the memory device 100.

[0107] In this embodiment, the host device 50 can transmit a host command and the corresponding logical address to the flash memory controller 110 to access the memory device 100. The flash memory controller 110 receives the host command and the logical address, and translates the host command into a memory operation command (hereinafter referred to as the operation command). Then, it uses the operation command to control the flash memory module 120 to read, write / program memory cells (e.g., pages) at certain physical addresses in the flash memory module 120, where the physical address corresponds to the logical address. When the memory controller 110 performs an erase operation on any one of the flash memory chips 122-n among the flash memory chips 122-1, 122-2, ... and 122-N (the symbol "n" can represent any integer in the range [1, N]), at least one of the multiple blocks of the flash memory chip 122-n will be erased. Each of the multiple blocks may include multiple pages (e.g., data pages), and an access operation (e.g., read or write) may be performed on one or more pages.

[0108] Figure 2 This is a schematic diagram of a three-dimensional (3D) NAND flash memory according to an embodiment of the present invention. For example, any memory component of at least one of the flash memory chips 122-1, 122-2, ... and 122-N can be based on... Figure 2 The invention is implemented using the three-dimensional NAND flash memory shown, but is not limited thereto.

[0109] According to this embodiment, the three-dimensional NAND flash memory may include a plurality of memory cells arranged in a three-dimensional architecture, such as (Nx*Ny*Nz) memory cells arranged in the Nz layer perpendicular to the Z-axis and aligned in the three directions corresponding to the X-axis, Y-axis and Z-axis respectively: {{M(1,1,1),…,M(Nx,1,1)},{M(1,2,1),…,M(Nx,2,1)},…,{M(1,Ny,1),…,M(Nx,Ny,1)}}, {{M(1,1,2),…,M(Nx ...}, {{M(1,1,2),…,M(Nx,1)}}}, {{M(1,1,2),…,M(Nx,1)}}}, {{M(1,1,2),…,M(Nx,1)}}}, {{M(1,1,2),…,M(Nx,1)}}}, {{M(1, ,2)},{M(1,2,2),…,M(Nx,2,2)},…,{M(1,Ny,2),…,M(Nx,Ny,2)}}、…、and{{M(1,1,Nz),…,M(Nx,1,Nz)},{M(1,2,Nz),…,M(Nx,2,Nz)},…,{M(1,Ny,Nz),…,M(Nx,Ny,Nz)}}, and may also include multiple selector circuits for selection control, such as an upper layer arranged above the Nz layer. The Nx*Ny top selector circuits {MBLS(1,1),…,MBLS(Nx,1)}, {MBLS(1,2),…,MBLS(Nx,2)},… and {MBLS(1,Ny),…,MBLS(Nx,Ny)} arranged below the Nz layer, and the Nx*Ny bottom selector circuits {MSLS(1,1),…,MSLS(Nx,1)}, {MSLS(1,2),…,MSLS(Nx,2)},… and {MSLS(1,Ny),…,MSLS(Nx,Ny)} arranged below the Nz layer. In addition, the three-dimensional NAND flash memory may include multiple bit lines and multiple word lines for access control, such as Nx bit lines BL(1), ... and BL(Nx) arranged in a top layer above the upper layer, and (Ny*Nz) word lines {WL(1,1),WL(2,1),...,WL(Ny,1)}, {WL(1,2),WL(2,2),...,WL(Ny,2)}, ... and {WL(1,Nz),WL(2,Nz),...,WL(Ny,Nz)} arranged in the Nz layer.In addition, the three-dimensional NAND flash memory may include multiple select lines for selection control, such as Ny upper select lines BLS(1), BLS(2), ... and BLS(Ny) arranged in the upper layer, and Ny lower select lines SLS(1), SLS(2), ... and SLS(Ny) arranged in the lower layer, and may also include multiple source lines for providing multiple reference levels, such as Ny source lines SL(1), SL(2), ... and SL(Ny) arranged in a bottom layer below the lower layer.

[0110] like Figure 2As shown, the three-dimensional NAND flash memory can be divided into Ny circuit modules PS2D(1), PS2D(2), ... and PS2D(Ny) distributed along the Y-axis. For ease of understanding, circuit modules PS2D(1), PS2D(2), ... and PS2D(Ny) may have certain electrical characteristics similar to a planar NAND flash memory (whose memory cells are arranged in a single layer), and therefore can be regarded as multiple virtual two-dimensional (pseudo-2D) circuit modules, but the present invention is not limited thereto. In addition, any circuit module PS2D(ny) among circuit modules PS2D(1), PS2D(2), ... and PS2D(Ny) may include Nx secondary circuit modules S(1,ny), ... and S(Nx,ny), where "ny" may represent any integer in the interval [1,Ny]. For example, circuit module PS2D(1) may include Nx secondary circuit modules S(1,1), ... and S(Nx,1), circuit module PS2D(2) may include Nx secondary circuit modules S(1,2), ... and S(Nx,2), ..., and circuit module PS2D(Ny) may include Nx secondary circuit modules S(1,Ny), ... and S(Nx,Ny). In circuit module PS2D(ny), any one of the secondary circuit modules S(1,ny), ..., S(Nx,ny) may include Nz memory cells M(nx,ny,1), M(nx,ny,2), ..., M(nx,ny,Nz), and may include a set of selector circuits corresponding to the memory cells M(nx,ny,1), M(nx,ny,2), ..., M(nx,ny,Nz), such as the upper selector circuit MBLS(nx,ny) and the lower selector circuit MSLS(nx,ny), where "nx" may represent any integer in the interval [1,Nx]. The upper selector circuit MBLS(nx,ny), the lower selector circuit MSLS(nx,ny), and the memory cells M(nx,ny,1), M(nx,ny,2), ..., M(nx,ny,Nz) may be implemented by transistors. For example, the upper selector circuit and the lower selector circuit MSLS(nx,ny) can be implemented by ordinary transistors without any floating gates, and any memory cell M(nx,ny,nz) among the memory cells M(nx,ny,1), M(nx,ny,2), ... and M(nx,ny,Nz) can be implemented by a floating gate transistor, where “nz” can represent any integer in the interval [1,Nz], but the present invention is not limited thereto.Furthermore, the upper selector circuits MBLS(1,ny), ... and MBLS(Nx,ny) in the circuit module PS2D(ny) can be selected according to the selection signal on the corresponding selection line BLS(ny), while the lower selector circuits MSLS(1,ny), ... and MSLS(Nx,ny) in the circuit module PS2D(ny) can be selected according to the selection signal on the corresponding selection line SLS(ny).

[0111] Figure 3 The illustration is based on an embodiment of the present invention. Figure 2 The diagram shows some local structures of a three-dimensional NAND flash memory. The three-dimensional NAND flash memory can be designed to have multiple rod-shaped local structures, such as... Figure 3 The illustrated rod-shaped local structures can be arranged to pass through the secondary circuit modules {S(1,1),…,S(Nx,1)}, {S(1,2),…,S(Nx,2)},… and {S(1,Ny),…,S(Nx,Ny)}, respectively. For ease of understanding, the multiple rod-shaped local structures can be considered as… Figure 2 The architecture shown includes channels of the associated transistors for the secondary circuit modules {S(1,1),…,S(Nx,1)}, {S(1,2),…,S(Nx,2)},… and {S(1,Ny),…,S(Nx,Ny)}, such as channels of ordinary transistors for implementing the upper selector circuit MBLS(nx,ny) and the lower selector circuit MSLS(nx,ny), and channels of floating gate transistors for implementing the memory cell M(nx,ny,nz). According to some embodiments, the number of the plurality of rod-shaped local structures may be equal to the total number (Nx*Ny) of the secondary circuit modules {S(1,1),…,S(Nx,1)}, {S(1,2),…,S(Nx,2)},… and {S(1,Ny),…,S(Nx,Ny)}, but the invention is not limited thereto. For example, the arrangement of the plurality of memory cells may be varied, and the number of the plurality of rod-shaped local structures may be changed accordingly.

[0112] Furthermore, the three-dimensional NAND flash memory can be designed to have multiple pipe-shaped local structures, and these multiple pipe-shaped local structures can be arranged to surround the multiple rod-shaped local structures to form the various components of the secondary circuit modules {S(1,1),…,S(Nx,1)}, {S(1,2),…,S(Nx,2)},… and {S(1,Ny),…,S(Nx,Ny)}, particularly forming… Figure 2The architecture shown includes the control gates and floating gates of the plurality of memory cells, as well as the gates of the plurality of selector circuits. The memory cells {{M(1,1,1),M(2,1,1),…},{M(1,1,2),M(2,1,2),…},…} and word lines {WL(1,1),WL(1,2),…} are drawn in… Figure 3 In the middle, and Figure 3 The tubular local structure shown indicates that there are certain additional local structures surrounding each of the plurality of rod-shaped local structures, and details of these additional local structures will be further described in subsequent embodiments.

[0113] Figure 4 The illustration is based on an embodiment of the present invention. Figure 2 Some implementation details of one of the plurality of memory cells in the three-dimensional NAND flash memory shown. For example... Figure 4 As shown, the memory cell M(nx,ny,nz) may include a portion of one of the plurality of rod-shaped local structures, such as a rod segment Mch in the rod-shaped local structure corresponding to the secondary circuit module S(nx,ny), and may also include certain tubular local structures having the same axis of symmetry. For example, the upper side Md and the lower side Ms of the rod segment Mch can be used as the drain and source of a floating gate transistor for implementing the memory cell M(nx,ny,nx), and a first tubular local structure Mfg and a second tubular local structure Mcg among these tubular local structures can be used as the floating gate and control gate of this floating gate transistor. Other tubular local structures among these tubular local structures, such as the tubular local structure between the rod segment Mch and the first tubular local structure Mfg, and the tubular local structure between the first tubular local structure Mfg and the second tubular local structure Mcg, may be implemented by one or more insulating materials.

[0114] According to certain embodiments, Figure 2 Any of the multiple selector circuits in the illustrated architecture can be modified. Figure 4 The architecture shown is used for implementation. For example, the upper Md and lower Ms of the rod segment Mch can be used as the drain and source of a common transistor for implementing this selector circuit, while the second tubular local structure Mcg in these tubular local structures can be used as the gate of this common transistor, wherein the first tubular local structure Mfg should be removed from the one or more insulating materials. Therefore, there will only be one tubular local structure between the rod segment Mch and the second tubular local structure Mcg, but the invention is not limited thereto.

[0115] In the flash memory module 120, when a block of any of the flash memory chips 122-1 to 122-N acts as a single-level cell block, each of the multiple physical pages in the block corresponds to one logical page, that is, each of the multiple memory cells in the page is configured to store only one bit. One physical page may include all transistors controlled by a word line (e.g., memory cells M(1,1,Nz) to M(Nx,1,Nz) corresponding to word line WL(1,Nz) form a physical page). When a block of any of the flash memory chips 122-1 to 122-N acts as a multi-level cell block, each of the multiple physical pages in the block corresponds to two logical pages, that is, each of the multiple memory cells in the page is configured to store two bits. When a block of any of the flash memory chips 122-1 to 122-N acts as a three-level cell block, each of the multiple physical pages in the block corresponds to three logical pages, that is, each of the multiple memory cells in the page is configured to store three bits. When a block of any of the flash memory chips 122-1 to 122-N acts as a fourth-order cell block, each of the multiple physical pages in the block corresponds to four logical pages, that is, each of the multiple memory cells of the page is configured to store four bits.

[0116] Figure 5 This is a schematic diagram illustrating multiple states (programming states) of a memory cell in a fourth-order cell block according to an embodiment of the present invention. Figure 5 As shown, each memory cell can have sixteen states, and each state represents a different combination of four positions (named apex, upper, middle, and lower, respectively). Figure 5In the illustrated embodiment, when the memory cell is programmed to have state S0, the top, upper, middle, and lower positions of the memory cell are stored as (1,1,1,1); when the memory cell is programmed to have state S1, the top, upper, middle, and lower positions of the memory cell are stored as (1,1,1,0); when the memory cell is programmed to have state S2, the top, upper, middle, and lower positions of the memory cell are stored as (1,0,1,0); when the memory cell is programmed to have state S3, the top, upper, middle, and lower positions of the memory cell are stored as (1,0,0). When the memory cell is programmed to have state S4, the top, upper, middle, and lower positions of the memory cell are stored as (1,0,0,1); when the memory cell is programmed to have state S5, the top, upper, middle, and lower positions of the memory cell are stored as (0,0,0,1); when the memory cell is programmed to have state S6, the top, upper, middle, and lower positions of the memory cell are stored as (0,0,0,0); when the memory cell is programmed to have state S7, the top, upper, middle, and lower positions of the memory cell are stored as (0,0,1,0). When the memory cell is programmed to have state S8, the top, upper, middle, and lower positions of the memory cell are stored as (0,1,1,0); when the memory cell is programmed to have state S9, the top, upper, middle, and lower positions of the memory cell are stored as (0,1,0,0); when the memory cell is programmed to have state S10, the top, upper, middle, and lower positions of the memory cell are stored as (1,1,0,0); when the memory cell is programmed to have state S11, the top, upper, middle, and lower positions of the memory cell are stored as (1,1,0,1); when the memory cell is programmed to have state S11, the top, upper, middle, and lower positions of the memory cell are stored as (1,1,0,1); when the memory cell is programmed to have state S11, the memory cell is programmed to have state S11; when the memory cell is programmed to have state S10, the top, upper, middle, and lower positions of the memory cell are stored as (1,1,0,1); when the memory cell is programmed to have state S11, the memory cell is programmed to have state S11; ... The memory cell is programmed to have state S12, with the top, upper, middle, and lower positions of the memory cell stored as (0,1,0,1); when the memory cell is programmed to have state S13, the top, upper, middle, and lower positions of the memory cell are stored as (0,1,1,1); when the memory cell is programmed to have state S14, the top, upper, middle, and lower positions of the memory cell are stored as (0,0,1,1); and when the memory cell is programmed to have state S15, the top, upper, middle, and lower positions of the memory cell are stored as (1,0,1,1).

[0117] In the prior art, when the top bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply four read voltages VR5, VR10, VR12, and VR15 to read the memory cell. If the memory cell is conducting when read voltage VR5 is applied, the top bit is determined to be "1"; if the memory cell is not conducting when read voltage VR5 is applied and the memory cell is conducting when read voltage VR10 is applied, the top bit is determined to be "0"; if the memory cell is not conducting when read voltage VR10 is applied and the memory cell is conducting when read voltage VR12 is applied, the top bit is determined to be "1"; if the memory cell is not conducting when read voltage VR12 is applied and the memory cell is conducting when read voltage VR15 is applied, the top bit is determined to be "0"; and if the memory cell is not conducting when read voltage VR15 is applied, the top bit is determined to be "1". When the upper bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply three read voltages VR2, VR8, and VR14 to read the memory cell. If the memory cell is conducting when read voltage VR2 is applied, the upper bit is determined to be "1"; if the memory cell is not conducting when read voltage VR2 is applied and the memory cell is conducting when read voltage VR8 is applied, the upper bit is determined to be "0"; if the memory cell is not conducting when read voltage VR8 is applied and the memory cell is conducting when read voltage VR14 is applied, the upper bit is determined to be "1"; if the memory cell is not conducting when read voltage VR14 is applied, the upper bit is determined to be "0". When the middle bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply four read voltages VR3, VR7, VR9, and VR13 to read the memory cell. If the memory cell is on when a read voltage VR3 is applied, the intermediate bit is determined to be "1"; if the memory cell is not on when a read voltage VR3 is applied and the memory cell is on when a read voltage VR7 is applied, the intermediate bit is determined to be "0"; if the memory cell is not on when a read voltage VR7 is applied and the memory cell is on when a read voltage VR9 is applied, the intermediate bit is determined to be "1"; if the memory cell is not on when a read voltage VR9 is applied and the memory cell is on when a read voltage VR13 is applied, the intermediate bit is determined to be "0"; and if the memory cell is not on when a read voltage VR13 is applied, the intermediate bit is determined to be "1".When the lower bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply four read voltages VR1, VR4, VR6, and VR11 to read the memory cell. If the memory cell is on when read voltage VR1 is applied, the lower bit is determined to be "1"; if the memory cell is not on when read voltage VR1 is applied and the memory cell is on when read voltage VR4 is applied, the lower bit is determined to be "0"; if the memory cell is not on when read voltage VR4 is applied and the memory cell is on when read voltage VR6 is applied, the lower bit is determined to be "1"; if the memory cell is not on when read voltage VR6 is applied and the memory cell is on when read voltage VR11 is applied, the lower bit is determined to be "0"; and if the memory cell is not on when read voltage VR11 is applied, the lower bit is determined to be "1".

[0118] It should be noted that, Figure 5 The Gray code shown is for illustrative purposes only and is not intended to limit the invention. Any suitable Gray code can be used in the memory device 100, and the read voltage used to determine the top bit, upper bit, middle bit, and lower bit can be changed accordingly.

[0119] Bits read from the memory cells using portions of read voltages VR1 to VR15 can be considered as sign bits. Sign bits obtained from multiple memory cells (e.g., four thousand (4K) memory cells) are processed by derandomizer 138 and subjected to error correction by decoder 134 to generate decoded data. However, because the state range of memory cells in a multi-level cell block is very small, these states can exhibit significant variation due to read interference, programming interference, or data retention problems occurring in the flash memory module 120, potentially causing error correction to fail. To address this issue, existing technologies apply additional read voltages to read the memory cells to obtain multiple soft bits, increasing the success rate of error correction. For example, if decoder 134 cannot decode the multiple sign bits obtained from the plurality of memory cells, flash controller 110 may control flash module 120 to use additional read voltage to reread the plurality of memory cells to obtain a first set of soft bits, and decoder 134 may use a low-density parity-check code (LDPC) method to decode the plurality of sign bits with the first set of soft bits. For example, if flash controller 110 attempts to read the top page of the block (i.e., the top bits of the plurality of memory cells), flash controller 110 may control flash module 120 to use additional read voltages (VR5-Δ), (VR10-Δ), (VR12-Δ), and (VR15-Δ) to obtain the first set of soft bits. If the decoder 134 still cannot decode, the flash memory controller 110 can control the flash memory module 120 to use additional read voltages (VR5+Δ), (VR10+Δ), (VR12+Δ), and (VR15+Δ) to reread the plurality of memory cells to obtain a second set of soft bits, and the decoder 134 can use the low-density parity check method to decode the plurality of sign bits with the first set of soft bits and the second set of soft bits, etc.

[0120] Given the above, if the flash memory controller 110 needs to read data from the fourth-order cell block in the flash memory module 120, the flash memory controller 110 can read the plurality of memory cells and decode the data multiple times to obtain soft bits to successfully decode the data. Each time the flash memory controller 110 reads the plurality of memory cells, it needs to send a read command to the flash memory module 120, and the flash memory module 120 needs a read busy time to read the sign bit or soft bit. Therefore, the read mechanism in the prior art for high-density storage (such as fourth-order cell blocks using 3D NAND flash memory technology) is not efficient.

[0121] To address the aforementioned problems, embodiments of the present invention disclose a reading mechanism and a decoding method for efficiently accessing the flash memory module 120.

[0122] Figure 6 This is a schematic diagram of a flash memory chip 600 according to an embodiment of the present invention, wherein the flash memory chip 600 may be... Figure 1 Any of the flash memory chips 122-1 to 122-N shown. For example... Figure 6 As shown, the flash memory chip 600 includes two memory arrays 610 and 620, sense amplifiers 612, 614, 622 and 624, and peripheral circuits 632 and 634, wherein the memory arrays 610 and 620 include Figure 2 The memory cells shown, the sense amplifiers 612, 614, 622 and 624 are used to read data from the memory arrays 610 and 620, and the peripheral circuits 632 and 634 include pads, related control circuits and other interface circuits.

[0123] Figure 7 This is a schematic diagram of a sensing amplifier 700 according to a first embodiment of the present invention. Figure 7 In this embodiment, the sensing amplifier 700 includes an operational amplifier 710, a voltage source 712, a control circuit 714, a counter 716, and a switch SW1. The sensing amplifier 700 is used to read... Figure 1 The memory cell M(1,1,Nz) is shown corresponding to bit line BL(1) and word line WL(1,Nz). When memory cell M(1,1,Nz) is to be read, control circuit 714 is used to generate read voltage VR. Figure 1 The memory cell M(1,1,Nz) is shown, while the selector circuit MBLS(1,1) above and other memory cells M(1,1,1)~M(1,1,(Nz-1)) are controlled to be turned on.

[0124] Please refer to the above. Figure 7 as well as Figure 8 , Figure 8The following is a timing diagram of certain signals of a sense amplifier 700 according to an embodiment of the present invention. During the operation of the sense amplifier 700, the read voltage VR is initially equal to zero (i.e., the memory cell M(1,1,Nz) is disabled), and switch SW1 is controlled to connect bit line BL(1) to voltage source 712. Voltage source 712 begins to charge parasitic capacitance CBL such that the voltage VBL at one terminal of parasitic capacitance CBL is equal to the voltage Vpre provided by voltage source 712 at time T0. Then, at time T1, switch SW1 is controlled to connect bit line BL(1) to the negative terminal of operational amplifier 710, and control circuit 714 begins to generate a ramp signal acting as the read voltage VR to word line WL(1,Nz) to control memory cell M(1,1,Nz). Control circuit 714 also generates a uniform energy signal CNT_EN to cause counter 716 to start operating and provide an incrementing count value CNT when output signal Vout goes high. For example, suppose memory cell M(1,1,Nz) stores data corresponding to state S8 (its critical voltage is approximately 3V). When the read voltage VR starts to rise from 0V to 3V, memory cell M(1,1,Nz) cannot be enabled because the read voltage VR is not high enough. The voltage VBL remains at voltage Vpre. Since voltage VBL / Vpre is greater than the reference voltage Vsen at the positive terminal of operational amplifier 710, the output signal Vout generated by operational amplifier 710 is equal to "0". When the read voltage VR is greater than the critical voltage of memory cell M(1,1,Nz) at time T2, memory cell M(1,1,Nz) is enabled to generate a current I_cell to discharge the parasitic capacitance CBL, and voltage VBL decreases. When voltage VBL decreases and becomes lower than the reference voltage Vsen, output signal Vout becomes "1" to trigger counter 716 to output the current count value CNT. Figure 8 In the illustrated embodiment, if the memory cell M(1,1,Nz) stores data corresponding to state S8, the count value CNT is approximately "28".

[0125] exist Figure 7 as well as Figure 8In the illustrated embodiment, since the slope of the read voltage VR, the discharge time, and the circuit delay are known, the count value CNT output by counter 716 can accurately represent the critical voltage of memory cell M(1,1,Nz). Furthermore, if counter 716 is a counter with high resolution, such as an octet counter (i.e., the frequency used by counter 716 is high), the count value CNT can represent the sign bit and soft bit of memory cell M(1,1,Nz). Therefore, compared to the prior art which uses multiple read operations to obtain the sign bit and soft bit, the embodiment of the present invention can obtain the sign bit and soft bit with a single read instruction, and the read efficiency can be significantly improved. In addition, since the count value CNT output by counter 716 can represent the critical voltage of memory cell M(1,1,Nz), that is, the state of memory cell M(1,1,Nz) can be obtained, the information carried by the count value CNT is far more than that obtained by the sign bit in the prior art (i.e., the sign bit in the prior art cannot accurately indicate which state memory cell M(1,1,Nz) has). In detail, if the top bit of memory cell M(1,1,Nz) is to be read, the prior art uses read voltages VR5, VR10, VR12, and VR15 to read memory cell M(1,1,Nz), and the flash memory module only sends the top bit to the flash memory controller. For example, if the prior art flash memory module outputs the top bit "1" (i.e., the sign bit) to the flash memory controller, the flash memory controller only knows that memory cell M(1,1,Nz) has one of the states S0-S4, S10-S11, and S15, but the flash memory controller cannot know exactly which state memory cell M(1,1,Nz) has.

[0126] It should be noted that, although Figure 8 The use of the ramp signal as a read voltage VR has been demonstrated, but the invention is not limited thereto. In other embodiments, the control circuit 714 can apply read voltages VR with different voltage levels to the memory cell M(1,1,Nz) (i.e., read voltages VR with different voltage levels can be considered as multiple read voltages), each voltage level of the read voltage VR corresponding to a count value CNT, and the read voltages VR can have any other suitable design. In one embodiment, the number of voltage levels of the read voltage VR (or the number of read voltages) is equal to or greater than the number of states of the memory cell M(1,1,Nz).

[0127] In one embodiment, the sensing amplifier 700 further includes Figure 9The mapping circuit 910 is shown. Mapping circuit 910 is used to convert the count value into eight-bit information indicating the critical voltage or state of memory cell M(1,1,Nz), where four bits are the most significant bit (MSB) and the other four bits are the least significant bit (LSB). For example, count value "1" is mapped to eight-bit information (0,0,0,0,0,0,0,0,0), count value "2" is mapped to eight-bit information (0,0,0,0,0,0,0,1), count value "3" is mapped to eight-bit information (0,0,0,0,0,0,1,0), ..., count value "255" is mapped to eight-bit information (1,1,1,1,1,1,1,1,0), and count value "256" is mapped to eight-bit information (1,1,1,1,1,1,1,1,1). Figure 10 This is a schematic diagram illustrating states S0 to S15 and the corresponding plurality of most significant bits and plurality of least significant bits according to an embodiment of the present invention. Figure 10 In the illustrated embodiment, the plurality of most significant bits are used to indicate the state of the memory cell M(1,1,Nz), i.e., the most significant bit (0,0,0,0) represents state S0, the most significant bit (0,0,0,1) represents state S1, the most significant bit (0,0,1,0) represents state S2, ..., the most significant bit (1,1,1,0) represents state S14, and the most significant bit (1,1,1,1) represents state S15. Furthermore, the range defined by the plurality of most significant bits is further divided into sixteen sub-ranges represented by the plurality of least significant bits, and the plurality of least significant bits can act as the aforementioned soft bits.

[0128] In one embodiment, the flash memory module 120 can transmit the most significant bit and the least significant bit to the flash memory controller 110 in response to a read command received only once. (See reference...) Figure 11If the flash memory controller 110 wants to read data from a page (e.g., a logical page), the flash memory controller 110 sends a read command to the flash memory module 120, and the flash memory module 120 uses the above mechanism to read the memory cells of the page to generate the most significant bit and the least significant bit for each memory cell. Assuming that the page includes four sectors / chunks and each sector / chunk is an encoding / decoding unit, the flash memory module 120 can sequentially send the most significant bit of each memory cell in a first sector / chunk, the most significant bit of each memory cell in a second sector / chunk, the most significant bit of each memory cell in a third sector / chunk, and the most significant bit of each memory cell in a fourth sector / chunk to the flash memory controller 110 for subsequent de-randomization and decoding operations. After the most significant bit of all memory cells on the page has been transmitted to the flash memory controller 110, the flash memory module 120 begins to sequentially transmit the least significant bit of each memory cell in the first sector / block, the least significant bit of each memory cell in the second sector / block, the least significant bit of each memory cell in the third sector / block, and the least significant bit of each memory cell in the fourth sector / block to the flash memory controller 110 for subsequent de-randomization and decoding operations.

[0129] In the above embodiments, if the decoder 134 of the flash memory controller 110 can successfully decode data using only the most significant bits of the multiple memory cells of the page, the least significant bits of the multiple memory cells may not be used for decoding operations, or the flash memory controller 110 may notify the flash memory module 120 to stop transmitting the least significant bits.

[0130] In one embodiment, although the flash memory module 120 obtains the most significant bit and least significant bit of the plurality of memory cells in response to a read instruction from the flash memory controller 110, the flash memory module 120 does not automatically transmit the least significant bit of the plurality of memory cells to the flash memory controller 110 until the flash memory controller 110 requests the least significant bit of the plurality of memory cells (for example, the flash memory module 120 transmits the least significant bit of the plurality of memory cells to the flash memory controller 110 when the flash memory controller 110 requests the least significant bit of the plurality of memory cells).

[0131] Figure 12This is a flowchart illustrating a method for accessing a flash memory module 120 according to an embodiment of the present invention. In step 1200, the process begins, and the host device 50 and the memory device 100 are powered on. In step 1202, the flash memory controller 110 sends a read command to the flash memory module 120 and requests a page of data. In step 1204, the flash memory module 120 receives the read command and uses... Figures 7 to 10 The read mechanism shown reads all memory cells of the page and obtains the most significant bit and least significant bit of each memory cell. Assuming the page has multiple blocks, and each block is an encoding / decoding unit such as the aforementioned encoding / decoding unit, the flash memory module 120 sequentially transmits the most significant bit of each memory cell in a first block, the most significant bit of each memory cell in a second block, ..., and the most significant bit of each memory cell in a last block to the flash memory controller 110. In this embodiment, the most significant bit of each memory cell can be considered as state information indicating which state the memory cell has. In step 1206, during the sequential reception of data from the flash memory module 120, the flash memory controller 110 determines whether the multiple states of a portion of the memory cells are balanced or unbalanced to generate a determination result. If the determination result indicates that the multiple states of the multiple numbers ...

[0132] Specifically, since the most significant bit transmitted from the flash memory module 120 can be considered as a state of the memory cell, the flash memory controller 110 can accumulate the number of states S0 to S15 during the process of sequentially receiving the most significant bits of the plurality of memory cells. Ideally, since the data programmed into the flash memory module 120 is processed by the randomizer 136, the number of states S0 to S15 should be close to each other. For example, if the flash memory controller 110 receives the most significant bits of sixteen thousand (16K) memory cells from the flash memory module 120, the number of each of the sixteen thousand memory cells' states S0 to S15 should be approximately "1000". If the difference between the number of these states is within a defined range, the number of these states is judged to be balanced; if the difference between the number of these states is not within the defined range, the number of these states is judged to be unbalanced. For example, the flash memory controller 110 can establish Figure 13 The histogram shown. (As shown) Figure 13 As shown, ideally, states S0 to S15 have similar numbers, and if the page encounters problems such as data retention or read interference, the multiple memory cells will experience a critical value shift. Figure 13 In the example shown, state S15 is shifted to other states such as S12 to S14, so the sensing amplifier (e.g., sensing amplifier 700) will not sense state S15 from any memory cell, and such a critical value shift phenomenon results in an unbalanced number of states.

[0133] If the flash memory controller 110 determines that the number of states of the memory cells in the specified portion is balanced, the process proceeds to step 1208 and the decoder 134 decodes the data using the most significant bit of the memory cells belonging to a block (i.e., hard decoding). If the flash memory controller 110 determines that the number of states of the memory cells in the specified portion is unbalanced, the process proceeds to step 1210 and the flash memory controller 110 sends a signal to trigger the flash memory module 120 to transmit the least significant bit of the memory cells. After the flash memory module 120 reads the least significant bit of the memory cells, in step 1214, the decoder 134 decodes the data using the most significant bit and the least significant bit of the memory cells belonging to a block (i.e., soft decoding).

[0134] In step 1212, the decoder 134 is determined to have successfully decoded the data. If the decoder 134 successfully decodes the data, the process proceeds to step 1216 to end the read operation or begin the next read operation; if the decoder 134 fails to decode the data, the process proceeds to step 1210 to send the signal to trigger the flash memory module 120 to send the least significant bit of the plurality of memory cells.

[0135] exist Figure 12 In the flowchart shown, if the number of states of the memory cells in the specified portion is determined to be balanced, the flash memory controller 110 can directly perform hard decoding on the most significant bit of the memory cells. The least significant bit of the memory cells temporarily stored in the flash memory module 120 is only transmitted to the flash memory controller 110 if the hard decoding operation fails. Therefore, this invention avoids unnecessary data transmission to save bandwidth and power. Furthermore, if the number of states of the memory cells in the specified portion is determined to be unbalanced, the flash memory controller 110 can directly perform soft decoding on the most significant and least significant bits of the memory cells without first performing the hard decoding operation, thus avoiding wasting power and time on high-failure-rate hard decoding operations.

[0136] It should be noted that the details of the above-mentioned hardware decoding operation and software decoding operation are well known to those skilled in the art, and the detailed steps of the above-mentioned hardware decoding operation and software decoding operation are not the subject of this invention, so they will not be described in detail hereafter.

[0137] Figure 14 This is a schematic diagram of a sensing amplifier 1400 according to a second embodiment of the present invention. Figure 14 In this embodiment, the sensing amplifier 1400 includes an operational amplifier 1410, a voltage source 1412, a digital-to-analog converter 1414, and a switch SW1. The sensing amplifier 1400 is used to read... Figure 1 The memory cell M(1,1,Nz) is shown corresponding to bit line BL(1) and word line WL(1,Nz). When memory cell M(1,1,Nz) is to be read, analog-to-digital converter 1414 is used to generate read voltage VR. Figure 1 The memory cell M(1,1,Nz) is shown, while other memory cells M(1,1,1) to M(1,1,(Nz-1)) are controlled to be conductive.

[0138] Please refer to the above. Figure 14 as well as Figure 15 , Figure 15This is a timing diagram of certain signals of a sense amplifier 1400 according to an embodiment of the present invention. During the operation of the sense amplifier 1400, the digital-to-analog converter 1414 is initially not in operation and the read voltage VR is initially equal to zero (i.e., the memory cell M(1,1,Nz) is disabled). Switch SW1 is controlled to connect bit line BL(1) to voltage source 1412, and voltage source 1412 begins to charge parasitic capacitance CBL such that the voltage VBL at one terminal of parasitic capacitance CBL is equal to the voltage Vpre provided by voltage source 1412 at time T0. Then, at time T1, switch SW1 is controlled to connect bit line BL(1) to the negative terminal of operational amplifier 1410, and digital-to-analog converter 1414 begins to generate a ramp signal acting as the read voltage VR to word line WL(1,Nz) according to the consistency energy signal DAC_EN to control memory cell M(1,1,Nz). For example, suppose memory cell M(1,1,Nz) stores data corresponding to state S8 (its critical voltage is approximately 3V). When the read voltage VR starts to rise from 0V to 3V, memory cell M(1,1,Nz) cannot be enabled because the read voltage VR is not high enough. The voltage VBL remains at voltage Vpre. Since voltage VBL / Vpre is greater than the reference voltage Vsen at the positive terminal of operational amplifier 1410, the output signal Vout generated by operational amplifier 1410 is equal to "0". When the read voltage VR is greater than the critical voltage of memory cell M(1,1,Nz) at time T2, memory cell M(1,1,Nz) is enabled to generate a current I_cell to discharge the parasitic capacitance CBL, and voltage VBL decreases. When voltage VBL decreases and becomes lower than the reference voltage Vsen, output signal Vout becomes "1" to trigger digital-to-analog converter 1414 to output a digital value corresponding to the current read voltage VR.

[0139] It should be noted that, although Figure 15 The use of the ramp signal as a read voltage VR has been demonstrated, but the invention is not limited thereto. In other embodiments, the digital-to-analog converter 1414 can apply read voltages VR with different voltage levels to memory cells M(1,1,Nz) (i.e., read voltages VR with different voltage levels can be considered as multiple read voltages), and the read voltages VR can have any other suitable design. In one embodiment, the number of voltage levels (or the number of read voltages) of the read voltage VR is equal to or greater than the number of states of the memory cells M(1,1,Nz).

[0140] exist Figure 14 and Figure 15In the illustrated embodiment, the digital value output by the digital-to-analog converter 1414 can represent the critical voltage of the memory cell M(1,1,Nz) (i.e., the analog voltage corresponding to the digital value output by the digital-to-analog converter 1414 is very close to the critical voltage of the memory cell M(1,1,Nz), so the digital value can be effectively used for subsequent decoding operations. Furthermore, assuming the digital-to-analog converter 1414 is an eight-bit digital-to-analog converter, the digital value may have… Figure 10 The four most significant bits and four least significant bits are shown, and the flash memory module 120 can directly transmit the digital value (i.e., the multiple most significant bits and multiple least significant bits) to the flash memory controller 110 with a single read instruction. A timing diagram for transmitting the read instruction and the multiple most significant bits / least significant bits can be found in [reference needed]. Figure 11 Furthermore, due to circuit delay and discharge time, the digital value output by the digital-to-analog converter 1414 can be slightly adjusted so that the adjusted digital value is closer to the critical voltage of the memory cell M(1,1,Nz).

[0141] The above embodiment uses a fourth-order cell block as an example; however, the above reading mechanism can also be applied to third-order cell blocks, multi-order cell blocks, and single-order cell blocks. Those skilled in this art should be able to understand how to use the above steps to read memory cells in third-order cell blocks, multi-order cell blocks, and single-order cell blocks; other details are not elaborated here.

[0142] In summary, in the flash memory controller and flash memory module of the present invention, the flash memory module can output multiple bits of information of each memory cell to the flash memory controller in response to a read instruction, and the multiple bits of information of each memory cell can indicate the critical voltage or state of the memory cell. Therefore, the read efficiency can be significantly improved. Furthermore, in the decoding operation of the flash memory controller, the decoder can determine whether the multiple quantities of the multiple states are balanced or unbalanced to employ different decoding mechanisms, thereby improving decoding efficiency.

[0143] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A flash memory controller, wherein the flash memory controller is coupled to a flash memory module, the flash memory module including at least one flash memory chip, each flash memory chip including a plurality of blocks, each block including a plurality of pages, and the flash memory controller is characterized in that it includes: A memory used to store program code; as well as A microprocessor is used to execute the program code to access the flash memory module via a control logic; After the microprocessor sends a read instruction to the flash memory module to request data on at least one memory cell, the control logic determines whether the difference between the number of states of multiple memory cells in the at least one memory cell is within a predetermined range, and generates a determination result. If the determination result indicates that the difference is not within the predetermined range, the control logic receives multiple first specific locations and multiple second specific locations read from the multiple memory cells of the at least one memory cell, and a decoder in the control logic uses a second decoding method to decode using the multiple first specific locations and the multiple second specific locations. If the determination result indicates that the difference is within the predetermined range, the control logic only receives the multiple first specific locations read from the multiple memory cells of the at least one memory cell, and the decoder uses a first decoding method to decode using the multiple first specific locations. Each memory cell of the at least one memory unit is used to store multiple bits, and the multiple states are used to indicate different combinations of the multiple bits, and each memory cell has only one state.

2. The flash memory controller as described in claim 1, characterized in that, The control logic receives the state information of the plurality of memory cells from the flash memory module, and the state information includes the number of each state of the plurality of memory cells.

3. The flash memory controller as described in claim 1, characterized in that, The first decoding method is a hardware decoding method, and the second decoding method is a software decoding method.

4. The flash memory controller as claimed in claim 1, characterized in that, Each state is divided into multiple sub-ranges, and the multiple second features are soft information indicating which sub-range of the state the memory cell possesses.

5. The flash memory controller as claimed in claim 1, characterized in that, If the determination result indicates that the difference is not within the predetermined range, the decoder directly uses the second decoding method to decode the data by using the plurality of first specific locations and the plurality of second specific locations received from the flash memory module, without using the first decoding method.

6. The flash memory controller as claimed in claim 1, characterized in that, If the determination result indicates that the difference is not within the predetermined range, the control logic sends a signal to trigger the flash memory module to transmit the plurality of second features to the flash memory controller. Then, the decoder uses the second decoding method to decode the data by using the plurality of first features and the plurality of second features received from the flash memory module.

7. The flash memory controller as claimed in claim 1, characterized in that, If the decoder is unable to decode the data using the first decoding method, the control logic sends a signal to trigger the flash memory module to transmit the plurality of second features to the flash memory controller. Then, the decoder uses the second decoding method to decode the data by using the plurality of first features and the plurality of second features received from the flash memory module.

8. A method for accessing a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: A flash memory controller is used to send a read command to the flash memory module to request data on at least one memory cell; A control logic is used to determine whether the difference between the number of states of multiple memory cells in the at least one memory unit is within a predetermined range, so as to generate a determination result; if the determination result indicates that the difference is not within the predetermined range, the control logic receives multiple first specific locations and multiple second specific locations read from the multiple memory cells of the at least one memory unit, and a decoder in the control logic uses a second decoding method to decode using the multiple first specific locations and the multiple second specific locations; as well as If the determination result indicates that the difference is within the predetermined range, then the control logic only receives the plurality of first specific locations read from the plurality of memory cells of the at least one memory unit, and the decoder uses a first decoding method to decode using the plurality of first specific locations; Each memory cell of the at least one memory unit is used to store multiple bits, and the multiple states are used to indicate different combinations of the multiple bits, and each memory cell has only one state.

9. The method as described in claim 8, characterized in that, Also includes: The flash memory module receives state information from the plurality of memory cells, and the state information includes the number of each state of the plurality of memory cells.

10. The method as described in claim 8, characterized in that, The first decoding method is a hardware decoding method, and the second decoding method is a software decoding method.

11. The method as described in claim 8, characterized in that, Each state is divided into multiple sub-ranges, and the multiple second features are soft information indicating which sub-range of the state the memory cell possesses.

12. The method as described in claim 8, characterized in that, Also includes: If the determination result indicates that the difference is not within the predetermined range, the decoder directly uses the second decoding method to decode the data by using the plurality of first specific locations and the plurality of second specific locations received from the flash memory module, without using the first decoding method.

13. The method as described in claim 8, characterized in that, Also includes: If the determination result indicates that the difference is not within the predetermined range, the control logic sends a signal to trigger the flash memory module to transmit the plurality of second features to the flash memory controller, and then uses the decoder to use the second decoding method to decode the data by using the plurality of first features and the plurality of second features received from the flash memory module.

14. The method as described in claim 8, characterized in that, Also includes: If the decoder cannot decode the data using the first decoding method, the control logic sends a signal to trigger the flash module to transmit the plurality of second features to the flash controller; and The decoder uses the second decoding method to decode the data by using the plurality of first specific positions and the plurality of second specific positions received from the flash memory module.

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