Display device

Abstract

A display device is provided, including: a display panel including a display area and a peripheral area; a printed circuit board attached to the peripheral area and including a ground portion and a test electrode spaced apart from the ground portion; a connector including a plurality of connector terminals connected to an external control device and electrically connecting the printed circuit board and the external control device to each other; and a cover layer disposed on the printed circuit board and covering at least a portion of the printed circuit board. Accordingly, not only the reliability of the display quality and the electrical characteristics of the display device is improved, but also the loss during the manufacturing process is reduced and the yield is improved.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0093306, filed on July 27, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a display device including a printed circuit board. Background Technology

[0004] Mobile electronic devices are already widely used. Recently, in addition to small electronic devices such as mobile phones, tablet PCs have also been widely used as mobile electronic devices.

[0005] Such mobile electronic devices include display devices to provide users with various functions, such as visual information like images or videos. Recently, with the miniaturization of components used to drive the display devices, the area occupied by the display devices in electronic devices has gradually increased, and therefore, display devices with various characteristics and functions have been developed.

[0006] The display device may include a display panel, which includes a display area and a peripheral area. A drive unit, a printed circuit board, and the like for driving the display panel may be arranged in the peripheral area of ​​the display panel. Since the printed circuit board is configured to transmit electrical signals applied from an external control device to the drive unit, it may be appropriately protected from electromagnetic interference (EMI) and electrostatic discharge (ESD) to ensure the display quality and reliability of the display device. Summary of the Invention

[0007] A display device is provided in which display quality and electrical characteristic reliability are improved not only by reducing the effects of electromagnetic interference (EMI) and electrostatic discharge (ESD), but also by reducing losses and increasing product yield during the manufacturing process. However, the scope of this disclosure is not limited thereto.

[0008] Additional aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0009] According to one or more embodiments, a display device includes a display panel including a display area and a peripheral area; a printed circuit board attached to the peripheral area and including a ground portion and a test electrode spaced apart from the ground portion; a connector including a plurality of connector terminals for electrically connecting the printed circuit board and an external control device to each other; and a cover layer on at least a portion of the printed circuit board and covering the at least a portion of the printed circuit board.

[0010] The cover layer can overlap the ground portion and the test electrode.

[0011] The cover layer can be connected to the ground portion and the test electrode.

[0012] The cover layer can include a conductive material.

[0013] The cover layer can include a metal layer.

[0014] The cover layer can include a conductive fiber.

[0015] One of the plurality of connector terminals can be electrically connected to the test electrode.

[0016] Another of the plurality of connector terminals can be electrically connected to the ground portion.

[0017] The test electrode, the cover layer, and the ground portion can form a current path for a current applied to the one connector terminal.

[0018] The printed circuit board can further include first and second terminals electrically connected to the test electrode and the ground portion, respectively.

[0019] The first and second terminals can not overlap the cover layer.

[0020] The test electrode, the cover layer, and the ground portion can form a current path through which a current applied to the first terminal flows.

[0021] According to one or more embodiments, a display device includes a display panel including a pixel circuit; a driver integrated circuit configured to apply an electrical signal to the pixel circuit; a printed circuit board electrically connected to the driver integrated circuit and including a ground portion and a test electrode spaced apart from the ground portion; a connector connected to one side of the printed circuit board and including a plurality of connector terminals for connection to an external control device; and a conductive layer on at least a portion of the printed circuit board and covering the at least a portion of the printed circuit board, wherein the ground portion is configured to receive a current applied to the test electrode via the conductive layer.

[0022] The conductive layer can overlap the ground portion and the test electrode.

[0023] The conductive layer can be connected to the ground portion and the test electrode.

[0024] One of the plurality of connector terminals can be electrically connected to the test electrode.

[0025] Another of the plurality of connector terminals can be electrically connected to the ground portion.

[0026] The conductive layer can include a conductive fiber or a metal layer including copper (Cu).

[0027] The printed circuit board can further include first and second terminals electrically connected to the test electrode and the ground portion, respectively.

[0028] The test electrode, the conductive layer, and the ground portion can form a current path through which a current applied to the first terminal flows.

[0029] Additional aspects, features, and advantages will be apparent from the detailed description of the disclosure that follows, taken in conjunction with the accompanying drawings and the appended claims.

[0030] These general and specific aspects can be implemented using a system, a method, a computer program, or any combination of a system, a method, and a computer program. BRIEF DESCRIPTION OF DRAWINGS

[0031] The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a plan view of a display device according to some embodiments;

[0033] Figure 2 is an equivalent circuit diagram of one pixel circuit of a display device according to some embodiments;

[0034] Figure 3 is a cross-sectional view of a portion of the display device of Figure 1

[0035] Figure 4 is a perspective view of a portion of the display device according to some embodiments;

[0036] Figure 5 is an exploded perspective view of a portion of the display device of Figure 4

[0037] Figure 6 is a perspective view of a portion of the display device according to other embodiments; and

[0038] Figure 7 ​​is a portion of a display device according to some embodiments Figure 6 exploded perspective view of a portion of a display device. DETAILED DESCRIPTION

[0039] Aspects of some embodiments of the present disclosure and methods of implementing the same can be understood more readily by reference to the following detailed description of embodiments and the accompanying drawings. In the following detailed description of embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration embodiments in which aspects of the disclosure can be practiced. However, it is to be understood that other embodiments can be utilized and that not all of the noted aspects of the present disclosure can be utilized. Moreover, the illustrated embodiments can be combined. Furthermore, the described embodiments can be implemented in the absence of any of the following, unless otherwise stated. It is to be understood that other hardware and software configurations can also be utilized, and that the described embodiments are not necessarily comprised of all of the components shown in the figures.

[0040] Unless otherwise indicated, like references, characters or combinations thereof in the entire specification and drawings mean the same or similar elements, and thus the description will not be repeated. Also, portions of the description that are related with the description of the embodiments can not be shown to make the description clear. In the drawings, the relative sizes of the elements, layers, and regions can be exaggerated for clarity. Also, the use of cross-hatching and / or shading in the drawings is generally provided to illustrate the boundaries of regions or areas, for purposes of clarity. Thus, unless specifically stated otherwise, the presence of cross-hatching or shading in a drawing is not indicative of any preference or requirement for any particular material, material property, dimension, ratio, commonality of any particular feature between illustrations, and / or any other characteristic, attribute, property, or requirement.

[0041] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and / or intermediate structures being utilized in the manufacture of embodiments (e.g., to explain manufacturing processes, or the like). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Additionally, the particular structural and functional configurations shown in the illustrations are exemplary embodiments and are not intended to limit the scope of the disclosure. Thus, the embodiments disclosed herein are not to be interpreted as being limited to the particular configurations illustrated. For example, the embodiments can be implemented in a variety of different configurations.

[0042] For example, an implant region shown as a rectangle will typically have rounded or curved features at its edges and / or a gradient of implant concentration, rather than a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which implantation occurs. Thus, the regions shown in the figures are illustrative in nature and their shapes are not intended to show the actual shape of a region of a device and are not intended to be limiting. Moreover, as will be appreciated by those skilled in the art, the described implementations can be modified in various different ways without departing from the spirit and scope of the disclosure.

[0043] In the detailed description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various implementations. It will be apparent, however, that various implementations can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily complicating the various implementations.

[0044] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“a first element,”“a first component,”“a first region,”“a first layer,” or“a first section” described below could be termed a“second element,”“a second component,”“a second region,”“a second layer,” or“a second section,” without departing from the spirit and scope of the disclosure.

[0045] For ease of illustration, spatial relative terms, such as“beneath,”“below,”“lower,”“under,”“above,”“upper,” and the like, can be used herein to describe one element’s or feature’s relationship to another element (or elements) or feature (or features) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as“below” or“beneath” or“under” other elements or features would then be oriented“above” the other elements or features. Thus, the exemplary term“below” can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first part is described as being“on” a second part, this means that the first part is disposed on the upper side or lower side of the second part, without being limited to a gravity-based orientation of the upper side.

[0046] Also, in the present specification, the phrase "on plane" or "plan view" means to view a target portion from the top, and the phrase "on cross section" means to view a cross section formed by cutting a target portion vertically from the side.

[0047] It will be understood that when an element, layer, region or component is referred to as being "on" or "connected to" or "coupled to" another element, layer, region or component, it can be directly on, connected or coupled to the other element, layer, region or component or intervening elements, layers, regions or components can be present. In contrast, when an element, layer, region or component is referred to as being "directly on" or "directly connected to" or "directly coupled to" another element, layer, region or component, there are no intervening elements, layers, regions or components present. Also, it will be understood that when an element is referred to as being "between" two other elements, it can be the only element between the two other elements or one or more intervening elements can also be present. In contrast, when an element is referred to as being "directly between" two other elements, there are no intervening elements present.

[0048] For purposes of the present disclosure, expressions such as "at least one of... " when following a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one of X, Y, and Z" are each to be construed as X alone, Y alone, Z alone, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, expressions such as "at least one of A and B" can include A, B, or A and B. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "A and / or B" can include A, B, or A and B.

[0049] In examples, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" "comprising," "has" "having," "includes" and "including" when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0051] As used herein, the terms "substantially," "approximately," "about," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. As used herein, "about" or "approximately" includes the stated value and a range of values acceptable as measured by one of ordinary skill in the art considering the measurement and error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5% of the stated value. Additionally, "may" as used in describing the embodiments of the present disclosure indicates "one or more embodiments of the present disclosure."

[0052] When one or more embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described consecutively can be performed substantially simultaneously, or in the reverse order of the described sequence.

[0053] The electronic device or electric device and / or any other related device or component according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on one integrated circuit (IC) chip or on separate IC chips. In addition, various components of these devices can be implemented on a flexible printed circuit film, tape carrier package (TCP), printed circuit board (PCB), or formed on one substrate.

[0054] In addition, various components of these devices can be processes or threads running on one or more processors in one or more computing devices executing computer program instructions and interacting with other system components for performing various functions described herein. The computer program instructions are stored in memory which can be implemented using any suitable storage device, such as, for example, random access memory (RAM), and the like. The computer program instructions can also be stored in other non-transitory computer-readable media, such as, for example, a CD-ROM, a flash drive, and the like. In addition, those skilled in the art should appreciate that functions of various computing devices can be combined or integrated into a single computing device, or functions of a particular computing device can be distributed across one or more other computing devices, without departing from the spirit and scope of embodiments of the present disclosure.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0056] Figure 1 is a plan view of a display device 1 according to some embodiments.

[0057] Referring to Figure 1 The display device 1 can include a display panel 10, a driver integrated circuit 20, a printed circuit board (PCB) 30, a connector 40, and an external control device 50.

[0058] The display panel 10 can include a display area DA and a peripheral area PA located outside the display area DA. The display panel 10 can provide an image via an array of pixels PX arranged in the display area DA. Each of the pixels PX can include an emission element for emitting a specific light (e.g., red light, green light, or blue light), and the display panel 10 can provide an image by using light emitted through the emission element.

[0059] According to some embodiments, the display area DA can be a rectangle having a longer length in the ±y direction. Alternatively, the display area DA can be a polygon such as a rectangle having a longer length in the ±x direction, or a square, or can be an ellipse or a circle.

[0060] The peripheral area PA can be an area in which an image is not provided, and can be a non-display area. The peripheral area PA can completely or partially surround the display area DA. The driver integrated circuit 20 can be disposed in the peripheral area PA. The driver integrated circuit 20 can be mounted on the display panel 10 in a chip on glass (CoG) manner, a chip on film (CoF) manner, or a chip on plastic (CoP) manner. The driver integrated circuit 20 generates an electrical signal in response to a power supply and a signal received from an external source, and provides the electrical signal to each of the pixel circuits PC arranged in the display area DA. Figure 2

[0061] In addition, a pad portion PAD electrically connected to the driver integrated circuit 20 via a wire or via a conductive layer can be arranged in the peripheral area PA. The PCB 30 can be attached on the pad portion PAD of the peripheral area PA. In other words, the PCB 30 can be electrically connected to the driver integrated circuit 20 via the pad portion PAD. The PCB 30 can be attached to the pad portion PAD by an adhesive member such as an anisotropic conductive film (ACF).

[0062] The connector 40 can be connected to or mounted on one side of the PCB 30. The PCB 30 can be electrically connected to the external control device 50 via the connector 40. The external control device 50 can be, for example, an application processor (AP), and can include an external power supply unit for supplying a power supply. The PCB 30 can access the external control device 50 to deliver a control signal and / or a power supply received from the external control device 50 to the driver integrated circuit 20 and the display panel 10. According to some embodiments, the PCB 30 can be a flexible PCB (FPCB) having a flexible characteristic. The FPCB can be bent or curved, and can overlap at least a partial area of the display panel 10 by being bent under a rear surface of the display panel 10, for example, can overlap at least a partial area of the display panel 10 in the z direction.

[0063] Although in the above description, the display panel 10 is described as being bent in the x direction, the display panel 10 can be bent in the y direction. Figure 1 ​The lengths of the driver integrated circuit 20 and the PCB 30 in the ±x direction are each shown to be the same as the length of the display area DA in the ±x direction, but the lengths of the driver integrated circuit 20 and the PCB 30 are not limited thereto and can be different from each other. For example, the lengths of the driver integrated circuit 20 and the PCB 30 in the ±x direction can each be smaller than the length of the display area DA in the ±x direction.

[0064] Figure 2 is an equivalent circuit diagram of one pixel circuit PC included in a display device according to some embodiments.

[0065] Referring to Figure 2 , Figure 1 The display device 1 of Equation Figure 1 The pixel PX of Equation

[0066] The pixel circuit PC can include a storage capacitor and a plurality of thin film transistors. According to some embodiments, the pixel circuit PC can include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cap.

[0067] The second thin film transistor T2 is a switching thin film transistor connected to a scan line SL and a data line DL, and can be configured to transfer a data voltage (or a data signal) input from the data line DL to the first thin film transistor T1 based on a switching voltage (or a switching signal) input from the scan line SL.

[0068] The storage capacitor Cap is connected to the second thin film transistor T2 and a driving voltage line PL, and can store a voltage corresponding to a difference between a voltage received from the second thin film transistor T2 and a first power voltage ELVDD supplied to the driving voltage line PL. The storage capacitor Cap can include at least a first capacitor plate CE1 and a second capacitor plate CE2.

[0069] The first thin film transistor T1 is a driving thin film transistor connected to the driving voltage line PL and the storage capacitor Cap, and can control a driving current flowing through the organic light emitting diode OLED from the driving voltage line PL in response to a voltage value stored in the storage capacitor Cap. The organic light emitting diode OLED can emit light of a certain brightness according to the driving current. An opposite electrode (e.g., a cathode) of the organic light emitting diode OLED can receive a second power voltage ELVSS.

[0070] In Figure 2In the embodiment, the pixel circuit PC includes two thin film transistors T1 and T2 and one storage capacitor Cap, but the present disclosure is not limited thereto. For example, the pixel circuit PC can include three or more thin film transistors and / or two or more storage capacitors. According to some embodiments, the pixel circuit PC can include seven thin film transistors and one storage capacitor. The number of thin film transistors and storage capacitors can vary depending on the design of the pixel circuit PC. However, for ease of description, a case in which the pixel circuit PC includes two thin film transistors and one storage capacitor will be described hereinafter.

[0071] Figure 3 is a cross-sectional view of a portion of the display device 1 and can correspond to a cross-section taken along line III-III' of Figure 1 Figure 1

[0072] Referring to Figure 3 The substrate 100 can have a multi-layer structure including an inorganic layer and a base layer including a polymer resin. For example, the substrate 100 can include a barrier layer of an inorganic insulating layer and a base layer including a polymer resin. For example, the substrate 100 can include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104, which are sequentially stacked. The first base layer 101 and the second base layer 103 can include polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The first barrier layer 102 and the second barrier layer 104 can include an inorganic insulating material such as silicon oxide, silicon oxynitride, and / or silicon nitride.

[0073] A buffer layer 111 can be disposed on the substrate 100. The buffer layer 111 can reduce or prevent penetration of foreign materials, moisture, or ambient air from a bottom portion of the substrate 100, and can provide a flat surface on the substrate 100. The buffer layer 111 can include an inorganic insulating material such as silicon oxide, silicon oxynitride, or silicon nitride, and can have a single-layer structure or a multi-layer structure including such a material.

[0074] The pixel circuit PC can be disposed on the buffer layer 111. The pixel circuit PC can include a thin film transistor TFT and a storage capacitor Cap.

[0075] ​​The thin film transistor TFT can include a semiconductor layer Act, a gate electrode GE overlapping a channel region of the semiconductor layer Act, and a source electrode SE and a drain electrode DE connected to a source region and a drain region of the semiconductor layer Act, respectively. The first gate insulating layer 112 can be between the semiconductor layer Act and the gate electrode GE, and the second gate insulating layer 113 and the interlayer insulating layer 114 can be between the gate electrode GE and the source electrode SE and / or between the gate electrode GE and the drain electrode DE. The first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114 can constitute a stacked structure of the insulating layer IL.

[0076] The storage capacitor Cap can overlap the thin film transistor TFT. The storage capacitor Cap can include a first capacitor plate CE1 and a second capacitor plate CE2 overlapping each other. According to some embodiments, the gate electrode GE of the thin film transistor TFT can include the first capacitor plate CE1 of the storage capacitor Cap. The second gate insulating layer 113 can be between the first capacitor plate CE1 and the second capacitor plate CE2.

[0077] The semiconductor layer Act can include polysilicon. According to some embodiments, the semiconductor layer Act can include amorphous silicon. According to some embodiments, the semiconductor layer Act can include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer Act can include a channel region, and a source region and a drain region doped with impurities.

[0078] The first gate insulating layer 112 can include an inorganic insulating material such as silicon oxide, silicon nitride oxide, or silicon nitride, and can have a single-layer structure or a multi-layer structure including such a material.

[0079] The gate electrode GE or the first capacitor plate CE1 can include a low-resistance conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and can have a single-layer structure or a multi-layer structure including such a material.

[0080] The second gate insulating layer 113 can include an inorganic insulating material such as silicon oxide, silicon nitride oxide, or silicon nitride, and can have a single-layer structure or a multi-layer structure including such a material.

[0081] The second capacitor plate CE2 can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and can have a single-layer structure or a multi-layer structure including such a material.

[0082] The interlayer insulating layer 114 can include an inorganic insulating material such as silicon oxide, silicon oxynitride, or silicon nitride, and can have a single-layer structure or a multi-layer structure including such a material.

[0083] The source electrode SE or the drain electrode DE can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and can have a single-layer structure or a multi-layer structure including such a material. For example, the source electrode SE or the drain electrode DE can have a three-layer structure of a titanium layer / aluminum layer / titanium layer.

[0084] The planarization layer 115 can be disposed on the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114. The planarization layer 115 can be arranged on the thin film transistor TFT of the pixel circuit PC. For example, the planarization layer 115 can be between the thin film transistor TFT of the pixel circuit PC and the pixel electrode 210. The planarization layer 115 can include an organic insulating material. The planarization layer 115 can include an organic insulating material such as acrylic, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). The organic insulating material of the planarization layer 115 can be a photosensitive organic insulating material.

[0085] The pixel electrode 210 can be arranged on the planarization layer 115. The pixel electrode 210 can be electrically connected to the pixel circuit PC via a contact hole in the planarization layer 115.

[0086] The pixel electrode 210 can include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. The pixel electrode 210 can include a reflective layer including such a material, and a transparent conductive layer above and / or below the reflective layer. The transparent conductive layer can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). According to some embodiments, the pixel electrode 210 can have a three-layer structure of an ITO layer / Ag layer / ITO layer stacked in order.

[0087] The pixel defining layer 117 can be arranged on the pixel electrode 210. The pixel defining layer 117 can include an opening 117OP that covers an edge of the pixel electrode 210 and overlaps with a central portion of the pixel electrode 210.

[0088] The pixel definition layer 117 can increase the distance between the edge of the pixel electrode 210 and the counter electrode 230 on the pixel electrode 210, thereby reducing or preventing the possibility of an arc occurring at the edge of the pixel electrode 210. The pixel definition layer 117 can be formed via a method such as spin coating using an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, HMDSO, or phenol resin.

[0089] The intermediate layer 220 is disposed on the pixel definition layer 117 to correspond to the pixel electrode 210. The intermediate layer 220 can include a high molecular weight organic material or a low molecular weight organic material that emits light of a specific color.

[0090] The counter electrode 230 is disposed on the intermediate layer 220. The counter electrode 230 can include a conductive material having a relatively low work function. For example, the counter electrode 230 can include a (semi-)transparent layer including Ag, Mg, Al, Ni, Cr, Li, Ca, or an alloy thereof. The counter electrode 230 can also include a layer including ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including such a material. According to some embodiments, the counter electrode 230 can include Ag and Mg.

[0091] The stacked structure of the pixel electrode 210, the intermediate layer 220, and the counter electrode 230 can form a light emitting diode, e.g., an organic light emitting diode OLED. The organic light emitting diode OLED can emit red light, green light, or blue light, and the emission area of each organic light emitting diode OLED can correspond to a pixel PX. Since the openings 117OP of the pixel definition layer 117 define the size and / or width of the emission area, the size and / or width of the pixel PX depends on the size and / or width of the corresponding openings 117OP of the pixel definition layer 117.

[0092] A capping layer 250 can be disposed on the counter electrode 230. The capping layer 250 can include lithium fluoride (LiF). Alternatively, the capping layer 250 can include an inorganic insulating material such as silicon nitride, and / or can include an organic insulating material. According to some embodiments, the capping layer 250 can be omitted.

[0093] A thin film encapsulation layer 300 can be arranged on the capping layer 250. The organic light emitting diode OLED can be covered by the thin film encapsulation layer 300. The thin film encapsulation layer 300 can include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 therebetween.

[0094] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can each include at least one inorganic insulating material. The inorganic insulating material can include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can be formed via a chemical vapor deposition method.

[0095] The organic encapsulation layer 320 can include a polymer-based material. Examples of the polymer-based material can include an acrylic resin, an epoxy resin, a polyimide, and / or a polyethylene. For example, the organic encapsulation layer 320 can include an acrylic resin such as polymethyl methacrylate, polyacrylic acid, or the like. The organic encapsulation layer 320 can be formed by curing or applying a polymer.

[0096] In other embodiments, an outer coating layer and an optical functional layer such as a touch input layer, an anti-reflection layer, and / or a color filter layer can be disposed on the thin film encapsulation layer 300.

[0097] Figure 4 is a perspective view of a portion of a display device according to some embodiments, in which a PCB 30 and its peripheral components are mainly extracted from the display device.

[0098] Reference Figure 4 The PCB 30 can include a circuit pattern portion 31. The circuit pattern portion 31 can include a circuit pattern configured to transmit a signal and / or a power from an external control device to the driver integrated circuit 20 of the display device 1. In addition, electronic devices including transistors, semiconductor chips, resistors, capacitors, condensers, inductors, and the like can be mounted on the circuit pattern portion 31. Figure 1

[0099] The PCB 30 can include a ground portion 32. For example, the ground portion 32 can be a portion of the circuit pattern portion 31. The ground portion 32 can be connected to a ground of the display device 1 (see Figure 1 ) and configured to provide a reference potential for determining whether the PCB 30 along with the devices mounted on the PCB 30 are working.

[0100] The PCB 30 can include a test electrode 33. The test electrode 33 can be spaced apart from the ground portion 32. Thus, the test electrode 33 can not be directly electrically connected to the circuit pattern portion 31 and the ground portion 32. However, as will be described below, the test electrode 33 can be indirectly electrically connected to the circuit pattern portion 31 and the ground portion 32 through the cover layer 60.

[0101] ​For example, the circuit pattern portion 31, the ground portion 32, and the test electrode 33 can be disposed on the same layer, or can be disposed on different layers. Hereinafter, a case in which the circuit pattern portion 31, the ground portion 32, and the test electrode 33 are disposed on the same layer will be mainly described for convenience of description.

[0102] The circuit pattern portion 31, the ground portion 32, and the test electrode 33 can be formed by patterning a metal layer. For example, a metal layer can be first formed on a substrate of the PCB 30, and the metal layer can be patterned via an exposure, development, and separation process to form the circuit pattern portion 31, the ground portion 32, and the test electrode 33. The metal layer can include a metal material such as Cu having a high electrical conductivity. Various circuit formation methods such as a subtractive method using a dry film, a semi-additive process (SAP) method, and a plasma semi-additive process (PSAP) method can be applied to the exposure, development, and separation process.

[0103] Next, a protective layer can be formed on the metal layer, and the protective layer can include an insulating material. The protective layer can include an opening so that one surface of the ground portion 32 and one surface of the test electrode 33 are exposed. Accordingly, the respective surfaces of the ground portion 32 and the test electrode 33 and one surface of the protective layer can form a stepped portion. The opening can be formed via, for example, laser drilling or computer numerical control (CNC) drilling.

[0104] The circuit pattern portion 31 among the patterned metal layer on the substrate of the PCB 30 is covered by the protective layer of the PCB 30, and the ground portion 32 and the test electrode 33 are exposed through the opening of the protective layer. Figure 4 In the middle, the area of the circuit pattern portion 31 is shown in a dashed line. However, since the ground portion 32 and the test electrode 33 are exposed through the opening of the protective layer, the ground portion 32 and the test electrode 33 are shown in the middle. Figure 4

[0105] Meanwhile, for convenience of illustration, the substrate of the PCB 30, the metal layer, and the protective layer are shown as one assembly as a whole.

[0106] The connector 40 can be connected to one side of the PCB 30. For example, the connector 40 and the PCB 30 can be integrally formed. As another example, the connector 40 and the PCB 30 can be independently formed, and the connector 40 can be mounted on one side of the PCB 30. One end of the connector 40 can be electrically connected to the PCB 30, and the other end thereof can be electrically connected to an external control device. In other words, the connector 40 can electrically connect the PCB 30 and the external control device.

[0107] ​A plurality of connector terminals 41 can be provided in the other end of the connector 40. The plurality of connector terminals 41 can enable access to an external control device. Different electrical signals can be transmitted via the plurality of connector terminals 41, respectively, or the same electrical signal can be transmitted via the plurality of connector terminals 41.

[0108] Each of the plurality of connector terminals 41 can be electrically connected to the circuit pattern portion 31 of the PCB 30 via a wire. According to some embodiments, among the plurality of connector terminals 41, a first connector terminal 41a can be electrically connected to the ground portion 32 of the PCB 30 via a first wire CL1, and a second connector terminal 41b can be electrically connected to the test electrode 33 of the PCB 30 via a second wire CL2. The plurality of connector terminals 41 and the wires can include a metal material such as Cu having high electrical conductivity in a manner similar to the circuit pattern portion 31, the ground portion 32, and the test electrode 33.

[0109] The display device 1 according to some embodiments of Figure 1 The display device 1 according to some embodiments of

[0110] The cover layer 60 is an electrically conductive layer and can include an electrically conductive material. According to some embodiments, the cover layer 60 can be a metal layer including a metal material such as Cu having high electrical conductivity. According to other embodiments, the cover layer 60 can include electrically conductive fibers, which can be, for example, fibers coated with Ni and / or Cu.

[0111] Electronic devices mounted on the PCB 30 can operate according to high frequency signals, and can generate electromagnetic waves or static electricity through the high frequency signals. Such electromagnetic waves or static electricity can cause interference with electrical signals transmitted to the display panel 10 (see Figure 1 ), and can be emitted to the outside of the display device 1 (see Figure 1 ) or beyond the display device 1, thereby causing malfunction of peripheral devices. According to some embodiments, the cover layer 60 connected to the ground portion 32 shields the PCB 30 to reduce adverse effects caused by electromagnetic interference (EMI) and electrostatic discharge (ESD), thereby improving reliability in display quality and electrical characteristics of the display device 1.

[0112] When the adhesion between the cover layer 60 and the grounding portion 32 is poor, the electromagnetic wave and electrostatic shielding performance of the cover layer 60 may be reduced, thereby causing the display device 1 (see...) Figure 1 Defects in the bonding between the cover layer 60 and the ground portion 32. Therefore, during the manufacturing process of the display device 1, an inspection process for adhesion defects between the cover layer 60 and the ground portion 32 (hereinafter referred to as adhesion defect inspection or adhesion defect inspection process) can be appropriately used. According to some embodiments, in order to determine adhesion defects between the cover layer 60 and the ground portion 32, the bonding resistance between the cover layer 60 and the ground portion 32 can be used. For example, when the adhesion between the cover layer 60 and the ground portion 32 is poor, the bonding resistance between the cover layer 60 and the ground portion 32 can be increased. Therefore, adhesion defects can be determined via bonding resistance, and reference will be made below. Figure 5 Describe the inspection methods related to bonding resistance.

[0113] Figure 5 yes Figure 4 An exploded perspective view of a portion of the display device. For the sake of brevity, references will be omitted. Figure 4 Descriptions of components that are the same as or correspond to the components being described.

[0114] refer to Figure 5 To inspect for adhesion defects between the cover layer 60 and the ground portion 32, the first connector terminal 41a and the second connector terminal 41b can be connected to an inspection device. The inspection device can apply a test current I to the second connector terminal 41b. When the test current I is applied to the second connector terminal 41b, the test electrode 33, the cover layer 60, and the ground portion 32 can form a current path for the test current I to flow. Specifically, since the second connector terminal 41b is electrically connected to the test electrode 33 via the second wire CL2, since the test electrode 33 is connected to the cover layer 60, and since the cover layer 60 is connected to the ground portion 32, the test current I applied to the second connector terminal 41b can flow sequentially along the test electrode 33, the cover layer 60, and the ground portion 32.

[0115] At this time, the inspection device can measure the voltage V at the second connector terminal 41b. Since the first connector terminal 41a is electrically connected to the ground portion 32 via the first wire CL1, the potential at the first connector terminal 41a can be a reference potential. Therefore, the voltage V at the second connector terminal 41b can represent the potential difference between the first connector terminal 41a and the second connector terminal 41b.

[0116] Therefore, since the value of the test current I and the value of the voltage V at the second connector terminal 41b are known, the total resistance Rt on the current path of the test current I can be calculated by using Equation 1 below.

[0117]

[0118] Here, the total resistance Rt can include the bonding resistance Rb. The bonding resistance Rb among the total resistance Rt varies according to an adhesion defect between the cover layer 60 and the ground portion 32, but other resistances than the bonding resistance Rb corresponding to the total resistance Rt can have a fixed value. Therefore, when the resistance value of the total resistance Rt including the bonding resistance Rb is higher than a desired value (e.g., a predetermined normal value), it can be determined that there is an adhesion defect, and when the resistance value of the total resistance Rt is equal to or lower than the normal value, it can be determined that the adhesion force is satisfactory.

[0119] As a comparative example, in order to measure the bonding resistance between the cover layer and the ground portion, a portion of the ground portion can be exposed by removing a portion of the cover layer overlapping the ground portion. In the comparative example, an inspection device can be connected to the exposed portion of the ground portion and the cover layer to measure the bonding resistance. In such a destructive adhesion defect inspection, the inspection is performed by sampling some of the manufactured display devices, and thus, a separate process of sampling and removing the cover layer can be necessary.

[0120] However, according to some embodiments described above, since the first connector terminal 41a electrically connected to the ground portion 32, the test electrode 33, and the second connector terminal 41b electrically connected to the test electrode 33 are provided, the adhesion defect inspection can be performed by using the first connector terminal 41a and the second connector terminal 41b without removing the cover layer 60. In such a non-destructive adhesion defect inspection, some of the manufactured display devices do not need to be sampled, and quality control can be achieved for all of the manufactured display devices.

[0121] In addition, in such a non-destructive adhesion defect inspection, since a normal product can be manufactured by performing a re-compression process on a product determined to have an adhesion defect according to the inspection result, a loss due to disposal of a defective product can be reduced.

[0122] In addition, the adhesion defect inspection process can be performed concurrently or substantially simultaneously with an existing inspection process (e.g., an inspection process for normal operation of a display panel), or can be performed immediately after a process of adhering the cover layer 60, and a separate process of sampling or removing the cover layer 60 can be omitted. Therefore, during a manufacturing process of a display device, a loss can be reduced, and a yield can be improved.

[0123] Figure 6 is a perspective view of a display device according to other embodiments. Descriptions on components identical or corresponding to those described with reference to Figure 4 will be omitted, and a description will be mainly given of the differences.

[0124] With reference to Figure 6 , the PCB 30 can include a first terminal TP1 and a second terminal TP2 electrically connected to the ground portion 32 and the test electrode 33, respectively. For example, the ground portion 32 and the first terminal TP1 can be connected via a third conductive line CL3, and the test electrode 33 and the second terminal TP2 can be connected via a fourth conductive line CL4. The first terminal TP1 and the second terminal TP2 can be formed on the same layer as the ground portion 32 and the test electrode 33, and can include the same material as the ground portion 32 and the test electrode 33. The protective layer of the PCB 30 can include an opening so that respective surfaces of the first terminal TP1 and the second terminal TP2 are exposed. The first terminal TP1 and the second terminal TP2 can not overlap the cover layer 60.

[0125] Figure 7 is an exploded perspective view of a display device according to other embodiments. Descriptions on components identical or corresponding to those described with reference to Figure 6 and Figure 4 will be omitted. Figure 6

[0126] According to other embodiments, the first terminal TP1 and the second terminal TP2 can be used to check an adhesion defect between the cover layer 60 and the ground portion 32. A checking device such as an automatic resistance tester can be connected to the first terminal TP1 and the second terminal TP2.

[0127] The checking device can apply a test current I to the second terminal TP2. When the test current I is applied to the second terminal TP2, the test electrode 33, the cover layer 60, and the ground portion 32 can form a current path through which the test current I flows.

[0128] At this time, the checking device can measure a voltage V at the second terminal TP2. Since the first terminal TP1 is electrically connected to the ground portion 32, a potential at the first terminal TP1 can be a reference potential. Accordingly, the voltage V at the second terminal TP2 can represent a potential difference between the first terminal TP1 and the second terminal TP2.

[0129] ​Therefore, since the value of the test current I and the value of the voltage V at the second terminal TP2 are known, the total resistance Rt on the current path of the test current I can be calculated by using Equation 1 above. Here, the total resistance Rt can include the bonding resistance Rb. As described above, the bonding resistance Rb among the total resistance Rt varies depending on the adhesion defect between the cover layer 60 and the ground portion 32, but other resistances corresponding to the total resistance Rt and excluding the bonding resistance Rb can have fixed values. Therefore, when the resistance value of the total resistance Rt including the bonding resistance Rb is higher than a desired value (e.g., a predetermined normal value), the adhesion defect can be determined, and when the resistance value of the total resistance Rt is equal to or lower than the desired value / normal value, the satisfactory adhesion force can be determined.

[0130] Since the first terminal TP1 and the second terminal TP2 are located in the PCB 30, the third conductive line CL3 and the fourth conductive line CL4 can be relatively short, and the resistance caused by the third conductive line CL3 and the fourth conductive line CL4 can be reduced. Therefore, the ratio of the bonding resistance Rb among the total resistance Rt becomes relatively high, and thus a more accurate result of the adhesion defect inspection can be obtained.

[0131] In the above, the display device has been mainly described, but the present disclosure is not limited thereto. For example, a method of manufacturing such a display device will also be within the scope of the present disclosure.

[0132] According to the above-described embodiments, via the reduction of EMI and ESD on the PCB by using the cover layer, the reliability on the display quality and the electrical characteristics of the display device can be improved. Further, since the inspection for the adhesion defect of the cover layer is performed non-destructively, during the manufacturing process of the display device, the loss can be reduced, and the yield can be improved. However, the scope of the present disclosure is not limited by these aspects.

[0133] It should be understood that the embodiments described herein should be understood, only by way of description in rather than by way of limitation. Descriptions of features or aspects within described embodiments should generally be considered as being applicable to and combinable with other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the attached figures, those of ordinary skill in the art will appreciate that various changes in form and detail can be made thereto without departing from the spirit and scope as defined by the following claims, which functional equivalents will include within their scope.

Claims

1. A display device comprising: a display panel including a display area and a peripheral area; a printed circuit board attached to the peripheral area and including a ground portion and a test electrode spaced apart from the ground portion; a connector including a plurality of connector terminals for electrically connecting the printed circuit board and an external control device to each other; and a cover layer on and covering at least a portion of the printed circuit board; wherein the cover layer is connected to the ground portion. The cover layer overlaps the ground portion and the test electrode.

2. The display device according to claim 1, wherein The cover layer is connected to the test electrode.

3. The display device according to claim 2, wherein The cover layer includes a conductive material.

4. The display device according to claim 1, wherein The cover layer includes a metal layer or a conductive fiber.

5. The display device of claim 4, wherein, One of the plurality of connector terminals is electrically connected to the test electrode.

6. The display device according to claim 1, wherein Another of the plurality of connector terminals is electrically connected to the ground portion.

7. The display device of claim 6, wherein, The test electrode, the cover layer, and the ground portion form a current path for a current applied to the one connector terminal.

8. The display device of claim 6, wherein, The printed circuit board further includes a first terminal and a second terminal electrically connected to the test electrode and the ground portion, respectively, wherein the first terminal and the second terminal do not overlap the cover layer.

9. The display device according to claim 1, wherein The test electrode, the cover layer, and the ground portion form a current path through which a current applied to the first terminal flows.

10. The display device of claim 9, wherein, ​

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