Display substrate, method for identifying pattern of display substrate, and display device

Abstract

The display substrate, the texture identification method thereof and the display device provided by the present disclosure comprise a substrate substrate; a plurality of pixel driving circuits arranged in an array on the substrate substrate; a plurality of texture identification circuits located at the gaps of the pixel driving circuits; the texture identification circuit comprises a photosensitive transistor, the active layer of the photosensitive transistor is located on the side of the gate of the photosensitive transistor away from the substrate substrate, and the first pole and the second pole of the photosensitive transistor are located on the side of the active layer of the photosensitive transistor away from the substrate substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a method for identifying its texture, and a display device. Background Technology

[0002] With the rapid development of the information industry, biometric technology has been used more and more widely. In particular, because different users have different fingerprints, functions such as unlocking devices, identity authentication, and payment can be realized based on fingerprints. Therefore, fingerprint recognition technology has been widely used in mobile terminals, smart homes and other fields to provide security for user information. Summary of the Invention

[0003] This disclosure provides a display substrate, a texture recognition method thereon, and a display device to reduce the manufacturing process of in-screen fingerprint recognition display products.

[0004] Therefore, the display substrate provided in this embodiment includes:

[0005] Substrate;

[0006] Multiple pixel driving circuits are arranged in an array on the substrate.

[0007] Multiple texture recognition circuits are provided, the texture recognition circuits being located at the gaps in the pixel driving circuits; each texture recognition circuit includes a phototransistor, the active layer of which is located on the side of the phototransistor's gate away from the substrate, and the first and second electrodes of which are located on the side of the phototransistor's active layer away from the substrate.

[0008] Optionally, the display substrate provided in the embodiments of this disclosure further includes: a first insulating layer and a second insulating layer, wherein the first insulating layer is located between the gate layer of the phototransistor and the active layer of the phototransistor, the second insulating layer is located between the active layer of the phototransistor and the first and second electrodes of the phototransistor, and the thickness of the first insulating layer is less than the thickness of the second insulating layer.

[0009] Optionally, in the display substrate provided in the embodiments of this disclosure, the texture recognition circuit further includes: a reset transistor and a scanning transistor;

[0010] The gate of the reset transistor is electrically connected to the reset signal terminal, the first terminal of the reset transistor is electrically connected to the reference signal terminal, and the second terminal of the reset transistor is electrically connected to the second terminal of the phototransistor.

[0011] The gate of the scanning transistor is electrically connected to the scanning signal terminal, the first terminal of the scanning transistor is electrically connected to the second terminal of the reset transistor, and the second terminal of the scanning transistor is electrically connected to the read signal terminal.

[0012] Optionally, in the display substrate provided in the embodiments of this disclosure, the phototransistor, the reset transistor, and the scan transistor all have an oxide active layer.

[0013] Optionally, in the display substrate provided in the embodiments of this disclosure, the reset transistor and the scan transistor have the same functional film layers disposed in the same layer and have at least one gate; the gate of the photosensitive transistor is disposed in the same layer as one of the at least one gates.

[0014] Optionally, in the display substrate provided in the embodiments of this disclosure, both the reset transistor and the scan transistor have a first gate located between the oxide active layer and the substrate, and / or a second gate located on the side of the oxide active layer away from the substrate.

[0015] The gate of the phototransistor is disposed on the same layer as the first gate or the second gate.

[0016] Optionally, in the display substrate provided in the embodiments of this disclosure, the texture recognition circuit further includes a charge integrating capacitor, which is connected between the first electrode of the phototransistor and the second electrode of the phototransistor.

[0017] Optionally, in the display substrate provided in the embodiments of this disclosure, the charge integration capacitor includes a first electrode plate and a second electrode plate stacked on the substrate; the first electrode plate is disposed on the same layer as the first gate, and the second electrode plate is located between the first electrode plate and the substrate.

[0018] Optionally, in the display substrate provided in the embodiments of this disclosure, the plurality of texture recognition circuits are arranged in an array on the substrate.

[0019] In a single-row texture recognition circuit, the first terminal of each phototransistor is electrically connected to a high-level power supply line, and in a single-row texture recognition circuit, the gate of each phototransistor is electrically connected to a bias signal line.

[0020] In the texture recognition circuit described in a row, the reset signal terminal of each reset transistor is electrically connected to a reset signal line, and the reference signal terminal of each reset transistor in the texture recognition circuit described in a row is electrically connected to a reference signal line.

[0021] In a single-row texture recognition circuit, the reading signal terminal of each scanning transistor is electrically connected to a reading signal line, and in a single-row texture recognition circuit, the scanning signal terminal of each scanning transistor is electrically connected to a scanning signal line.

[0022] Optionally, the display substrate provided in the embodiments of this disclosure further includes: a plurality of charge integrating amplifiers, wherein the charge integrating amplifiers are electrically connected to the read signal lines one by one;

[0023] The charge integrating amplifier includes a feedback capacitor, an amplifier, and a switch. The first input terminal of the amplifier is electrically connected to the read signal line, the second input terminal of the amplifier is electrically connected to the reference signal line, the feedback capacitor is connected between the first input terminal and the output terminal of the amplifier, and the switch is connected between the first input terminal and the output terminal of the amplifier.

[0024] Optionally, in the display substrate provided in the embodiments of this disclosure, the pixel driving circuit includes: a driving transistor, a switching transistor, and a storage capacitor; wherein,

[0025] The driving transistor has a low-temperature polycrystalline silicon active layer, the switching transistor has an oxide active layer, and the switching transistor and the reset transistor have the same functional film layer in the same layer. The storage capacitor and the charge integration capacitor are in the same layer.

[0026] Based on the same inventive concept, this disclosure provides a display device including the display substrate provided in the above-described embodiments.

[0027] Based on the same inventive concept, this disclosure provides a method for texture recognition of the above-mentioned display substrate, including:

[0028] During the reset phase, the output terminal of the texture recognition circuit is reset;

[0029] During the reset phase, a high-level signal is applied to the first terminal of the phototransistor, and a reference signal is applied to the second terminal of the phototransistor, so that a voltage difference is formed between the first and second terminals of the phototransistor.

[0030] During the integration phase, a bias signal is applied to the gate of the phototransistor, causing the phototransistor to be in a turned-off state, and the phototransistor generates charge carriers under the illumination of the ripple-reflected light.

[0031] During the reading phase, the photogenerated carriers of the phototransistor are collected at the output terminal of the texture recognition circuit.

[0032] The beneficial effects of this disclosure are as follows:

[0033] The display substrate, texture recognition method, and display device provided in this disclosure include: a substrate; multiple pixel driving circuits arranged in an array on the substrate; and multiple texture recognition circuits located at the gaps between the pixel driving circuits. Each texture recognition circuit includes a phototransistor, the active layer of which is located on the side of the phototransistor's gate away from the substrate, and the first and second electrodes of which are located on the side of the phototransistor's active layer away from the substrate. Using a bottom-gate type phototransistor can generate charge carriers from the reflected light of a texture (e.g., a fingerprint). Because the light intensity reflected from the valleys and ridges of the texture differs, charge carriers of different intensities can be generated according to the difference in reflected light intensity, achieving full-screen texture recognition within the screen. Furthermore, the texture recognition circuit, including the phototransistor, is integrated at the gaps between the pixel driving circuits, allowing the texture recognition circuit to be fabricated simultaneously during the manufacturing of the pixel driving circuit. This provides better process compatibility and eliminates the need for a separate fabrication process for an integrated photodiode within the screen, reducing the overall manufacturing process of the in-screen texture recognition product, saving raw material costs, and improving production efficiency. Furthermore, compared to related technologies that use fingerprint recognition devices to achieve local fingerprint recognition, this method can effectively reduce the overall thickness of the display device and increase the added value of the product. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0035] Figure 2 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0036] Figure 3 This is a schematic diagram of the texture recognition circuit provided in an embodiment of the present disclosure;

[0037] Figure 4 Characteristic curves of the phototransistor provided in the embodiments of this disclosure;

[0038] Figure 5 A schematic diagram of the layout of the texture recognition circuit on the display substrate provided in the embodiments of this disclosure;

[0039] Figure 6 for Figure 1 The flowchart shown is a process for manufacturing a display substrate.

[0040] Figure 7 for Figure 2 The flowchart shown is a process for manufacturing a display substrate.

[0041] Figure 8 for Figure 3 The timing diagram of the texture recognition circuit shown is shown. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. The dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout the drawings.

[0043] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0044] Current mainstream fingerprint recognition products use a separate fingerprint sensor attached to a specific small area on the back or side of the display screen. However, this type of fingerprint recognition product can only recognize fingerprints in a very small area, and the external attachment method increases the overall thickness of the fingerprint recognition product, which is not conducive to its use on flexible displays.

[0045] In an era where full-screen products strive for maximum screen-to-body ratio, fingerprint recognition at any location on the screen better meets people's needs. Current technology typically integrates a photodiode within the full-screen display to achieve full-screen fingerprint recognition. However, because the photodiode consists of a stacked bottom electrode, a photoelectric conversion layer (PIN), and a top electrode, multiple masking processes are required to fabricate the photodiode.

[0046] To at least address the aforementioned problems in related technologies, embodiments of this disclosure provide a display substrate, such as... Figure 1 and Figure 2 As shown, it includes:

[0047] Substrate 101;

[0048] Multiple pixel driving circuits 102 are arranged in an array on the substrate 101;

[0049] Multiple texture recognition circuits 103 are located at the gaps in the pixel driving circuits 102. In specific implementations, texture recognition circuits 103 can be provided at each gap in the pixel driving circuits 102, or they can be provided at some gaps in the pixel driving circuits 102. Each texture recognition circuit 103 includes a phototransistor Ts. The active layer of the phototransistor Ts is located on the side of the phototransistor Ts away from the substrate 101, and the first and second electrodes of the phototransistor Ts are located on the side of the active layer of the phototransistor Ts away from the substrate 101. Optionally, the texture recognition circuit 103 can be used to recognize fingerprints, palm prints, and other textures. In this disclosure, fingerprint recognition is used as an example for explanation.

[0050] In the display substrate provided in this embodiment, the phototransistor Ts generates different off-state leakage currents under different light intensities. This allows the bottom-gate type phototransistor Ts to generate electrical signals from the reflected light of the ridges (e.g., fingerprints). Since the light intensities reflected by the valleys and ridges of the ridges differ, different electrical signals can be generated based on the differences in reflected light intensity, achieving full-screen ridge recognition. Furthermore, the ridge recognition circuit 103, including the phototransistor Ts, is integrated into the gap of the pixel driving circuit 102. This allows the ridge recognition circuit to be fabricated simultaneously during the fabrication of the pixel driving circuit 102, providing better process compatibility. It also eliminates the need for a separate fabrication process for an integrated photodiode within the screen, reducing the overall manufacturing process of the in-screen ridge recognition product, saving raw material costs, and improving production efficiency. Moreover, compared to related technologies that attach fingerprint recognition devices for partial fingerprint recognition, this disclosure effectively reduces the overall thickness of the display device and increases the added value of the product.

[0051] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 1 and Figure 2As shown, it may further include: a first insulating layer 104 and a second insulating layer 105, wherein the first insulating layer 104 is located between the gate layer of the phototransistor Ts and the active layer of the phototransistor Ts, and the second insulating layer 105 is located between the active layer of the phototransistor Ts and the layers containing the first and second electrodes of the phototransistor Ts. The thickness of the first insulating layer 104 is less than the thickness of the second insulating layer 105. The first insulating layer 104 can achieve planarization below the active layer of the phototransistor Ts, and the second insulating layer 105 can effectively protect the active layer. At the same time, setting the thickness of the first insulating layer 104 to be less than the thickness of the second insulating layer 105 can satisfy the requirement that the gate of the phototransistor Ts has better control over the electrical performance of the channel region (equivalent to the active layer region between the first and second electrodes of the phototransistor Ts). Optionally, the materials of the first insulating layer 104 and the second insulating layer 105 may include inorganic insulating materials with good hydrogen barrier properties, such as silicon oxide and silicon nitride, which can prevent hydrogen from diffusing into the active layer, thereby making the transistors more stable and thus ensuring the reliability of the fabricated display substrate.

[0052] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 1 to 3 As shown, the texture recognition circuit 103 may further include: a reset transistor T1 and a scan transistor T2; wherein,

[0053] The gate of the reset transistor T1 is electrically connected to the reset signal terminal Rst, the first terminal of the reset transistor T1 is electrically connected to the reference signal terminal Ref, and the second terminal of the reset transistor T1 is electrically connected to the second terminal of the phototransistor Ts.

[0054] The gate of the scanning transistor T2 is electrically connected to the scan signal terminal Gate, the first terminal of the scanning transistor T2 is electrically connected to the second terminal of the reset transistor T1, and the second terminal of the scanning transistor T2 is electrically connected to the read signal terminal S.

[0055] In practical implementation, the gate of the phototransistor Ts can be electrically connected to the bias signal terminal Bias, and the first terminal of the phototransistor Ts can be electrically connected to the high-level power supply terminal VDD. The reset signal terminal Rst controls the reset transistor T1 to be in the on state, causing the reference signal Vref at the reference signal terminal Ref to be written to the second terminal (i.e., node n) of the phototransistor Ts. Because the high-level signal Vdd of the high-level power supply terminal VDD is written to the first terminal of the phototransistor Ts, a voltage difference is formed between the first and second terminals of the phototransistor Ts. Under the control of the bias signal terminal Bias, the phototransistor Ts is in the off state. After the reflected light from the fingerprint shines on the active layer of the phototransistor Ts, the phototransistor Ts generates charge carriers, which are then transferred from the phototransistor Ts to the scanning transistor T2. The scanning signal terminal Gate then controls the scanning transistor T2 to be turned on, allowing the photogenerated charge carriers to be output to the read signal terminal S, thus realizing the acquisition of the fingerprint ridge signal.

[0056] Figure 4 The curved portion within the dashed box illustrates the different leakage currents Ids generated by a phototransistor Ts in the off state (e.g., the voltage difference Vgs between the gate and source of phototransistor Ts is in the range of -10V to 0V) under different illumination intensities (e.g., dark and bright states). Figure 4 It can be seen that the off-state leakage current under dark conditions will be 1E. -14 A~1E -12 The current varies within the range of A; under bright-state conditions, because the phototransistor Ts generates photogenerated carriers, the off-state leakage current (equivalent to the sum of photogenerated carriers and optical leakage current) increases (for example, it can be 1E). -11 A). When the number of photogenerated carriers is small, the dark-state leakage current will cause noise interference and affect the fingerprint recognition effect.

[0057] Based on this, in the display substrate provided in the embodiments of this disclosure, the phototransistor Ts, the reset transistor T1, and the scan transistor T2 can all have an oxide active layer. This utilizes the low leakage current characteristics of the transistor with the oxide active layer to avoid noise interference caused by dark-state leakage current to photogenerated carriers, thereby improving the signal-to-noise ratio of fingerprint recognition. Optionally, the material of the oxide active layer may include indium gallium zinc oxide (IGZO).

[0058] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 1 and Figure 2As shown, the reset transistor T1 and the scan transistor T2 have the same functional film layers arranged in the same layer. Specifically, the active layer of the reset transistor T1 is arranged in the same layer as the active layer of the scan transistor T2, the gate of the reset transistor T1 is arranged in the same layer as the gate of the scan transistor T2, and the first and second electrodes of the reset transistor T1 are arranged in the same layer as the first and second electrodes of the scan transistor T2. Optionally, both the reset transistor T1 and the scan transistor T2 have at least one gate; the gate of the phototransistor Ts is arranged in the same layer as one of the at least one gates.

[0059] It should be noted that, in this disclosure, "same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same mask to form a single patterning process. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes. The specific pattern in the formed layer structure can be continuous or discontinuous; these specific patterns may be at the same height or have the same thickness, or they may be at different heights or have different thicknesses. Therefore, by setting the same functional film layers of the reset transistor T1 and the scan transistor T2 in the same layer, and setting the gate of the phototransistor Ts in the same layer as one of the gates of the reset transistor T1, this disclosure reduces the number of masking processes, saves material costs, and improves production efficiency. Furthermore, it reduces the number of film layers without increasing the overall module thickness and weight, making it more suitable for thinner and lighter self-emissive display products (such as OLEDs). In addition, integrating the display function and texture recognition function into the same display substrate greatly increases the added value of the display substrate, making it more marketable and mass-producible.

[0060] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 1 and Figure 2 As shown, both the reset transistor T1 and the scan transistor T2 may have a first gate G1 located between the oxide active layer and the substrate 101, and / or a second gate G2 located on the side of the oxide active layer away from the substrate 101. Since the first gate G1 can block light from the back side of the display substrate (i.e., the opposite side of the display surface), and the second gate G2 can block light from the display surface of the display substrate, in specific implementations, the reset transistor T1 and the scan transistor T2 may be configured to have both the first gate G1 and the second gate G2 to effectively avoid the adverse effects of light-induced leakage current on the fingerprint recognition effect.

[0061] Optionally, such as Figure 1 As shown, the gate of the phototransistor Ts can be disposed on the same layer as the first gate G1, or, as... Figure 2As shown, the gate of the phototransistor Ts can be disposed on the same layer as the second gate G2. Compared to Figure 1 , Figure 2 The phototransistor Ts in the display substrate is positioned higher, which helps to reduce the optical path of the reflected fingerprint light, thereby reducing the loss of reflected fingerprint light and improving fingerprint recognition performance. Furthermore, due to... Figure 1 As can be seen, when the gate of the phototransistor Ts and the first gate G1 are disposed on the same layer, the first insulating layer 104 can specifically be located between the layer containing the first gate G1 of the reset transistor T1 and the active layer of the phototransistor Ts, and the second insulating layer 105 can specifically be located between the active layer of the phototransistor Ts and the active layer of the reset transistor T1. Figure 2 As can be seen, when the gate of the phototransistor Ts and the second gate G2 are disposed on the same layer, the first insulating layer 104 can be specifically located between the layer where the second gate G1 of the reset transistor T1 is located and the active layer of the phototransistor Ts, and the second insulating layer 105 can be specifically located between the active layer of the phototransistor Ts and the layer where the first electrode and the second electrode of the phototransistor Ts are located.

[0062] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 1 to 3 As shown, the fingerprint recognition circuit 103 may further include a charge integrating capacitor C, which is connected between the first electrode and the second electrode of the phototransistor Ts. In a specific implementation, the charge integrating capacitor C, connected in parallel with the phototransistor Ts, can integrate and store the photogenerated carriers of the phototransistor Ts within a certain time. The stored charge Q of the charge integrating capacitor C satisfies the following relationship: Q = it = cv, where i represents the photogenerated carriers, t represents time, c represents the capacitance value of the charge integrating capacitor C, and v represents the voltage difference between the two electrode plates of the charge integrating capacitor C. By integrating the photogenerated carriers of the phototransistor Ts to a certain amount before outputting them, the intensity of the photogenerated carriers output to the reading signal terminal S can be greatly improved compared to the instantaneous output method, which is beneficial to improving the accuracy of fingerprint recognition.

[0063] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 1 and Figure 2 As shown, the charge integration capacitor C includes a first electrode plate and a second electrode plate stacked on the substrate 101; in order to reduce the number of film layers and masking times, the first electrode plate can be disposed on the same layer as the first gate G1, and the second electrode plate is located between the first electrode plate and the substrate 101.

[0064] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 4As shown, multiple fingerprint recognition circuits 103 are arranged in an array on the substrate 101. Optionally, one fingerprint recognition circuit 103 is provided at each gap of the pixel driving circuit 102. The first terminal of each photosensitive transistor Ts in a row of fingerprint recognition circuits 103 is electrically connected to a high-level power supply line VDDL, and the gate of each photosensitive transistor Ts in a row of fingerprint recognition circuits 103 is electrically connected to a bias signal line BIASL. The reset signal terminal Rst of each reset transistor T1 in a row of fingerprint recognition circuits 103 is electrically connected to a reset signal line RSTL, and the reference signal terminal Ref of each reset transistor T1 in a row of fingerprint recognition circuits 103 is electrically connected to a reference signal line REFL. The read signal terminal S of each scan transistor T2 in a row of fingerprint recognition circuits 103 is electrically connected to a read signal line SL, and the scan signal terminal Gate of each scan transistor T2 in a row of fingerprint recognition circuits 103 is electrically connected to a scan signal line GL. The above configuration can realize in-screen fingerprint recognition at any position on the full screen.

[0065] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 5 As shown, it may further include: multiple charge integrating amplifiers 106, each electrically connected to a corresponding read signal line; each charge integrating amplifier 106 includes a feedback capacitor Cf, an amplifier A, and a switch SW, wherein the first input terminal of amplifier A is electrically connected to the read signal line SL, the second input terminal of amplifier A is electrically connected to the reference signal line REFL, the feedback capacitor Cf is connected between the first input terminal of amplifier A and the output terminal Out of amplifier A, and the switch SW is connected between the first input terminal of amplifier A and the output terminal Out of amplifier A. Optionally, the charge integrating amplifier 106 may be integrated into a readout chip (ROIC) in related technologies.

[0066] In practical implementation, the charge integration capacitor C and the feedback capacitor Cf are redistributed using the following formula: c*(Vdd-Vn)=cf*(Vref-Vout), where c represents the capacitance value of the charge integration capacitor C, Vdd represents the voltage value of the high-level power supply terminal VDD (equivalent to the first terminal of the phototransistor Ts), Vn represents the voltage value of the n-node (equivalent to the second terminal of the phototransistor Ts), cf represents the capacitance value of the feedback capacitor Cf, Vref represents the voltage value of the reference signal terminal Ref, and Vout represents the voltage value of the output terminal Out of amplifier A. After amplification by amplifier A, the weak photogenerated carrier signal can be detected. The valleys and ridges of the fingerprint generate different voltages, and the greater the light intensity, the greater the change ΔV (i.e., Vout-Vref) of Vout relative to Vref. By scanning the rows, the signal of the entire fingerprint recognition circuit 103 array can be read, generating a fingerprint image and achieving the purpose of fingerprint recognition. In some embodiments, the voltage value Vref of the reference signal terminal Ref is adjustable, so that the voltage value Vn of node n can be adjusted by Vref, and finally the output voltage of the charge integrating amplifier 106 can be adjusted so that the voltage corresponding to the valley / ridge of the fingerprint works within the full scale of ROIC, which is beneficial to improving the detection accuracy.

[0067] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 1 and Figure 2 As shown, the pixel driving circuit 102 may include: a driving transistor Td, a switching transistor T3, and a storage capacitor Cst; wherein,

[0068] The driving transistor Td has a low-temperature polycrystalline silicon (LTPS) active layer, and the switching transistor T3 has an oxide active layer. The switching transistor T3 and the reset transistor T1 share the same functional film layer, and the storage capacitor Cst and the charge integration capacitor C are also located on the same layer. The driving transistor Td with the LTPS active layer has high mobility, which accelerates the charging speed of the storage capacitor Cst. The open-type transistor with the oxide active layer has lower leakage current. Combining the advantages of these two transistors in the pixel driving circuit 102 helps to fabricate high-resolution, low-power, and high-quality display products.

[0069] Specifically, the gate of the switching transistor T3 is disposed on the same layer as the gate of the reset transistor T1, the active layer of the switching transistor T3 can be disposed on the same layer as the active layer of the reset transistor T1, and the first and second electrodes of the switching transistor T3 can be disposed on the same layer as the first and second electrodes of the reset transistor T1. The gate of the driving transistor Td can be disposed on the same layer as the second electrode plate of the charge integrating capacitor C, the low-temperature polysilicon active layer of the driving transistor Td can be located between the layer containing the gate of the driving transistor Td and the substrate 101, and the first and second electrodes of the driving transistor Td can be disposed on the same layer as the first and second electrodes of the reset transistor T1. Optionally, to avoid leakage caused by light irradiation of the low-temperature polysilicon active layer, a light-shielding layer 107 can be disposed between the low-temperature polysilicon active layer and the substrate 101, such that the orthographic projection of the low-temperature polysilicon active layer on the substrate 101 is located within the orthographic projection of the light-shielding layer 107 on the substrate 101, so as to block light through the light-shielding layer 107 and avoid the influence of light on the low-temperature polysilicon active layer.

[0070] It should be noted that the first and second terminals of the transistors provided in the embodiments of this disclosure are the drain and source, respectively. Their functions can be interchanged depending on the transistor type and the input signal, and no specific distinction is made here. Generally, when the transistor is a P-type transistor, the first terminal is the source and the second terminal is the drain; when the transistor is an N-type transistor, the first terminal is the drain and the second terminal is the source.

[0071] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 1 and Figure 2 As shown, the substrate may also include a buffer layer 108, a first gate insulating layer 109, a first interlayer dielectric layer 110, a first planarization layer 111, a second gate insulating layer 112, a second interlayer dielectric layer 113, a second planarization layer 114, a transition electrode 115, a third planarization layer 116, an anode 117, a pixel defining layer 118, a support layer 119, a light-emitting functional layer 120 (including but not limited to a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting material layer, a hole blocking layer, an electron transport layer, and an electron injection layer), and an encapsulation layer 121 (including but not limited to a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked together). Other essential components of the display substrate are those that should be understood by those skilled in the art and are not described in detail here, nor should they be construed as limiting this disclosure.

[0072] In addition, regarding the information provided in this disclosure Figure 1 The display substrate shown in this disclosure also provides a corresponding manufacturing method, such as... Figure 6 As shown, the specific production process is as follows:

[0073] A patterned light-shielding layer 107 is formed on the substrate 101;

[0074] A buffer layer 108 is formed on the side of the light-shielding layer 107 away from the substrate 101;

[0075] A low-temperature polysilicon active layer of the driving transistor Td, which is shielded by the light-shielding layer 107, is formed on the side of the buffer layer 108 away from the substrate 101.

[0076] A first gate insulating layer 109 is formed on the side of the low-temperature polycrystalline silicon active layer away from the substrate 101;

[0077] On the side of the first gate insulating layer 109 away from the substrate 101, the gate of the driving transistor Td, the second electrode plate of the storage capacitor Cst, and the second electrode plate of the charge integration capacitor C are formed by sharing the same film layer.

[0078] A first interlayer dielectric layer 110 is formed on the side of the layer where the gate of the driving transistor Td is located that is away from the substrate 101;

[0079] On the side of the first interlayer dielectric layer 110 away from the substrate 101, the first electrode plate of the storage capacitor Cst, the first gate G1 of the switching transistor T3, the first gate G1 of the reset transistor T1, the first gate G1 of the scanning transistor T2, the gate of the phototransistor Ts, and the first electrode plate of the charge integration capacitor C are formed by sharing the same film layer.

[0080] A first insulating layer 104 is formed on the side of the layer where the gate of the phototransistor Ts is located that is away from the substrate 101;

[0081] An oxide active layer of a phototransistor Ts is formed on the side of the first insulating layer 104 away from the substrate 101.

[0082] A second insulating layer 105 is formed on the side of the oxide active layer of the phototransistor Ts that is away from the substrate 101.

[0083] On the side of the second insulating layer 105 away from the substrate 101, the same film layer is used to form the oxide active layer of the switching transistor T3, the oxide active layer of the reset transistor T1, and the oxide active layer of the scan transistor T2.

[0084] A second gate insulating layer 112 is formed on the side of the common film layer of the oxide active layer of the reset transistor T1 away from the substrate 101.

[0085] The second gate G2 of the switching transistor T3, the second gate G2 of the reset transistor T1, and the second gate G2 of the scan transistor T2 are formed on the side of the second gate insulating layer 112 away from the substrate 101, sharing the same film layer.

[0086] A second interlayer dielectric layer 113 is formed on the layer where the second gate G2 of the reset transistor T1 is located;

[0087] On the side of the second interlayer dielectric layer 113 away from the substrate 101, the first and second terminals of the switching transistor T3, the first and second terminals of the reset transistor T1, the first and second terminals of the scanning transistor T2, the first and second terminals of the photosensitive transistor Ts, and the first and second terminals of the driving transistor Td are formed using the same film layer; wherein the first and second terminals of each transistor are electrically connected to their respective active layers via vias; thus, the fabrication of the texture recognition circuit 103 and the pixel driving circuit 102 is completed;

[0088] A second planarization layer 114 is formed on the side of the layer containing the first and second electrodes of the phototransistor Ts that is away from the substrate 101;

[0089] A transfer electrode 115 electrically connected to the first / second pole of the driving transistor Td is formed on the side of the second planarization layer 114 away from the substrate 101;

[0090] A third planarization layer 116 is formed on the side of the layer where the transfer electrode 115 is located that is away from the substrate 101;

[0091] An anode 117 electrically connected to the transfer electrode 115 is formed on the side of the third planarization layer 116 away from the substrate 101;

[0092] A pixel defining layer 118 with multiple openings is formed on the side of the layer where the anode 117 is located away from the substrate 101, and the openings expose at least a portion of the anode 117.

[0093] A support layer 119 is formed on the side of the pixel defining layer 118 away from the substrate 101;

[0094] A light-emitting functional layer 120 is formed on the side of the support layer 119 away from the substrate 101, and a cathode (not shown in the figure) is located on the side of the light-emitting functional layer 120 away from the substrate 101.

[0095] An encapsulation layer 121 is formed on the side of the layer containing the cathode (not shown) away from the substrate 101, thus completing the process. Figure 1 The fabrication of the display substrate is shown.

[0096] Regarding the information provided in this disclosure Figure 2 The display substrate shown is manufactured using the same method as... Figure 1 The manufacturing methods of the display substrates shown are similar; the following only describes the differences, and for repetitions, please refer to [link to relevant documentation]. Figure 1 The fabrication steps of the display substrate shown are not detailed here. Specifically, as... Figure 7 As shown, Figure 2The manufacturing process of the display substrate shown is as follows: Figure 1 The difference in the manufacturing process of the display substrate shown is that:

[0097] The first electrode plate of the storage capacitor Cst, the first gate G1 of the switching transistor T3, the first gate G1 of the reset transistor T1, the first gate G1 of the scan transistor T2, and the first electrode plate of the charge integration capacitor C are formed on the side of the first interlayer dielectric layer 110 away from the substrate 101 by sharing the same film layer.

[0098] A first planarization layer 111 is formed on the side of the layer containing the gate of the phototransistor Ts that is away from the substrate 101;

[0099] On the side of the first planarization layer 111 away from the substrate 101, the same film layer is used to form the oxide active layer of the switching transistor T3 and the oxide active layer of the reset transistor T1.

[0100] On the side of the second gate insulating layer 112 away from the substrate 101, the second gate G2 of the switching transistor T3, the second gate G2 of the reset transistor T1, the second gate G2 of the scan transistor T2, and the gate of the photosensitive transistor Ts are formed using the same film layer.

[0101] A first insulating layer 104 is formed on the side of the layer where the second gate G2 of the reset transistor T1 is located, away from the substrate 101;

[0102] An oxide active layer of a phototransistor Ts is formed on the side of the first insulating layer 104 away from the substrate 101.

[0103] A second insulating layer 105 is formed on the side of the oxide active layer of the phototransistor Ts that is away from the substrate 101.

[0104] On the side of the second insulating layer 105 away from the substrate 101, the first and second terminals of the switching transistor T3, the first and second terminals of the reset transistor T1, the first and second terminals of the scanning transistor T2, the first and second terminals of the photosensitive transistor Ts, and the first and second terminals of the driving transistor Td are formed using the same film layer; wherein the first and second terminals of each transistor are electrically connected to their respective active layers via vias; thus, the fabrication of the texture recognition circuit 103 and the pixel driving circuit 102 is completed.

[0105] It should be noted that, in the fabrication method provided in the embodiments of this disclosure, the patterning processes involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes, depending on the actual pattern formed during the fabrication process, and are not limited here. For example, a post-baking process may be included after development and before etching.

[0106] The deposition process can be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and is not limited here; the mask used in the masking process can be a half-tone mask, a single-slit mask, or a gray-tone mask, and is not limited here; the etching can be dry etching or wet etching, and is not limited here.

[0107] Based on the same inventive concept, this disclosure provides a method for texture recognition of the above-mentioned display substrate, including:

[0108] During the reset phase t1, the output of the texture recognition circuit 103 is reset.

[0109] During the reset phase t2, a high-level signal Vdd is applied to the first terminal of the phototransistor Ts, and a reference signal Vref is applied to the second terminal of the phototransistor Ts, so that a voltage difference is formed between the first and second terminals of the phototransistor Ts.

[0110] During the integration phase t3, a bias signal Vbias is applied to the gate of the phototransistor Ts, causing the phototransistor Ts to be in the off state, and the phototransistor Ts generates charge carriers under the illumination of the ripple reflected light.

[0111] During the reading phase t4, the photogenerated carriers of the phototransistor Ts are collected at the output of the texture recognition circuit 103.

[0112] To better understand the texture recognition method provided in the embodiments of this disclosure, the following will be used as... Figure 3 The texture recognition circuit 103 shown is used as an example for explanation. Figure 3 In the texture recognition circuit shown, both the reset transistor T1 and the scan transistor T2 are N-type transistors, which are turned on under high potential and turned off under low potential; the switch SW is turned on under high potential and turned off under low potential; the bias signal terminal Bias is loaded with a fixed potential, so that the phototransistor Ts remains in the off state; the corresponding timing sequence of the texture recognition circuit is as follows. Figure 8 As shown, specifically, select Figure 8The reset phase t1, reset phase t2, integration phase t3, and reading phase t4 in the working timing sequence shown will be described in detail.

[0113] During the reset phase t1, the reset signal terminal Rst outputs a low potential, causing the reset transistor T1 to be in the off state; the scan signal terminal Gate outputs a high potential, causing the scan transistor T2 to be in the on state; the switch SW has a high potential, causing the switch SW to be on. A reference signal Vref is applied to the read signal terminal S to reset the feedback capacitor Cf, thereby canceling the interference of the parasitic capacitance of the read signal line SL (equivalent to the read signal terminal S) on the discharge read process.

[0114] During the reset phase t2, the reset signal terminal Rst outputs a high potential, turning on the reset transistor T1; the scan signal terminal Gate outputs a low potential, turning off the scan transistor T2; and the switch SW is at a high potential, turning on the switch SW. The reference signal Vref at the reference signal line terminal Ref is written to node n (i.e., the second terminal of phototransistor Ts) through the turned-on reset transistor T1, thus resetting node n. The high-level signal Vdd at the high-level power supply terminal VDD is applied to the first terminal of phototransistor Ts, creating an electric field between the first and second terminals of phototransistor Ts. This forms a voltage difference across the charge integrating capacitor C, effectively configuring the charge range input to the charge integrating amplifier 106 and achieving maximum accuracy measurement across the full scale.

[0115] During the integration phase t3, the reset signal terminal Rst outputs a low potential, causing the reset transistor T1 to be in the off state; the scan signal terminal Gate outputs a low potential, causing the scan transistor T2 to be in the off state; the switch SW has a high potential, causing the switch SW to be on. The fixed bias signal Vbias at the bias signal terminal Bias causes the phototransistor Ts to be in the off state. The phototransistor Ts receives reflected light from the ripples and generates charge carriers. The charge integration capacitor C integrates the photogenerated charge carriers of the phototransistor Ts and stores them. Under different intensities of reflected light, the n node forms different potentials, resulting in different amounts of charge stored in the charge integration capacitor C.

[0116] During the reading phase t4, the reset signal terminal Rst outputs a low potential, causing the reset transistor T1 to be in the off state; the scan signal terminal Gate outputs a high potential, causing the scan transistor T2 to be in the on state; the switch SW has a low potential, causing the switch SW to be in the off state. The feedback capacitor Cf redistributes the photogenerated carriers stored in the charge integration capacitor C according to the formula—c*(Vdd-Vn)=cf*(Vref-Vout), and the redistributed photogenerated carriers are amplified and output by amplifier A. The valleys and ridges of the fingerprint generate different voltages, and the greater the light intensity, the greater the change in Vout relative to Vref ΔV (i.e., Vout-Vref). Through row scanning, the signal reading of the entire fingerprint recognition circuit 103 array can be realized, generating a fingerprint image and achieving the purpose of fingerprint recognition.

[0117] Based on the same inventive concept, this disclosure provides a display device including the display substrate described above. Since the principle by which this display device solves the problem is similar to that of the display substrate, the implementation of this display device can refer to the embodiments of the display substrate described above, and repeated details will not be elaborated further.

[0118] In some embodiments, the display device provided in this disclosure can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. This display device includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, memory, processor, and power supply. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in this disclosure. In other words, the display device provided in this disclosure may include more or fewer of the aforementioned components, or combine certain components, or have different component arrangements.

[0119] As can be seen from the above, the embodiments of this disclosure achieve full-screen fingerprint recognition by embedding the pixel driving circuit array and the fingerprint recognition circuit together, fabricating them simultaneously, and sharing the same film layer. This reduces the number of processes required and facilitates mass production. Specifically, when a finger is placed above the display device, the light-emitting device electrically connected to the pixel driving circuit acts as a light source. Light shines onto the finger surface and is reflected onto the oxide active layer surface of the phototransistor. After the reset transistor resets the second terminal (i.e., the n-node) of the phototransistor, the Vgs voltage of the phototransistor is adjusted, causing the phototransistor to operate in the off state. Different current responses (i.e., photogenerated carriers) occur based on the different reflection intensities of light from the fingerprint valleys and ridges. These photogenerated carriers integrate within a certain time and are stored in the charge integration capacitor. They are then discharged by the scanning transistor, and subsequently integrated, amplified, and filtered in the charge integration amplifier to detect different signals, ultimately forming a clear fingerprint image and achieving fingerprint recognition.

[0120] Although preferred embodiments of the present disclosure have been described, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of the present disclosure and their equivalents.

Claims

1. A display substrate, characterized in that, include: Substrate; Multiple pixel driving circuits are arranged in an array on the substrate. The pixel driving circuit includes: a driving transistor, a switching transistor, and a storage capacitor; wherein, the driving transistor has a low-temperature polysilicon active layer, the switching transistor has an oxide active layer, the gate of the driving transistor is disposed in the same layer as the second electrode plate of the storage capacitor, the low-temperature polysilicon active layer of the driving transistor is located between the gate layer of the driving transistor and the substrate, and the first and second electrodes of the driving transistor are disposed in the same layer as the first and second electrodes of the switching transistor; Multiple texture recognition circuits are provided, the texture recognition circuits being located at the gaps in the pixel driving circuits; each texture recognition circuit includes a phototransistor, the active layer of which is located on the side of the phototransistor's gate away from the substrate, the first and second electrodes of which are located on the side of the phototransistor's active layer away from the substrate, the phototransistor having an oxide active layer, and the oxide active layer of the phototransistor being disposed in a different layer from the oxide active layer of the switching transistor; It also includes: a first insulating layer and a second insulating layer, wherein the first insulating layer is located between the gate layer of the phototransistor and the oxide active layer of the phototransistor, the second insulating layer is located between the oxide active layer of the phototransistor and the oxide active layer of the switching transistor, and the thickness of the first insulating layer is less than the thickness of the second insulating layer.

2. The display substrate as described in claim 1, characterized in that, The texture recognition circuit further includes: a reset transistor and a scanning transistor; The gate of the reset transistor is electrically connected to the reset signal terminal, the first terminal of the reset transistor is electrically connected to the reference signal terminal, and the second terminal of the reset transistor is electrically connected to the second terminal of the phototransistor. The gate of the scanning transistor is electrically connected to the scanning signal terminal, the first terminal of the scanning transistor is electrically connected to the second terminal of the reset transistor, and the second terminal of the scanning transistor is electrically connected to the read signal terminal.

3. The display substrate as described in claim 2, characterized in that, Both the reset transistor and the scan transistor have an oxide active layer.

4. The display substrate as described in claim 3, characterized in that, The reset transistor and the scan transistor have the same functional film layer disposed on the same layer and have at least one gate; the gate of the phototransistor is disposed on the same layer as the first electrode plate of the storage capacitor.

5. The display substrate as described in claim 4, characterized in that, Both the reset transistor and the scan transistor have a first gate located between the oxide active layer and the substrate, and / or a second gate located on the side of the oxide active layer away from the substrate.

6. The display substrate as described in claim 5, characterized in that, The texture recognition circuit also includes a charge integrating capacitor, which is connected between the first electrode of the phototransistor and the second electrode of the phototransistor.

7. The display substrate as described in claim 6, characterized in that, The charge integrating capacitor includes a first electrode plate and a second electrode plate stacked on the substrate; the first electrode plate of the charge integrating capacitor is disposed on the same layer as the first gate, and the second electrode plate of the charge integrating capacitor is located between the first electrode plate and the substrate.

8. The display substrate according to any one of claims 2 to 7, characterized in that, The plurality of texture recognition circuits are arranged in an array on the substrate. In a single-row texture recognition circuit, the first terminal of each phototransistor is electrically connected to a high-level power supply line, and in a single-row texture recognition circuit, the gate of each phototransistor is electrically connected to a bias signal line. In the texture recognition circuit described in a row, the reset signal terminal of each reset transistor is electrically connected to a reset signal line, and the reference signal terminal of each reset transistor in the texture recognition circuit described in a row is electrically connected to a reference signal line. In a single-row texture recognition circuit, the reading signal terminal of each scanning transistor is electrically connected to a reading signal line, and in a single-row texture recognition circuit, the scanning signal terminal of each scanning transistor is electrically connected to a scanning signal line.

9. The display substrate as described in claim 8, characterized in that, Also includes: Multiple charge integrating amplifiers are electrically connected to the read signal lines in a one-to-one correspondence. The charge integrating amplifier includes a feedback capacitor, an amplifier, and a switch. The first input terminal of the amplifier is electrically connected to the read signal line, the second input terminal of the amplifier is electrically connected to the reference signal line, the feedback capacitor is connected between the first input terminal and the output terminal of the amplifier, and the switch is connected between the first input terminal and the output terminal of the amplifier.

10. The display substrate as described in claim 6 or 7, characterized in that, The switching transistor and the reset transistor are disposed on the same layer with the same functional film layer, and the storage capacitor and the charge integration capacitor are disposed on the same layer.

11. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 10.

12. A method for texture recognition of a display substrate as described in any one of claims 1 to 10, characterized in that, include: During the reset phase, the output terminal of the texture recognition circuit is reset; During the reset phase, a high-level signal is applied to the first terminal of the phototransistor, and a reference signal is applied to the second terminal of the phototransistor, so that a voltage difference is formed between the first and second terminals of the phototransistor. During the integration phase, a bias signal is applied to the gate of the phototransistor, causing the phototransistor to be in a turned-off state, and the phototransistor generates charge carriers under the illumination of the ripple-reflected light. During the reading phase, the photogenerated carriers of the phototransistor are collected at the output terminal of the texture recognition circuit.

Images