Verification Method of Static Random Access Memory Layout
By dividing the static random memory layout into rectangular sub-layers and combining it into verification layouts, the problem of traditional OPC verification methods being too long to verify when processing large-scale layouts is solved, and more efficient layout verification and publication are achieved.
Patent Information
- Application Number
- CN202111376185.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-11-19
- Publication Date
- 2025-04-22
- Estimated Expiration
- 2041-11-19
AI Technical Summary
In semiconductor integrated circuit manufacturing, traditional OPC verification methods use too long verification time when processing large static random memory layouts, which affects the efficiency of layout publishing.
By dividing the static random memory layout into multiple rectangular sub-layers, cutting and combining them into verification sub-layers, then these sub-layers are synthesized into verification layouts, and verification is performed after the optical proximity effect correction.
This method can greatly reduce the area of the verification layout and the complexity of the graphics, significantly shorten the time of OPC verification, and improve the efficiency of layout publishing.
Smart Images
Figure CN114004189B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a static random access memory layout verification method. Background Art
[0002] In the photolithography process of semiconductor integrated circuit manufacturing, it is necessary to perform optical proximity correction (OPC) on the design layout to improve the manufacturability of the pattern.
[0003] As the technology nodes of semiconductor integrated circuits continue to decrease, the complexity of layout design increases. If the traditional method is used for OPC verification, the size of the static random access memory (SRAM) layout is not processed during the verification test run. When the layout is large, the OPC verification time is often too long, affecting the efficiency of layout publishing. The reason is that there is a lack of a fast, effective and universally applicable method to reduce the SRAM layout while ensuring that the graphic pattern is not lost. Summary of the invention
[0004] In order to solve the above technical problems and to quickly verify the static random access memory layout, the present invention provides a static random access memory layout verification method, comprising:
[0005] Step S1, selecting a plurality of storage areas in the static random access memory layout as a plurality of sub-layouts, wherein the sub-layouts are rectangular;
[0006] Step S2, cutting the rectangular areas at the four corners of each of the sub-patterns;
[0007] Step S3, combining the four rectangular areas into a verification sub-pattern;
[0008] Step S4, combining the verification sub-patterns into a verification pattern;
[0009] Step S5, verifying the verification layout after correcting the optical proximity effect.
[0010] Preferably, the length of the sub-pattern is Ai, and the width of the sub-pattern is Bi; the length of the rectangular area is Li, and the width of the rectangular area is Mi; Li is not greater than one quarter of Ai, and Mi is not greater than one quarter of Bi.
[0011] Preferably, in the step S1, the boundary of the periodically repeated pattern in the layout is identified by the baseline pattern of the identification layer, and the memory area is selected by using the boundary.
[0012] Preferably, the length Li and the width Mi of each rectangular region are 4-5 micrometers, the length Li and the width Mi of the same rectangular region are different, and the length Li and the width Mi of different rectangular regions are also different.
[0013] Preferably, in step S3, each of the verification sub-layouts is classified, and in step S4, when the verification sub-layouts are combined into a verification layout, only one verification sub-layout of the same classification is retained in the verification layout.
[0014] Preferably, the method for classifying each of the verification sub-layouts is to classify the verification sub-layouts containing the same periodic repeating pattern in the sub-layouts into the same category. The verification sub-layouts contain at least part of the periodic repeating pattern.
[0015] Preferably, the method for classifying each of the verification sub-layouts is to classify the verification sub-layouts containing the same preset graphics in the sub-layouts into the same category. The verification sub-layouts contain at least part of the preset graphics.
[0016] Compared with the prior art, the static random access memory layout verification method of the present invention can significantly reduce the area of the verification layout and the complexity of the graphics, shorten the time of OPC verification, and improve the efficiency of layout publishing. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A schematic diagram of the steps of the static random access memory layout verification method of Example 1;
[0018] Figure 2 The left side is a schematic diagram of one of the sub-layouts in Example 2, and the right side is a schematic diagram of the combined verification sub-layout;
[0019] Figure 3 The left side is a schematic diagram of the layout of the prior art, the middle is a schematic diagram of the verification layout, and the right side is an enlarged schematic diagram of the verification sub-layout. DETAILED DESCRIPTION
[0020] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also included in the protection scope of the present invention.
[0021] It should be noted that the drawings are all simplified, use non-precise proportions, and are only used to conveniently and clearly assist in illustrating the embodiments.
[0022] Example 1
[0023] like Figure 1As shown, the verification method of the static random access memory layout of this specific embodiment includes:
[0024] Step S1, selecting a plurality of memory areas in the static random access memory layout as a plurality of sub-layouts, wherein the sub-layouts are rectangular;
[0025] Step S2, cutting the rectangular areas at the four corners of each of the sub-patterns;
[0026] Step S3, combining the four rectangular areas into a verification sub-pattern;
[0027] Step S4, combining the verification sub-patterns into a verification pattern;
[0028] Step S5, verifying the verification layout after correcting the optical proximity effect.
[0029] For example, it can be divided into i sub-layouts, the length of the sub-layout is Ai (A1, A2, A3...Ai), and the width is Bi (B1, B2, B3...B i). The length Ai and width Bi of different sub-layouts may be the same or different.
[0030] The length of the rectangular area at the four corners of the sub-layout is Li (L1, L2, L3...Li), and the width is Mi (M1, M2, M3...Mi). The length Li and width Mi of each rectangular area are between 4-5 microns. The length Li and width Mi of the same rectangular area are different, and the length Li and width Mi of different rectangular areas are also different.
[0031] However, in a sub-layout, the length Li of the rectangular area at the four corners is not greater than one-fourth of the length Ai of the sub-layout, and the width Mi of the rectangular area at the four corners is not greater than one-fourth of the width Bi of the sub-layout.
[0032] In step S1, the boundary of the periodically repeated pattern in the layout is identified by the baseline pattern of the identification layer, and the memory area is selected by using the boundary. Figure 3 As shown, the layout on the left can be divided into many sub-layouts.
[0033] like Figure 2 As shown, the left side is one of the sub-layouts, and the right side is the assembled verification sub-layout. The length and width of the rectangular area can be equal to form a square sub-layout. Figure 3 The right side of is the combined verification layout.
[0034] The area of the spliced verification layout is much smaller than the original layout, so the area of the verification layout and the complexity of the graphics can be greatly reduced, the time for OPC verification can be shortened, and the efficiency of layout publishing can be improved.
[0035] Example 2
[0036] On the basis of Example 1, in order to further reduce the verification layout, in step S3, each verification sub-layout is classified, and in step S4, when the verification sub-layouts are assembled into the verification layout, only one verification sub-layout of the same classification is retained in the verification layout.
[0037] The method for classifying each verification sub-layout is to classify the verification sub-layouts containing the same periodic repeating pattern into the same category, and the verification sub-layouts contain at least part of the periodic repeating pattern.
[0038] Example 3
[0039] The classification method of this embodiment is different from that of the second embodiment, and the method for classifying each verification sub-pattern is to classify the verification sub-patterns containing the same preset pattern in the sub-pattern into the same category. The verification sub-patterns contain at least part of the preset pattern.
[0040] The methods of Examples 2 and 3 can further reduce the area of the verification layout and the complexity of the graphics, shorten the time of OPC verification, and improve the efficiency of layout publishing. Figure 3 As shown, the SRAM layout with a length of about 1.8 mm and a width of about 0.3 mm can be reduced to 23 verification sub-layouts with a length and width of about 8 microns, and finally these 23 verification sub-layouts are combined into a verification layout. After the reduction, the verification time is about 20 minutes, which is 90% less than the verification time before the reduction, effectively improving the publishing efficiency.
Claims
1. A static random access memory layout verification method, characterized in that: include: Step S1, selecting a plurality of storage areas in the static random access memory layout as a plurality of sub-layouts, wherein the sub-layouts are rectangular; Step S2, cutting the rectangular areas at the four corners of each of the sub-patterns; Step S3, combining the four rectangular areas into a verification sub-pattern; Step S4, combining the verification sub-patterns into a verification pattern; Step S5, verifying the verification layout after correcting the optical proximity effect.
2. The method for verifying a static random access memory layout as claimed in claim 1, wherein: The length of the sub-pattern is Ai, and the width of the sub-pattern is Bi; The length of the rectangular area is Li, and the width of the rectangular area is Mi; The Li is not greater than one quarter of Ai, and the Mi is not greater than one quarter of Bi.
3. The method for verifying a static random access memory layout as claimed in claim 1, wherein: In the step S1, the boundary of the periodically repeated pattern in the layout is identified by the baseline pattern of the identification layer, and the storage area is selected by using the boundary.
4. The method for verifying a static random access memory layout as claimed in claim 2, wherein: The length Li and the width Mi of each rectangular region are 4-5 micrometers. The length Li and the width Mi of the same rectangular region are different, and the length Li and the width Mi of different rectangular regions are also different.
5. The method for verifying a static random access memory layout as claimed in claim 1, wherein: In the step S3, each of the verification sub-patterns is classified. In the step S4, when the verification sub-patterns are assembled into a verification pattern, only one verification sub-pattern of the same classification is retained in the verification pattern.
6. The method for verifying a static random access memory layout as claimed in claim 5, wherein: The method for classifying each of the verification sub-layouts is to classify the verification sub-layouts containing the same periodically repeated patterns in the sub-layouts into the same category.
7. The method for verifying a static random access memory layout as claimed in claim 5, wherein: The method for classifying each of the verification sub-patterns is to classify the verification sub-patterns containing the same preset graphics in the sub-patterns into the same category.
8. The method for verifying a static random access memory layout as claimed in claim 6, wherein: The verification sub-layout includes at least a portion of the periodically repeated pattern.
9. The method for verifying a static random access memory layout as claimed in claim 7, wherein: The verification sub-pattern includes at least a portion of the preset graphics.
Citation Information
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