A convolutional neural network hardware acceleration platform

Abstract

The present invention discloses a convolutional neural network hardware acceleration platform, comprising a control module, a data calculation module and an external memory, wherein the external memory is used to store input data, output data and weight data, the control module calls the input data and weight data into the data calculation module, the data calculation module comprises an on-chip cache and a calculation logic, and the on-chip cache is divided into an input cache, a weight cache, a convolution intermediate result cache and a pooling intermediate result cache according to the type of stored data; the data calculation module comprises a convolution operator, a pooling operator and a post-processing operator, and the convolution operator and the pooling operator are respectively connected to the post-processing operator; the convolution operator is respectively connected to the control module and the external memory, the pooling operator is respectively connected to the control module and the external memory, and the post-processing operator is connected to the external memory.

Description

Technical Field

[0001] The present invention belongs to the technical field of intelligent computers, and specifically relates to a convolutional neural network hardware acceleration platform. Background Art

[0002] Convolutional Neural Networks (CNN) are a type of feedforward neural network that includes convolutional calculations and has a deep structure. It is one of the representative algorithms of deep learning. Convolutional neural networks have representation learning capabilities and can perform shift-invariant classification on input information according to their hierarchical structure. Therefore, they are also called "Shift-Invariant Artificial Neural Networks (SIANN)".

[0003] In recent years, with the introduction of deep learning theory and the improvement of numerical computing equipment, convolutional neural networks have developed rapidly and have been applied to fields such as computer vision and natural language processing. Convolutional neural networks have achieved great success, especially in image classification, image segmentation, and target tracking, and have been widely used in real life. However, convolutional neural networks have high requirements on the performance of computing platforms. Although computing platforms such as GPU and TPU can meet the high computing power requirements of convolutional neural networks, deploying convolutional neural networks on such general platforms often requires high energy consumption, which brings huge challenges to deploying neural networks in embedded devices with limited energy and heat dissipation conditions. Therefore, there is an urgent need for a hardware acceleration platform designed for convolutional neural networks that can meet the real-time requirements of algorithms while reducing power consumption. Summary of the invention

[0004] In order to achieve the above objectives, reduce the high requirements of convolutional neural networks on data transmission bandwidth and reduce consumption, the present invention proposes a convolutional neural network hardware acceleration platform.

[0005] The present invention adopts the following technical scheme: a convolutional neural network hardware acceleration platform, including a control module, a data calculation module and an external memory, the external memory is used to store input data, output data and weight data, the control module calls the input data and weight data to the data calculation module, the data calculation module includes an on-chip cache and a calculation logic, and the on-chip cache is divided into an input cache, a weight cache, a convolution intermediate result cache and a pooling intermediate result cache according to the type of stored data; the data calculation module includes a convolution operator, a pooling operator and a post-processing operator, the convolution operator and the pooling operator are respectively connected to the post-processing operator; the convolution operator is respectively connected to the control module and the external memory, receives and stores the input data and weight data, and loads The convolution calculation logic completes the two-dimensional convolution part calculation, and stores the obtained intermediate result in the convolution intermediate result cache, and completes the complete two-dimensional convolution operation by switching the convolution intermediate result cache; the pooling operator is connected to the control module and the external memory respectively, receives input data, loads it into the pooling calculation logic to obtain the intermediate result, stores the intermediate result in the pooling intermediate result cache, and completes the complete two-dimensional pooling operation by switching the pooling intermediate result cache; the post-processing operator is connected to the external memory, receives the calculation result and function control instruction of the convolution operator, the calculation result and function control instruction of the pooling operator, and completes the data selection, activation and cumulative bias according to the corresponding function control instruction, and writes the processed output data required to be written into the external memory.

[0006] Furthermore, the convolution operator includes a one-dimensional multiplication systolic array, K×N i ×N o convolution intermediate result buffer, 2×P i Input buffers and P i ×P o weight cache, the bandwidth of each convolution intermediate result cache is B bits, B∈[4,1024]∧B∈Z; or, the pooling operator includes K×P i The bandwidth of each pooled intermediate result buffer is B bits, B∈[4,1024]∧B∈Z;

[0007] where K∈[1,13]∧K∈Z,P i ∈[1,256]∧P i ∈Z,P o ∈[1,256]∧P o ∈Z, where Z represents the set of integers.

[0008] Furthermore, the convolution operator includes a computational convolution function, which is composed of K×N i ×N oOne-dimensional multiplication systolic arrays are implemented, requiring post-processing of data selection, activation, and accumulation bias; or, the pooling operator includes a computational pooling function, consisting of 2×N i A one-dimensional data comparison systolic array is implemented, which requires post-processing of data selection; or, the post-processing operator includes data selection, activation and cumulative bias functions, and the function in the post-processing module is selected for execution according to the control instruction issued by the upper-level operator.

[0009] Among them, the implementation method of data selection is to count the incoming data and discard invalid data in the input data according to the data size in the control instruction issued by the previous level operator; the implementation method of activation is to apply the activation function to the input data; the function of cumulative bias is to output the input after cumulative bias.

[0010] Furthermore, the data calculation module adopts 2×P i ,P i ∈[1,256]∧P i ∈Z input buffers, each with a bandwidth of Bbits, B∈[4,1024]∧B∈Z; the convolution operator calls P i When the input data in the input buffer is i An on-chip cache loads input data from external memory.

[0011] Furthermore, in the convolution operator, in each round of calculation, the convolution operator starts from P i ,P i ∈[1,256]∧P i ∈Z input buffers read out input data, and the input data in each on-chip buffer is broadcast to K×P o ,P o ∈[1,256]∧P o ∈Z,K∈[1,13]∧K∈Z one-dimensional systolic arrays.

[0012] Furthermore, in the convolution operator and the pooling operator, the intermediate results of the calculation are stored in their respective intermediate result caches: the number of convolution intermediate result caches of the convolution operator is M×N, M∈[1,256], N∈[1,256], and the bandwidth of each convolution intermediate result cache is B bits, B∈[1,1024]; the number of pooling intermediate result caches of the pooling operator is M p ×N p ,M p ∈[1,256],N p ∈[1,256], the bandwidth of each pooled intermediate result cache is B bits, B∈[1,1024], and the final result is obtained by accumulating or performing comparison operations by switching the intermediate result cache.

[0013] Furthermore, in the data calculation module, the weight data is stored in a secondary cache structure: the secondary cache area is composed of P i ×P o ,P i ∈[1,256]∧P i ∈Z,P o ∈[1,256]∧P o ∈Z weight caches with bandwidth of B bits, B∈[1,1024]; the capacity of the first-level cache is K×K×P i ×P o K∈[1,13],P i ∈[1,256]∧P i ∈Z,P o ∈[1,256]∧P o ∈Z.

[0014] Furthermore, the input data adopts a block strategy, and the tensor dimension of the input data is I c ×I x ×I y , the block tensor dimension of the input data is T ic ×T ix ×T iy , the block strategy must satisfy I c =m i ×T ic ,m i =p / q,p∈{1,2,3,4},q∈{1,2,3,4},I x =m x ×T ix ,m x =p / q, p∈{1,2,3,4}, q∈{1,2,3,4}.

[0015] Furthermore, the weight data adopts a block strategy, and the tensor dimension of the weight data is W ic ×W oc ×W x ×W y , the block tensor dimension of weight data is T wic ×T woc ×T wx ×T wy , the block strategy must satisfy T wic =m wic ×W ic ,m wic =p / q,p∈{1,2,3,4},q∈{1,2,3,4}, T wx =m wx W x ,m wx=p / q,p∈{1,2,3,4},q∈{1,2,3,4}, T wy =m wy W y ,m wx =p / q, p∈{1,2,3,4}, q∈{1,2,3,4}.

[0016] Furthermore, the control module uses DMA and datamover to complete the scheduling of input data, output data weight data between the data calculation module and the external memory.

[0017] The technical solution of the present invention has the following beneficial effects: a hardware structure for implementing a two-dimensional convolution operation using a one-dimensional multiplication pulsation array is used. Based on the pulsation array, the convolution operation is split to achieve the effect of performing the convolution operation in steps, simplifying the data flow control logic and hardware structure, and reducing the consumption of on-chip logic resources per unit operation. A data scheduling strategy that matches the hardware structure is proposed to fully utilize the computing resources of the acceleration platform while reducing the demand for data transmission bandwidth. A structure of multiple input caches and weight secondary caches is used to reduce the latency and consumption of memory access. The hardware structure of a pooling operator for a one-dimensional data comparison pulsation array is designed. A structure for CPU and FPGA collaborative processing is designed, and the CPU schedules the convolution, pooling, and post-processing operators on the FPGA chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a convolutional neural network hardware acceleration platform is provided for an embodiment of the present invention;

[0019] Figure 2 A schematic diagram of the structure of a two-dimensional convolution operator is provided for an embodiment of the present invention;

[0020] Figure 3 A schematic structural diagram of a two-dimensional pooling operator is provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The specific embodiments of the present invention are further described in conjunction with the accompanying drawings to make the technical solution clearer and more understandable.

[0022] like Figure 1-3 As shown, this embodiment discloses a convolutional neural network hardware acceleration platform, which mainly includes three parts: a control module, a data calculation module and an external memory.

[0023] The data calculation module includes three operators, namely, convolution operator, pooling operator and post-processing operator, and the convolution operator and pooling operator are connected to the post-processing operator respectively. The external memory (DDR) shown is used to store input data and weight data. The control module shown calls the input data and weight data to the data calculation module, and completes the scheduling of convolution, pooling and post-processing operators by sending various configuration instructions. The convolution operator and pooling operator are cascaded to the post-processing operator, and the post-processing operator writes the calculation results to the external memory.

[0024] In the data calculation module, the convolution operator is connected to the control module and the external memory (DDR) respectively, receives and stores the input data and weight data, and loads them into the convolution calculation logic to complete the two-dimensional convolution part calculation;

[0025] The pooling operator is connected to the control module and the external memory respectively, receives input data, stores the intermediate results in the pooling intermediate cache, and completes the complete two-dimensional pooling operation by switching the intermediate result cache; the post-processing operator is connected to the external memory, receives the calculation results and function control instructions of the convolution operator, the calculation results and function control instructions of the pooling operator, and writes them into the external memory after processing according to the corresponding function control instructions.

[0026] The convolution operator and the pooling operator are connected to the post-processing operator, and the post-processing operator writes the calculation result, that is, the output data, into the external memory. The convolution operator and the pooling operator are each connected to the external memory and the control module (CPU).

[0027] The convolution operator contains the function of calculating the convolution, consisting of K×N i ×N o The pooling operator contains the computational pooling function, which consists of 2×N i The one-dimensional data comparison systolic array is implemented, which requires post-processing of data selection. The post-processing operator includes data selection, activation and cumulative bias functions, and selects the function in the post-processing module to execute according to the control instruction issued by the previous operator. Among them, the implementation method of data selection is to count the incoming data and discard invalid data in the input data according to the data size in the control instruction issued by the previous operator; the implementation method of activation is to apply the activation function to the input data; the function of cumulative bias is to output the input after cumulative bias.

[0028] Input data is stored in 2×P i ,P i ∈[1,256]∧P i ∈Z input buffers, each with a bandwidth of Bbits, B∈[4,1024]∧B∈Z. When the external memory (DDR) sendsi When writing data to one input buffer, the convolution operator writes data from another P i The data in each input buffer is broadcast to P o ,P o ∈[1,256]∧P o ∈Z two-dimensional operators.

[0029] The storage of weight data adopts the structure of secondary cache, loading the data in the weight block into the secondary cache, and loading the data called in the next round of calculation in the weight block into the primary cache. Through the above secondary cache structure, the demand for the number of memory particles is reduced while meeting the high bandwidth requirements for loading weight data. Specifically, the weight data is stored in P i ×P o ,P i ∈[1,256]∧P i ∈Z,P o ∈[1,256]∧P o ∈Z weight caches. When calculating, the data in the first-level cache is loaded into the calculation logic, and the weight data required for the next round of calculation is loaded from the second-level cache into the first-level cache. The number of weight data that the first-level cache can accommodate is K×K×P i ×P o where K∈[1,13],P i ∈[1,256]∧P i ∈Z,P o ∈[1,256]∧P o ∈Z. The second-level cache consists of P i ×P o ,P i ∈[1,256]∧P i ∈Z,P o ∈[1,256]∧P o ∈Z weight caches with bandwidth of B bits, B∈[1,1024]∧B∈Z.

[0030] The demand for on-chip cache (BRAM) is reduced by dividing the input data and weight data into blocks. The input data blocks and weight data blocks should meet the following requirements respectively. Assume that the input data dimension is I c ×I x ×I y , where I c Indicates the number of input data channels, I x and I y Indicates the number of columns and rows of a single channel of input data. The input data block dimension is T ic ×T ix ×T iy , where T ic , Tix and T iy Represent the number of columns and rows of the input channels and single channels of input data in the block respectively; then it must satisfy I c =m i ×T ic ,m i =p / q,p∈{1,2,3,4},q∈{1,2,3,4} and I x =m x ×T ix ,m x =p / q,p∈{1,2,3,4},q∈{1,2,3,4}. Let the dimension of weight data be W ic ×W oc ×W x ×W y , where W ic is the number of weight input channels, W oc is the number of weighted output channels, W x and W y is the length and width of the convolution kernel. The weight block dimension is T wic ×T woc ×T wx ×T wy , where T wic , T woc , T wx and T wy Respectively represent the number of input channels, the number of output channels, and the length and width of the convolution kernel in the weighted data block; then T wic =m wic ×W ic ,m wic =p / q,p∈{1,2,3,4},q∈{1,2,3,4}, T wx =m wx W x ,m wx =p / q,p∈{1,2,3,4},q∈{1,2,3,4}, T wy =m wy W y ,m wy =p / q, p∈{1,2,3,4}, q∈{1,2,3,4}.

[0031] When the control module calls the convolution operator, the input data is in size T ic ×T ix ×T iy Block, weight data according to size T wic ×T woc ×T wx ×T wyThe data is divided into blocks, and the divided data is loaded from the external memory into the on-chip cache, and then the data is loaded from the on-chip cache into the calculation logic to complete the two-dimensional convolution calculation. The input data is stored in 2×P i ,P i ∈[1,256]∧P i ∈Z input buffers, when external memory sends P i When writing data to one input buffer, the convolution operator writes data from another P i The input buffer reads data.

[0032] When calculating convolution, the operator in each round of calculation starts from P i ,P i ∈[1,256]∧P i ∈Z input buffers read data, and the data in each input buffer is broadcast to K×P o ,P o ∈[1,256]∧P o ∈Z,K∈[1,13]∧K∈Z one-dimensional systolic arrays, and the weight data is loaded from the first-level cache to the calculation logic. The intermediate results of the calculation are stored in the on-chip cache to which the operator belongs. The calculation result of each one-dimensional systolic array is the intermediate result of the convolution calculation. The accumulation of the intermediate results is completed by switching the intermediate result cache. When the calculation is completed, it is output to the lower-level operator. The pooling operator adopts a structure similar to the convolution. After reading data from the external storage space, the intermediate results are stored in the on-chip cache. The complete two-dimensional pooling operation is completed by switching the intermediate result cache. The calculation results of the convolution and pooling operators are passed to the activation operator to complete the data post-processing. Data post-processing includes functions such as selecting the calculation results of the previous operator, applying the activation function, and accumulating the bias term. The convolution operator and the pooling operator send control instructions to the activation operator. Among them, the convolution operator requires data selection, activation and accumulation of bias functions, and the pooling operator requires data selection function. Finally, the calculation results of the post-processing are written to the external storage space. Repeat the above steps until the calculation of all calculation layers is completed.

[0033] In the convolution and pooling operators, the intermediate results of the calculation are stored in their respective on-chip caches. The intermediate result cache of the convolution operator consists of M×N, M∈[1,256], N∈[1,256] caches, each with B bits, B∈[1,1024]; the intermediate cache of the pooling operator consists of M p ×N p ,M p ∈[1,256],N p ∈[1,256] caches, each with a block size of Bbits, B∈[1,1024], and the final result is obtained by accumulating (or comparing) the intermediate result caches.

[0034] The convolution computing platform consists of K×N i ×N o One-dimensional convolution operators, where K∈[1,13]∧K∈Z,N i ∈[1,256]∧N i ∈Z,N o ∈[1,256]∧N o ∈Z. The one-dimensional convolution operator adopts a hardware structure based on a systolic array. The input data is broadcast to each multiplier of the one-dimensional systolic array, multiplied with the weight data stored in the one-dimensional systolic array, and the intermediate result obtained by calculation is added to the intermediate result stored in the register of the one-dimensional systolic array. The result of the addition is stored in adjacent registers in the one-dimensional systolic array, and the result of the one-dimensional convolution calculation is output. Each group of three one-dimensional operators completes a two-dimensional convolution calculation. The input data is broadcast to the three one-dimensional convolutions in each group, and the output result is passed to the data selector and stored in N p ,N p ∈[2,4]∧N p ∈Z parts and data buffer. The two-dimensional convolution calculation is completed by switching the intermediate result buffer. After all channels of the current input data row are calculated, the corresponding relationship between the convolution intermediate result buffer and the one-dimensional convolution operator is switched, and then the convolution operator calculation result is accumulated in the intermediate result buffer. There are two cases of storing in the convolution intermediate result buffer. When the convolution intermediate result buffer stores the previously calculated intermediate result, the data in the convolution intermediate result buffer is read out and added to the calculation result of the one-dimensional convolution operator and then stored in the convolution intermediate result buffer; when there is no previously calculated intermediate result in the convolution intermediate result buffer, the calculation result of the one-dimensional convolution operator is directly stored in the convolution intermediate result buffer. When the data in the convolution intermediate result buffer is the calculation result of the two-dimensional convolution operation, the data in the convolution intermediate result buffer is transferred to the post-processing operator through the data selector. The process of completing the calculation of all channels of a row of data in the input data is called a round of calculation.

[0035] Pooling uses a hardware structure similar to convolution, consisting of 2×N i ,N i ∈[1,256]∧N i ∈Z one-dimensional pooling operators, and every two one-dimensional pooling operators form a two-dimensional pooling operator. The input data is broadcast to the two one-dimensional pooling operators. The one-dimensional pooling operator is implemented by a one-dimensional data comparison systolic array, and the processing results of the one-dimensional pooling operator are written into the pooling intermediate result buffer. Switching the pooling intermediate result buffer completes the two-dimensional pooling. The result of the completed pooling calculation is input from the pooling intermediate result buffer to the external memory.

[0036] The post-processing operator includes functions to remove useless data, apply activation functions to the output data, and add bias terms. In the calculation results passed in by the convolution operator, the first and last rows in each channel, as well as the first and last data in each row are useless data, and the post-processing operator discards them. Apply the activation function to the selected data, add the bias term, and obtain the final result and output it to the external memory.

[0037] In this embodiment, R represents a set of rational numbers, and Z represents a set of integers.

[0038] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A convolutional neural network hardware acceleration platform, characterized in that: It includes a control module, a data calculation module and an external memory, wherein the external memory is used to store input data, output data and weight data, the control module calls the input data and weight data into the data calculation module, and the data calculation module includes an on-chip cache and a calculation logic, and the on-chip cache is divided into an input cache, a weight cache, a convolution intermediate result cache and a pooling intermediate result cache according to the type of stored data; The data calculation module includes a convolution operator, a pooling operator and a post-processing operator, and the convolution operator and the pooling operator are respectively connected to the post-processing operator; The convolution operator is connected to the control module and the external memory respectively, receives and stores the input data and weight data, and loads them into the convolution calculation logic to complete the two-dimensional convolution part calculation, stores the obtained intermediate results in the convolution intermediate result cache, and completes the complete two-dimensional convolution operation by switching the convolution intermediate result cache; The pooling operator is connected to the control module and the external memory respectively, receives input data, loads it into the pooling calculation logic to obtain intermediate results, stores the intermediate results in the pooling intermediate result cache, and completes the complete two-dimensional pooling operation by switching the pooling intermediate result cache; the post-processing operator is connected to the external memory, receives the calculation results and function control instructions of the convolution operator, the calculation results and function control instructions of the pooling operator, and completes the data selection, activation and cumulative bias according to the corresponding function control instructions. The processed output data is written into the external memory; The convolution operator includes a one-dimensional multiplication systolic array, K×N i ×N o convolution intermediate result buffer, 2×P i Input buffers and P i ×P o weight cache, the bandwidth of each convolution intermediate result cache is B bits, B∈[4,1024]∧B∈Z; or, the pooling operator includes K×P i The bandwidth of each pooled intermediate result buffer is B bits, B∈[4,1024]∧B∈Z; where K∈[1,13]∧K∈Z,P i ∈[1,256]∧P i ∈Z,P o ∈[1,256]∧P o ∈Z, where Z represents the set of integers.

2. A convolutional neural network hardware acceleration platform according to claim 1, characterized in that: The convolution operator contains the function of calculating the convolution, consisting of K×N i ×N o A one-dimensional multiplication systolic array is implemented, requiring post-processing of data selection, activation, and accumulation bias; Alternatively, the pooling operator includes a computational pooling function, which is composed of 2×N i A one-dimensional data comparison systolic array is implemented, which requires post-processing of data selection; Alternatively, the post-processing operator includes data selection, activation and cumulative bias functions, and selects functions in the post-processing module for execution according to control instructions issued by the previous-level operator.

3. A convolutional neural network hardware acceleration platform according to claim 1, characterized in that: The data calculation module adopts 2×P i ,P i ∈[1,256]∧P i ∈Z input buffers, each with a bandwidth of Bbits, B∈[4,1024]∧B∈Z; the convolution operator calls P i When the input data in the input buffer is i An on-chip cache loads input data from external memory.

4. The convolutional neural network hardware acceleration platform according to claim 1, characterized in that: In the convolution operator, in each round of calculation, the convolution operator starts from P i ,P i ∈[1,256]∧P i ∈Z input buffers read out input data, and the input data in each on-chip buffer is broadcast to K×P o ,P o ∈[1,256]∧P o ∈Z,K∈[1,13]∧K∈Z one-dimensional systolic arrays.

5. The convolutional neural network hardware acceleration platform according to claim 1, characterized in that: In the convolution operator and pooling operator, the intermediate results of the calculation are stored in their respective intermediate result caches: The number of convolution intermediate result caches of the convolution operator is M×N, M∈[1,256], N∈[1,256], and the bandwidth of each convolution intermediate result cache is B bits, B∈[1,1024]; The number of pooled intermediate result caches of the pooling operator is M p ×N p ,M p ∈[1,256],N p ∈[1,256], the bandwidth of each pooled intermediate result cache is B bits, B∈[1,1024], and the final result is obtained by accumulating or performing comparison operations by switching the intermediate result cache.

6. A convolutional neural network hardware acceleration platform according to claim 1, characterized in that: In the data calculation module, the weight data is stored in a secondary cache structure: the secondary cache area consists of P i ×P o ,P i ∈[1,256]∧P i ∈Z,P o ∈[1,256]∧P o ∈Z weight caches with bandwidth of B bits, B∈[1,1024]; the capacity of the first-level cache is K×K×P i ×P o K∈[1,13],P i ∈[1,256]∧P i ∈Z,P o ∈[1,256]∧P o ∈Z.

7. A convolutional neural network hardware acceleration platform according to claim 1, characterized in that: The input data adopts a block strategy, and the tensor dimension of the input data is I c ×I x ×I y , the block tensor dimension of the input data is T ic ×T ix ×T iy , the block strategy must satisfy I c = m i ×T ic ,m i =p / q,p∈{1,2,3,4},q∈{1,2,3,4},I x =m x ×T ix ,m x = p / q,p∈{1,2,3,4}, q∈{1,2,3,4}.

8. The convolutional neural network hardware acceleration platform according to claim 1, characterized in that: The weight data adopts a block strategy, and the tensor dimension of the weight data is W. ic ×W oc ×W x ×W y , the block tensor dimension of weight data is T wic ×T woc ×T wx ×T wy , the block strategy must satisfy T wic =m wic ×W ic ,m wic =p / q,p∈{1,2,3,4},q∈{1,2,3,4}, T wx =m wx W x ,m wx =p / q,p∈{1,2,3,4},q∈{1,2,3,4}, T wy =m wy W y ,m wx =p / q, p∈{1,2,3,4}, q∈{1,2,3,4}.

9. The convolutional neural network hardware acceleration platform according to claim 1, characterized in that: The control module uses DMA and datamover to complete the scheduling of input data, output data, and weight data between the data calculation module and the external memory.

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