Electroluminescent display device

Abstract

The present invention provides an electroluminescent display device, which includes: a display panel, the display panel includes pixels, the pixels include driving elements and light-emitting devices; and a panel driving circuit, the panel driving circuit supplies a first data voltage for display driving operation and a display scanning signal synchronized with the first data voltage to the pixels in a vertical effective period after a first vertical blank period, and maintains the first data voltage in the pixels during a second vertical blank period after the vertical effective period, wherein the length of the first vertical blank period is fixed regardless of changes in the frame frequency, and the length of the second vertical blank period changes based on changes in the frame frequency.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0093993, filed on Jul. 28, 2020, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to electroluminescent display devices. Background Art

[0004] Electroluminescent display devices are divided into inorganic light-emitting display devices and electroluminescent display devices based on the material of the light-emitting layer. Each of the plurality of pixels of the electroluminescent display device includes a self-luminous light-emitting device, and the amount of light emitted by the light-emitting device is controlled by using a data voltage based on the grayscale of image data to adjust the brightness.

[0005] Electroluminescent display devices use external compensation technology to improve image quality. The external compensation technology senses pixel voltage or current based on the electrical characteristics of the pixels and modulates the data of the input image based on the sensed result to compensate for the electrical characteristic deviation between pixels.

[0006] However, in the conventional external compensation technology, when the frame frequency changes rapidly, the brightness deviation between the compensated pixels and the non-compensated pixels may increase, and thus, the position of the compensated pixels in the display panel may be recognized by the user. Summary of the invention

[0007] In order to overcome the above-mentioned problems of the related art, the present disclosure can provide an electroluminescent display device that cannot enable a user to recognize the position of a compensated pixel even when the frame frequency is changed based on an input image during the process of compensating for electrical characteristic deviations between pixels based on an external compensation method.

[0008] To achieve these objectives and other advantages, and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, an electroluminescent display device includes: a display panel, the display panel including pixels, the pixels including driving elements and light-emitting devices; and a panel driving circuit, the panel driving circuit supplies a first data voltage for display driving operation and a display scanning signal synchronized with the first data voltage to the pixels in a vertical effective period after a first vertical blank period, and maintains the first data voltage in the pixels during a second vertical blank period after the vertical effective period, wherein the length of the first vertical blank period is fixed regardless of changes in frame frequency, and the length of the second vertical blank period varies based on changes in frame frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate one or more embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0010] Figure 1 is a diagram showing an electroluminescent display device according to an embodiment of the present disclosure;

[0011] Figure 2 It is shown Figure 1 A diagram of a pixel array included in an electroluminescent display device;

[0012] Figure 3 is included in Figure 2 An equivalent circuit diagram of a pixel in a pixel array;

[0013] Figure 4 is a diagram showing an example of transmitting and receiving a signal based on a variable frame frequency between a host system and a timing controller;

[0014] Figure 5 and Figure 6 is a diagram for describing a variable refresh rate (VRR) technique for varying a frame frequency based on an input image;

[0015] Figure 7 and Figure 8 is a diagram for describing an example in which the length of a brightness recovery period varies based on the position of a pixel group line including a sensing pixel in an external compensation technique;

[0016] Fig. 9A and Fig. 9B is a diagram showing an example of differently setting a compensation gain for compensating for a brightness loss based on sensing based on a length of a brightness recovery period;

[0017] Fig.10 is a diagram showing a comparative example of the present disclosure, in which the length of a brightness recovery period corresponding to the same sensing pixel group line is changed based on a change in a frame frequency;

[0018] Fig.11 is a diagram illustrating an embodiment of the present disclosure, in which the length of a brightness recovery period corresponding to the same sensing pixel group line is constant regardless of changes in the frame frequency;

[0019] Fig.12 Shows the application to Fig.11 The waveforms of the data voltage and the scan signal of the sensing pixel group line; and

[0020] Fig.13It is shown that the Fig.11 Diagram of the internal structure of the timing controller of the technical spirit. DETAILED DESCRIPTION

[0021] The advantages and features of the present disclosure and methods for implementing the same will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0022] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the accompanying drawings for describing the various embodiments of the present disclosure are only exemplary, and the present disclosure is not limited thereto. Throughout the entire text, similar reference numerals refer to similar elements. Throughout the specification, the same elements are represented by the same reference numerals. As used in this article, unless the term "only" is used, the terms "including", "having", "comprising" etc. imply that other parts can be added. As used in this article, the singular forms "one", "an" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise.

[0023] Even if not explicitly stated, the elements in the various embodiments of the present disclosure should be construed as including error tolerances.

[0024] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on", "over", "under", and "immediately next to", unless "just" or "directly" is used, one or more other parts may be arranged between the two parts.

[0025] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0026] Like reference numerals refer to like elements throughout.

[0027] In the specification, the gate drive circuit provided on the substrate of the display panel may be implemented with a thin film transistor (TFT) having an n-type metal oxide semiconductor field effect transistor (MOSFET) structure, but is not limited thereto and may be implemented with a TFT having a p-type MOSFET structure. The TFT may be a three-electrode element including a gate, a source and a drain. The source may be an electrode that supplies carriers to the transistor. In the TFT, the carriers may flow from the source. The drain may be an electrode that enables the carriers to flow out of the TFT. That is, in the MOSFET, the carriers flow from the source to the drain. In an n-type TFT (NMOS), because the carriers are electrons, the source voltage may have a lower voltage than the drain voltage, so that the electrons flow from the source to the drain. In an n-type TFT, because the electrons flow from the source to the drain, the current may flow from the drain to the source. On the other hand, in a p-type TFT (PMOS), because the carriers are holes, the source voltage may be higher than the drain voltage, so that the holes flow from the source to the drain. In a p-type TFT, because holes flow from the source to the drain, current can flow from the source to the drain. It should be noted that the source and drain of a MOSFET are not fixed but switched between them. For example, the source and drain of a MOSFET can be switched between them. Therefore, when describing an embodiment of the present disclosure, one of the source and drain will be described as a first electrode, and the other of the source and drain will be described as a second electrode.

[0028] In the following description, when a detailed description of a related known function or configuration is determined to unnecessarily obscure the focus of the present disclosure, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 FIG. 1 is a diagram of a pixel array included in an electroluminescent display device. Figure 3 is included in Figure 2 Equivalent circuit diagram of a pixel in a pixel array.

[0030] Reference Figures 1 to 3 , the electroluminescent display device according to an embodiment of the present disclosure may include a display panel 10, a timing controller 11, a plurality of panel driving circuits 121 and 13, and a sensing circuit (SU) 122. The panel driving circuits 121 and 13 may include a digital analog converter (DAC) 121 connected to a plurality of data lines 15 of the display panel 10 and a gate driver 13 connected to a plurality of gate lines 17 of the display panel 10. The panel driving circuits 121 and 13 and the sensing circuit 122 may be equipped in a data integrated circuit (IC) 12.

[0031] The display panel 10 may include a plurality of data lines 15, a plurality of readout lines 16, and a plurality of gate lines 17. In addition, a plurality of pixels PXL may be respectively disposed in a plurality of pixel regions defined by intersections of the data lines 15, the readout lines 16, and the gate lines 17. Based on the pixels PXL arranged in a matrix type, a plurality of pixels PXL may be disposed in the display region AA of the display panel 10. Figure 2 The pixel array shown in .

[0032] In the pixel array, the pixels PXL can be grouped into a plurality of pixel group lines with respect to one direction. Each of the pixel group lines (lines 1 to 4) may include a plurality of pixels PXL adjacent to each other in the extension direction (or horizontal direction) of the gate line 17. A pixel group line may indicate a group of pixels PXL arranged adjacent to each other in one horizontal direction thereof, rather than a physical signal line. Therefore, the pixels PXL constituting the same pixel group line may be connected to the same gate line 17. The pixels PXL constituting the same pixel group line may be connected to different data lines 15, but are not limited thereto. The pixels PXL constituting the same pixel group line may be connected to different readout lines 16, but are not limited thereto, and a plurality of pixels PXL for realizing different colors may share one readout line 16.

[0033] In the pixel array, each of the pixels PXL may be connected to the DAC 121 through the data line 15, and may be connected to the sensing circuit 122 through the readout line 16. The DAC 121 and the sensing circuit 122 may be embedded in the data IC 12, but are not limited thereto. The sensing circuit 122 may be mounted on a control printed circuit board (PCB) (not shown) outside the data IC 12.

[0034] In the pixel array, each of the pixels PXL may be connected to a high-level pixel power source EVDD through a high-level power source line 18. In addition, each of the pixels PXL may be connected to a gate driver 13 through gate lines 17(1) to 17(4).

[0035] In the pixel array, the pixel PXL may include a plurality of pixels for realizing a first color, a plurality of pixels for realizing a second color, and a plurality of pixels for realizing a third color, and further, may include a plurality of pixels for realizing a fourth color. The first to fourth colors may each be a color selected from red, green, blue, and white.

[0036] Each pixel PXL can be Figure 3, but is not limited thereto. One pixel PXL provided in the kth (where k is an integer) pixel group line may include a light emitting device EL, a driving thin film transistor (TFT) DT, a storage capacitor Cst, a first switching TFT ST1 and a second switching TFT ST2. The first switching TFT ST1 and the second switching TFT ST2 may be connected to the same gate line 17 (k).

[0037] The light emitting device EL can emit light based on the pixel current. The light emitting device EL may include: an anode electrode connected to a source node Ns; a cathode electrode connected to a low-level pixel power supply EVSS; and an organic or inorganic compound layer disposed between the anode electrode and the cathode electrode. The organic or inorganic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When the voltage applied to the anode electrode is higher than the operating point voltage compared to the low-level pixel power supply EVSS applied to the cathode electrode, the light emitting device EL may be turned on. When the light emitting device EL is turned on, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) may move to the emission layer (EML) to generate excitons, and therefore, the emission layer (EML) may emit light.

[0038] The driving TFT DT may be a driving element. The driving TFT DT may generate a pixel current flowing in the light emitting device EL based on a voltage difference between its gate node Ng and source node Ns. The driving TFT DT may include: a gate electrode connected to the gate node Ng; a first electrode connected to a high-level pixel power source EVDD; and a second electrode connected to the source node Ns. The storage capacitor Cst may be connected between the gate node Ng and the source node Ns, and may store a gate-source voltage of the driving TFT DT.

[0039] The first switch TFT ST1 may enable a current to flow between the data line 15 and the gate node Ng based on the gate signal SCAN (k), and may apply a data voltage charged in the data line 15 to the gate node Ng. The first switch TFT ST1 may include: a gate electrode connected to the gate line 17 (k); a first electrode connected to the data line 15; and a second electrode connected to the gate node Ng. The second switch TFT ST2 may enable a current to flow between the readout line 16 and the source node Ns based on the gate signal SCAN (k), and may transfer a voltage of the source node Ns to the readout line 16 based on the pixel current. The second switch TFT ST2 may include: a gate electrode connected to the gate line 17 (k); a first electrode connected to the source node Ns; and a second electrode connected to the readout line 16.

[0040] Such a pixel structure is merely an embodiment, and the technical spirit of the present disclosure is not limited to this pixel structure. It should be noted that the technical spirit of the present disclosure can be applied to various pixel structures for sensing electrical characteristics (eg, threshold voltage or electron mobility) of a driving TFT DT.

[0041] The timing controller 11 may receive a vertical synchronization signal Vsync synchronized with a variable frame frequency, an input data enable signal I-DE, and input image data IDATA from the host system 14 through various interface circuits.

[0042] In a variable frame frequency environment, the length of the vertical effective period can be fixed, and the length of the vertical blank period can be varied based on the frame frequency. The vertical blank period can include a first vertical blank period whose length is fixed and a second vertical blank period whose length varies. The first vertical blank period can be set based on the highest frame frequency within a predetermined range of the variable frame frequency, and therefore, the first vertical blank period can be fixed regardless of the change in the frame frequency. On the other hand, the second vertical blank period can be set to increase as the frame frequency is reduced within a predetermined range of the variable frame frequency, and therefore can vary based on the change in the frame frequency.

[0043] The timing controller 11 may perform a sensing drive operation during the first vertical blank period to ensure a certain sensing period regardless of the change in the frame frequency, thereby increasing the reliability of sensing. The timing controller 11 may arrange the first vertical blank period before the vertical effective period so that the sensing drive operation is first performed before the display drive operation in the same frame, and may arrange the second vertical blank period that is not related to the sensing drive operation after the vertical effective period in which the display operation is performed, and therefore, the problem of the user identifying the position of the compensation pixel due to the brightness deviation between the compensation pixel and the non-compensation pixel can be solved.

[0044] To this end, the timing controller 11 may receive the input image data IDATA and the input data enable signal I-DE, and may modulate the input image data IDATA and the input data enable signal I-DE to be delayed by the first vertical blank period so that the first vertical blank period and the second vertical blank period in one frame cycle have a vertical effective period arranged therebetween. That is, the timing controller 11 may delay the input image data IDATA and the input data enable signal I-DE during a certain period, and then may generate a delayed data enable signal and delayed image data DDATA. Figures 11 to 13 The modulation operation of the timing controller 11 is described.

[0045] In the display operation, the timing controller 11 may generate a first data control signal DDC for controlling the operation timing of the data IC 12 and a first gate control signal GDC for controlling the operation timing of the gate driver 13 based on a plurality of timing signals, such as the vertical synchronization signal Vsync and the delayed data enable signal. In the sensing drive operation, the timing controller 11 may generate a second data control signal DDC for controlling the operation timing of the data IC 12 and a second gate control signal GDC for controlling the operation timing of the gate driver 13 based on the timing signals, such as the vertical synchronization signal Vsync and the input data enable signal I-DE. In addition, the timing controller 11 may also set a brightness recovery drive operation independently of the sensing drive operation and the display drive operation, and in the brightness recovery drive operation, the timing controller 11 may generate a third data control signal DDC for controlling the operation timing of the data IC 12 and a third gate control signal GDC for controlling the operation timing of the gate driver 13 based on the timing signals, such as the vertical synchronization signal Vsync and the input data enable signal I-DE.

[0046] The timing controller 11 can respectively control the display driving timing, sensing driving timing and brightness recovery driving timing of each of the pixel group lines of the display panel 10 based on the gate control signal GDC and the data control signal DDC, and therefore, in the middle of displaying the image, the electrical characteristics of each of the pixels PXL can be sensed in real time through the pixel group line unit.

[0047] Here, the display driving operation may indicate a driving operation of supplying a first data voltage (hereinafter referred to as a display data voltage) for a display driving operation to a pixel group line in one frame based on a line progressive scheme so that the display panel 10 can reproduce an input image. The sensing driving operation may indicate a driving operation of applying a second data voltage (hereinafter referred to as a sensing data voltage) to a pixel PXL disposed in a specific pixel group line (hereinafter referred to as a sensing pixel group line) to sense the electrical characteristics of the corresponding pixel PXL. In addition, the brightness recovery driving operation may be a driving operation of compensating for brightness loss caused by a sensing operation by applying a third data voltage (hereinafter referred to as a brightness recovery data voltage) to which a compensation gain is applied to the pixel PXL of the sensing pixel group line that has completed the sensing operation. The third data voltage may be a voltage obtained by applying a compensation gain to the first data voltage, and thus may be different from the first data voltage.

[0048] The timing controller 11 may control the operation of each of the panel driving circuits 121 and 13 so that the display driving operation is performed in the vertical effective period of one frame, and may control the operation of the sensing circuit 122 and each of the panel driving circuits 121 and 13 so that the sensing operation is performed in the first vertical blank period before the vertical effective period of one frame. In addition, the timing controller 11 may control the operation of each of the panel driving circuits 121 and 13 so that the brightness recovery driving operation is performed between the end time of the sensing driving operation and the start time of the display driving operation.

[0049] The vertical effective period may be a period in which the display data voltage is applied to the pixels PXL provided in all pixel group lines. The first vertical blank period may be a period in which the supply of the display data voltage is stopped, and further, the first vertical blank period may include a sensing period and may partially include a brightness recovery period. In the sensing period, the sensing data voltage may be applied to the pixels PXL provided in the sensing pixel group line, and in the brightness recovery period after the sensing period, the brightness recovery data voltage may be applied to the pixels PXL provided in the sensing pixel group line.

[0050] The gate driver 13 may generate a display scan signal SCAN, a sensing scan signal, and a brightness recovery scan signal, respectively, based on control by the timing controller 11 .

[0051] To implement a display driving operation, in a vertical effective period, the gate driver 13 may generate a display scan signal SCAN based on a first gate control signal GDC according to a delayed data enable signal and may supply the display scan signal SCAN to the gate line 17 based on a line-by-line scan scheme.

[0052] In order to realize the sensing driving operation, in the first vertical blank period before the vertical effective period, the gate driver 13 can generate a sensing scanning signal based on the second gate control signal GDC according to the input data enable signal I-DE, and can supply the sensing scanning signal to the gate line 17, which is connected to the sensing pixel group line.

[0053] Subsequently, in order to implement the brightness recovery driving operation, the gate driver 13 can generate a brightness recovery scanning signal based on the third gate control signal GDC according to the input data enable signal I-DE, and can also supply the brightness recovery scanning signal to the gate line 17, which is connected to the sensing pixel group line.

[0054] In the case of sensing and driving one pixel group line in each first vertical blank period, the positions of the sensing pixel group lines can be randomly distributed based on the operations in multiple first vertical blank periods. When the positions of the sensing pixel group lines are randomly distributed, the adverse effect of identifying the positions of the sensing pixel group lines can be minimized by the visual overall effect.

[0055] The gate driver 13 may be disposed in the non-display area NA of the display panel 10 based on a gate driver in panel (GIP) type.

[0056] The DAC 121 may be connected to the data line 15. The DAC 121 may generate a display data voltage Vdata, a sensing data voltage, and a brightness recovery data voltage, respectively, based on control by the timing controller 11.

[0057] To implement a display driving operation, in a vertical effective period, the DAC 121 may convert delayed image data DDATA into a display data voltage Vdata based on a first data control signal DDC according to a delayed data enable signal, and may supply the display data voltage Vdata to the data line 15 in synchronization with a display scan signal SCAN.

[0058] To implement the sensing driving operation, the DAC 121 may generate a sensing data voltage based on the second data control signal DDC according to the input data enable signal I-DE in a first vertical blank period before the vertical active period, and may supply the sensing data voltage to the data line 15 in synchronization with the sensing scan signal.

[0059] Subsequently, to implement the brightness recovery driving operation, the DAC 121 may generate a brightness recovery data voltage based on the third data control signal DDC according to the input data enable signal I-DE, and may also supply the brightness recovery data voltage to the data line 15 in synchronization with the brightness recovery scan signal.

[0060] In the sensing driving operation, the sensing circuit 122 may be connected to the target pixel PXL of the sensing pixel group line through the readout line 16. In the sensing period included in the first vertical blank period, the sensing circuit 122 may sense the electrical characteristics of the driving TFT DT included in each of the target pixels PXL through the readout line 16. The sensing circuit 122 may be implemented as a voltage sensing type, or may be implemented as a current sensing type.

[0061] The voltage sensing type sensing circuit 122 of the sensing circuit 122 may include a sampling circuit and an analog-to-digital converter (ADC). The sampling circuit may directly sample a specific node voltage of the target pixel PXL stored in the parasitic capacitor of the readout line 16. The ADC may convert the analog voltage obtained by sampling by the sampling circuit into a digital sensing value, and may transfer the digital sensing value to the timing controller 11.

[0062] The current sensing type sensing circuit 122 of the sensing circuit 122 may include a current integrator, a sampling circuit, and an ADC. The current integrator may integrate the pixel current flowing in the target pixel PXL to output a sensing voltage. The sampling circuit may sample the sensing voltage output from the current integrator. The ADC may convert the analog voltage obtained by sampling by the sampling circuit into a digital sensing value, and may transmit the digital sensing value to the timing controller 11.

[0063] The output terminal of the host system 14 may be connected to the timing controller 11 through various interface circuits. The host system 14 may change the frame frequency based on the input image, and may transfer the vertical synchronization signal Vsync, the input data enable signal I-DE, and the input image data IDATA to the timing controller 11 in synchronization with the variable frame frequency. The host system 14 may be mounted on a system board. The host system 14 may include: an input unit that receives user commands / data; a main power unit that generates main power; a variable refresh rate (VRR) control circuit that changes the frame frequency based on the input image; and an output terminal that outputs a transfer signal. The host system 14 may be implemented with an application processor, a personal computer (PC), a set-top box, or a graphics processor unit, but is not limited thereto.

[0064] Figure 4 is a diagram showing an example of transmitting and receiving a signal based on a variable frame frequency between a host system and a timing controller. Figure 5 and Figure 6 is a diagram for describing a VRR technique for varying a frame frequency based on an input image.

[0065] Reference Figure 4 , the host system 14 may use VRR technology based on the Video Electronics Standards Association (VESA) and may include a VRR control circuit. The host system 14 may change the frame frequency based on the input image. The VRR technology may change the frame frequency based on the input image, and thus may prevent tearing and may provide a smoother image screen.

[0066] The VRR control circuit included in the host system 14 can detect the amount of change of the input image in frame units, and can change the frame frequency based on the amount of image change, thereby solving problems such as screen disconnection, screen jitter, and input delay caused by rapid image changes. When the amount of image change is relatively high, the VRR control circuit can increase the frame frequency within a predetermined variable frame frequency range. On the other hand, when the amount of image change is relatively low, the VRR control circuit can reduce the frame frequency within a predetermined variable frame frequency range. For example, the VRR control circuit can adjust the frame frequency within a frequency of about 40 Hz to about 240 Hz based on the amount of image change. The range of the variable frame frequency can be set differently based on the mode and specification.

[0067] As in Figure 5 In the embodiment of the present invention, the host system 14 can fix the length of the vertical effective period VAP, and can adjust the length of the vertical blank period VBP based on the image change amount, thereby changing the frame frequency. In order to achieve smooth signal matching with the timing controller 11, the length of the vertical effective period VAP can be set to be fixed based on the highest frame frequency within a predetermined variable frame frequency range.

[0068] To adjust the length of the vertical blank period VBP, the host system 14 may set and fix the first vertical blank period VBP1 based on the highest frame frequency (eg, 240 Hz), and may adjust the length of the second vertical blank period VBP2 to increase from the first vertical blank period VBP1 based on a decrease in the frame frequency.

[0069] For example, the host system 14 may set the vertical blank period VBP so that the vertical blank period VBP includes only the first vertical blank period VBP1, thereby realizing the Figure 6 The host system 14 may set the vertical blank period VBP so that the vertical blank period VBP includes a first vertical blank period VBP1 and a second vertical blank period VBP2 with an "X" period added from the first vertical blank period VBP1, thereby realizing the 100Hz mode. The host system 14 may set the vertical blank period VBP so that the vertical blank period VBP includes a first vertical blank period VBP1 and a second vertical blank period VBP2 with a "Y" period (Y>X) added from the first vertical blank period VBP1, thereby realizing the 80Hz mode. In addition, the host system 14 may set the vertical blank period VBP so that the vertical blank period VBP includes a first vertical blank period VBP1 and a second vertical blank period VBP2 with a "Z" period (Z>Y) added from the first vertical blank period VBP1, thereby realizing the 60Hz mode.

[0070] Figures 7 to 9Bis a diagram for describing a sensing pixel group line compensation (SLC) technique for compensating for a length deviation of a luminance recovery period with respect to a position of a sensing pixel group line among external compensation techniques.

[0071] The SLC technology can be implemented with simple logic in a fixed frame frequency environment (ie, an environment where the frame frequency is fixed regardless of the amount of change of an input image).

[0072] For example, the following case will be described: when the frame frequency environment is as in Figure 7 In a fixed frame frequency environment of X Hz, pixels of the m-1th pixel group line (i.e., pixels of the pixel group line supplied with SCAN (m-1)) are sensed in the vertical blank period VBP of the N-1th frame, and pixels of the fourth pixel group line (i.e., pixels of the pixel group line supplied with SCAN (4)) are sensed in the vertical blank period VBP of the N-th frame (X Hz).

[0073] In the first display period DTME1, the pixels of the m-1th pixel group line may be charged with a display data voltage based on the m-1th display scan signal SCAN(m-1) (WT-DIS operation), and may then maintain an emission state based on the display data voltage at other times in the first display period DTME1 (HLD-DIS operation). The first display period DTME1 may partially overlap with the vertical active period VAP and the vertical blank period VBP of the N-1th frame.

[0074] In the sensing period STME after the first display period DTME1, the pixels of the m-1th pixel group line may be charged with a sensing data voltage (WT-SEN operation) based on the sensing scan signal and then may be sensed in a non-emission state. The sensing period STME may be in the vertical blank period VBP of the N-1th frame.

[0075] In the first brightness recovery period RTME1 after the sensing period STME, the pixels of the m-1th pixel group line may be charged with a brightness recovery data voltage (WT-RCV operation) based on the brightness recovery scan signal, and then may maintain an emission state (HLD-RCV operation) based on the brightness recovery data voltage at other times in the first brightness recovery period RTME1. The first brightness recovery period RTME1 may partially overlap with the vertical blank period VBP of the N-1th frame and the vertical active period VAP of the Nth frame.

[0076] In the second display period DTME2, the pixels of the fourth pixel group line may be charged with the display data voltage based on the fourth display scan signal SCAN(4) (WT-DIS operation), and then may maintain an emission state based on the display data voltage at other times in the second display period DTME2 (HLD-DIS operation). The second display period DTME2 may partially overlap with the vertical active period VAP and the vertical blank period VBP of the Nth frame.

[0077] In the sensing period STME after the second display period DTME2, the pixels of the fourth pixel group line may be charged with a sensing data voltage based on a sensing scan signal (WT-SEN operation) and then may be sensed in a non-emission state. The sensing period STME may be in a vertical blank period VBP of the Nth frame.

[0078] In the second brightness recovery period RTME2 after the sensing period STME, the pixels of the fourth pixel group line may be charged with a brightness recovery data voltage (WT-RCV operation) based on the brightness recovery scan signal, and then may maintain an emission state (HLD-RCV operation) based on the brightness recovery data voltage at other times of the second brightness recovery period RTME2. The second brightness recovery period RTME2 may partially overlap with the vertical blank period VBP of the Nth frame and the vertical effective period VAP of the N+1th frame.

[0079] Because the frame frequency environment is a fixed frame frequency environment, the length of the vertical blank period VBP of the N-1 frame can be the same as the length of the vertical blank period VBP of the N frame. In addition, in each of the vertical blank period VBP of the N-1 frame and the vertical blank period VBP of the N frame, the sensing period STME can have the same time length. In addition, because the frame frequency environment is a fixed frame frequency environment, the length of one frame required for the display drive operation, the sensing drive operation, and the brightness recovery drive operation performed on the pixels of the m-1 pixel group line can be the same as the length of one frame required for the display drive operation, the sensing drive operation, and the brightness recovery drive operation performed on the pixels of the fourth pixel group line.

[0080] In the vertical blank period VBP of the N-1th frame, the m-1th display scan signal SCAN(m-1) may have a phase earlier than that of the fourth display scan signal SCAN(4). Therefore, for the pixels of the m-1th pixel group line, the first display period DTME1 may be relatively short, and the first brightness recovery period RTME1 may be relatively long.

[0081] In the vertical blank period VBP of the Nth frame, the fourth display scan signal SCAN(4) may have a phase later than that of the m-1th display scan signal SCAN(m-1). Therefore, for the pixels of the fourth pixel group line, the second display period DTME2 may be relatively long, and the second brightness recovery period RTME2 may be relatively short.

[0082] However, as in Figure 8 In the case where all pixels in one screen display an image with the same brightness, the pixels of the sensing pixel group line PXL-B may not emit light during the sensing period STME in the vertical blank period VBP, and thus may achieve a brightness lower by "ΔL" than the pixels of the sensing pixel group line PXL-A. The sensing pixel group line PXL-B may be Figure 7 In the implementation manner of the m-1th pixel group line and the fourth pixel group line.

[0083] exist Figure 7 In an embodiment, the first brightness recovery period RTME1 and the second brightness recovery period RTME2 may be used to compensate for brightness loss. The first brightness recovery period RTME1 and the second brightness recovery period RTME2 may have different time lengths, and therefore, compensation gains may be applied differently thereto. Figure 8 In the embodiment, when the compensation gain is applied, the brightness in the brightness recovery period can be relatively higher than that in the display period, and therefore, all pixels in one screen can achieve substantially the same brightness.

[0084] There may be an inversely proportional relationship between the size of the compensation gain and the time length of the brightness recovery period. All sensing pixel group lines may have a sensing period having the same length regardless of the relative positions of the sensing pixel group lines, and thus may have the same brightness loss. However, the sensing pixel group lines may have brightness recovery periods having different lengths based on the relative positions therebetween, and thus, the size of the compensation gain for compensating for the brightness loss may be applied differently to the sensing pixel group lines.

[0085] As in Fig. 9A In the embodiment, the size of the compensation gain can be set differently for each of the brightness restoration block periods grouped based on a certain time size. Therefore, the compensation gain logic can be simplified and the compensation processing speed can be improved.

[0086] As in Fig. 9B In the embodiment of the present invention, the size of the compensation gain can be set differently for each brightness recovery period of each sensing pixel group line change. Therefore, the accuracy of compensation can be improved.

[0087] The correction operation performed on the image data based on the compensation gain may be performed by the timing controller. The timing controller may also include an SLC compensation logic circuit for applying the compensation gain to the image data to be applied to the pixels of the sensing pixel group line. Figures 7 to 9B The described SLC technology can be implemented with simple logic in a fixed frame frequency environment. The position of the sensing pixel group line can be predetermined for each frame, but because the frame frequency environment is a fixed frame frequency environment, the length of the brightness recovery period corresponding to the same sensing pixel group line may not be changed despite the change of the frame. That is, because the frame frequency environment is a fixed frame frequency environment, the brightness recovery period can be pre-mapped to the position of the sensing pixel group line to have different fixed lengths. In addition, the compensation gain can be pre-set and differently for brightness recovery periods with different fixed lengths.

[0088] Fig.10 is a diagram illustrating a comparative example of the present disclosure, in which the length of a luminance recovery period corresponding to the same sensing pixel group line varies based on a change in a frame frequency.

[0089] It may be difficult to refer to the above Fig. 9A and 9B The described SLC technology is applied to Fig.10 This is because the length of the brightness recovery period corresponding to the same sensing pixel group line varies based on the change of the frame frequency.

[0090] To provide additional description, it can be assumed that in each of the N-1th frame with a frame frequency of J Hz and the Nth frame with a frame frequency of K Hz higher than J Hz, the pixels of the fourth pixel group line (i.e., the pixels of the pixel group line supplied with SCAN(4)) are sensed sequentially.

[0091] As mentioned above Figure 5 and Figure 6 As described above, in a variable frame frequency environment, the time length of each of the vertical active period VAP and the first vertical blank period VBP1 can be set identically in the N-1 frame and the N-th frame regardless of the change in the frame frequency. Therefore, the length of the sensing period STME included in the first vertical blank period VBP1 can be set identically in the N-1 frame and the N-th frame.

[0092] On the other hand, the second vertical blank period VBP2 may be set to be longer in the N-1th frame having a relatively lower frame frequency than the Nth frame. The second vertical blank period VBP2 may determine the length of the brightness recovery period in the N-1th frame and the Nth frame. Therefore, for the same fourth pixel group line, the first brightness recovery period RTME1 of the N-1th frame may be longer than the second brightness recovery period RTME2 of the Nth frame.

[0093] In a variable frame frequency environment where the length of the brightness recovery period varies more based on the frame frequency and the relative position of the sensing pixel group line, the length variation of the brightness recovery period cannot be predicted based on the variation of the frame frequency, and therefore, the SLC technology cannot be applied. This will be described further below.

[0094] The timing controller may determine the frame frequency of each frame with reference to the input data enable signal I-DE transmitted from the host system, rather than receiving information about the variable frame frequency separately from the host system. In a specific frame, the timing controller may determine the transition period of the input data enable signal I-DE (i.e., the period in which pulses are alternately generated between a logic low voltage and a logic high voltage) as the vertical active period VAP of the corresponding frame, and may determine the non-transition period of the input data enable signal I-DE (i.e., the period in which only a logic low voltage is maintained without a pulse) as the vertical blank period (including the first vertical blank period VBP1 and the second vertical blank period VBP2) of the corresponding frame. Therefore, the timing controller may not know the second vertical blank period VBP2 of the N-1 frame until the first pulse of the input data enable signal I-DE starts to rise in the N frame, and further, may not know the second vertical blank period VBP2 of the N frame until the first pulse of the input data enable signal I-DE starts to rise in the N+1 frame. In other words, the timing controller may not be able to predict the length change of the first brightness recovery period RTME1 based on the frame frequency (J Hz) of the N-1th frame, and therefore, it may be difficult to apply an appropriate compensation gain to the first brightness recovery period RTME1. Similarly, the timing controller may not be able to predict the length change of the second brightness recovery period RTME2 based on the frame frequency (K Hz) of the Nth frame, and therefore, it may be difficult to apply an appropriate compensation gain to the second brightness recovery period RTME2.

[0095] When the length deviation of the first brightness recovery period RTME1 and the second brightness recovery period RTME2 corresponding to the same sensing pixel group line is not compensated based on an appropriate compensation gain, the sensing pixel group line may be identified as line dim. The reason for such a problem is that the first vertical blank period VBP1 having a fixed length and the second vertical blank period VBP2 having a length varying based on the frame frequency are successively arranged in the same frame based on the variable frame frequency.

[0096] Fig.11 is a diagram illustrating an embodiment of the present disclosure, in which the length of a brightness recovery period corresponding to the same sensing pixel group line is constant regardless of changes in the frame frequency. Fig.12 Shows the application to Fig.11 The waveforms of the data voltage and the scan signal of the sensing pixel group line.

[0097] Reference Fig.11 and Fig.12 , the electroluminescent display device according to the embodiment of the present disclosure can be used to prevent the user from recognizing the position of the compensated pixel even when the frame frequency is changed based on the input image in the process of compensating the electrical characteristic deviation between pixels based on the external compensation method. In other words, in the electroluminescent display device according to the embodiment of the present disclosure, when the SLC technology is applied in a variable frame frequency environment, the length of the brightness recovery period corresponding to the same pixel group line can be constant regardless of the change in the frame frequency, and therefore, the sensing pixel group line can be prevented from being recognized as line blur.

[0098] As in Fig.11 In a variable frame frequency environment where the N-1 frame to the N+1 frame have different frame frequencies (for example, "I Hz", "K Hz", and "L Hz"), the timing controller can set the length of the first brightness recovery period RTME1 in the N frame and the length of the second brightness recovery period RTME2 in the N+1 frame to be constant regardless of the change in the frame frequency.

[0099] In the same frame, based on the delay of the input signals I-DE and IDATA, the timing controller may arrange the first vertical blank period VBP1 for the sensing driving operation and the brightness recovery driving operation before the second vertical blank period VBP2 for maintaining the display state, and may arrange the second vertical blank period VBP2 for maintaining the display state after the vertical active period VAP. In other words, when a frame configuration arranged in the order of "VAP-VBP1-VBP2" is changed to the order of "VBP1-VAP-VBP2" based on the delay of the input signals I-DE and IDATA, the length of the brightness recovery period corresponding to the same pixel group line may be the same in the Nth frame and the N+1th frame. This is because: the length of the first brightness recovery period RTME1 in the Nth frame and the length of the second brightness recovery period RTME2 in the N+1th frame are determined regardless of the second vertical blank period VBP2 whose length varies based on the rate of the frame frequency.

[0100] To this end, an electroluminescent display device according to an embodiment of the present disclosure may include a display panel ( Figure 1 10) Sensing circuit ( Figure 1 122) and multiple panel drive circuits ( Figure 1 121 and 13), and in addition, may also include a host system ( Figure 1 14) and timing controller ( Figure 1 11).

[0101] In the Nth frame, the operation of the electroluminescent display device associated with one frame configuration change ("VBP1-VAP-VBP2") will be briefly described below.

[0102] The host system 14 may output the input image data IDATA and the input data enable signal I-DE of the N-th frame in synchronization with the frame frequency having K Hz.

[0103] The timing controller 11 may receive the input image data IDATA and the input data enable signal I-DE of the Nth frame from the host system 14. The timing controller 11 may modulate the input image data IDATA and the input data enable signal I-DE of the Nth frame. In other words, the timing controller 11 may delay the input image data IDATA of the Nth frame by the first vertical blank period VBP1, and may delay the input data enable signal I-DE of the Nth frame by the first vertical blank period VBP1. The length of the first vertical blank period VBP1 may be set based on the highest frame frequency within a predetermined range of the variable frame frequency, and the length of the first vertical blank period VBP1 may be fixed regardless of the change in the frame frequency.

[0104] In a frame period corresponding to the Nth frame, based on the delay of the input signals I-DE and IDATA of the Nth frame, the timing controller 11 may rearrange the first vertical blank period VBP1 before the vertical effective period VAP, and may rearrange the second vertical blank period VBP2 after the vertical effective period VAP. The length of the second vertical blank period VBP2 may vary based on the change of the frame frequency. In the case where the range of the variable frame frequency includes the lowest first frame frequency and the highest second frame frequency, the length of the second vertical blank period VBP2 may be the longest in the first frame frequency, and may be the shortest in the second frame frequency.

[0105] The timing controller 11 may generate a first gate control signal GDC and a first data control signal DDC based on the delayed data enable signal D-DE of the Nth frame. The timing controller 11 may supply delayed image data DDATA, the first gate control signal GDC, and the first data control signal DDC to the panel driving circuits 121 and 13 during the vertical active period VAP of the Nth frame.

[0106] The timing controller 11 may generate a second gate control signal GDC, a second data control signal DDC, a third gate control signal GDC, and a third data control signal DDC based on the delayed data enable signal D-DE of the Nth frame. The timing controller 11 may supply the second gate control signal GDC, the second data control signal DDC, the third gate control signal GDC, and the third data control signal DDC to the panel driving circuits 121 and 13 during the first vertical blank period VBP1 of the Nth frame.

[0107] The panel driving circuits 121 and 13 may drive pixels (pixels supplied with SCAN( 4 )) of a fourth pixel group line designated as a sensing pixel group line in the Nth frame (hereinafter referred to as target pixels) based on control by the timing controller 11 .

[0108] In the vertical active period VAP of the Nth frame, the panel driving circuits 121 and 13 may generate a first data voltage Vdata1 for a display driving operation and a display scanning signal P1 synchronized with the first data voltage Vdata1 based on the first gate control signal GDC and the first data control signal DDC. In the vertical active period VAP of the Nth frame, the panel driving circuits 121 and 13 may apply the first data voltage Vdata1 and the display scanning signal P1 to the target pixel (WT-DIS operation) to display drive the target pixel (HLD-DIS operation). The WT-DIS operation may be performed in the display period DTME included in the vertical active period VAP of the Nth frame, and the HLD-DIS operation may be performed in the vertical active period VAP and the second vertical blank period VBP2 of the Nth frame.

[0109] In the first vertical blank period VBP1 before the vertical active period VAP of the Nth frame, the panel driving circuits 121 and 13 may generate a second data voltage Vdata2 for a sensing driving operation and a sensing scanning signal P2 synchronized with the second data voltage Vdata2 based on the second gate control signal GDC and the second data control signal DDC. In the first vertical blank period VBP1 of the Nth frame, the panel driving circuits 121 and 13 may apply the second data voltage Vdata2 and the sensing scanning signal P2 to the target pixel (WT-SEN operation) to sense-drive the target pixel. In the sensing driving operation, a plurality of driving elements included in the target pixel may operate based on the second data voltage Vdata2, and a plurality of non-luminescent elements included in the target pixel may not emit light. Such a WT-SEN operation may be performed in the sensing period STME included in the first vertical blank period VBP1.

[0110] In the sensing period STME, the sensing circuit 122 may sense electrical characteristics (eg, threshold voltage or electron mobility) of a driving element included in a target pixel.

[0111] The panel driving circuits 121 and 13 can generate a third data voltage Vdata3 for a brightness recovery driving operation and a brightness recovery scanning signal P3 synchronized with the third data voltage Vdata3 based on the third gate control signal GDC and the third data control signal DDC in the brightness recovery period RTME of the Nth frame, and the brightness recovery period RTME is between the end time of the sensing period STME and the generation time of the display scanning signal P1. The third data voltage Vdata3 for the brightness recovery driving operation can be a data voltage to which a compensation gain is applied so as to compensate for the brightness loss caused by non-light emission during the sensing period STME. As shown in Fig. 9A and Fig. 9B In the embodiment, the compensation gain can be set to be the highest for the pixel group line with the shortest length relative to the brightness recovery period RTME (for example, the pixel group line supplied with SCAN(1) in the Nth frame), and can be set to be the lowest for the pixel group line with the longest length relative to the brightness recovery period RTME (for example, the pixel group line supplied with SCAN(m) in the Nth frame). The panel driving circuits 121 and 13 can supply the third data voltage Vdata3 and the brightness recovery scan signal P3 to which the compensation gain is applied to the target pixel in the brightness recovery period RTME of the Nth frame (WT-RCV operation) to drive the target pixel for brightness recovery (HLD-RCV operation). This WT-RCV operation can be performed in the first vertical blank period VBP1 of the Nth frame, and the HLD-RCV operation can be performed until the display scan signal P1 is generated in the vertical effective period VAP of the Nth frame.

[0112] As in Fig.12 The technical spirit of this embodiment can be expressed.

[0113] exist Fig.12 , "K Hz" of the Nth frame may be a frame frequency relatively higher than "L Hz" of the N+1th frame.

[0114] Reference Fig.12 , Gate Driver( Figure 1 13) can output a first scan signal (SCAN, P2) synchronized with a sensing data voltage Vdata2, a second scan signal (SCAN, P3) synchronized with a brightness recovery data voltage Vdata3, and a third scan signal (SCAN, P1) synchronized with a display data voltage Vdata1 in sequence to the same gate line connected to one pixel in the same frame. Here, one pixel can be driven in a variable frame frequency environment, and for example, can be driven at a first frame frequency (K Hz) in a first frame (Nth frame), and can be driven at a second frame frequency (L Hz) lower than the first frame frequency (K Hz) in a second frame (N+1th frame).

[0115] Based on the above-mentioned delay of the input signals I-DE and IDATA, the interval between the rising edge of the second scan signal (SCAN, P3) and the rising edge of the third scan signal (SCAN, P1) (i.e., the brightness recovery period) can be the same in the first frame and the second frame. In other words, the brightness recovery period can be fixed regardless of the rate of the frame frequency.

[0116] To this end, the first scan signal (SCAN, P2) and the second scan signal (SCAN, P3) may be output in the first vertical blank period VBP1, and the third scan signal (SCAN, P1) may be output in the vertical active period VAP later in time than the first vertical blank period VBP1. The length of the first vertical blank period VBP1 may be the same in the first frame and the second frame, and the length of the vertical active period VAP may be the same in the first frame and the second frame.

[0117] In addition, a second vertical blank period VBP2 later in time than the vertical active period VAP may be in the same frame, and the length of the second vertical blank period VBP2 may be different in the first frame and the second frame. The length of the second vertical blank period VBP2 in the second frame may be longer than that in the first frame.

[0118] According to the present embodiment, the length of the brightness recovery period RTME1 or RTME2 corresponding to the same pixel group line can be constant regardless of the change in the frame frequency. This is because: the timing controller 11 delays the input signals I-DE and IDATA of each frame, and thus ensures that the first vertical blank period VBP1 with a fixed length is before the vertical effective period VAP, and the sensing driving operation and the brightness recovery driving operation are implemented by using the first vertical blank period VBP1.

[0119] According to the present embodiment, since the length of the brightness recovery period changes only based on the order in which the plurality of display scan signals SCAN(1) to SCAN(m) are supplied and does not change based on the change in the frame frequency, the timing controller 11 can apply a compensation gain suitable for the length of the brightness recovery period to the image data, and can supply the image data to which the compensation gain is applied to the panel driving circuits 121 and 13. Therefore, the panel driving circuits 121 and 13 can generate a third data voltage to which an appropriate compensation gain is applied, and can apply the generated third data voltage to the pixels of the sensing pixel group line, thereby preventing the sensing pixel group line from being recognized as line blur.

[0120] Fig.13 It is shown that the Fig.11 FIG. 1 is a diagram of the internal structure of the timing controller 11 of the technical spirit.

[0121] Reference Fig.13 The timing controller 11 may include an input circuit 111 , a control circuit 112 , a delay circuit 113 and a signal output circuit 114 .

[0122] The input circuit 111 may receive input image data IDATA of each frame synchronized with a variable frame frequency, an input data enable signal I-DE, and a vertical synchronization signal Vsync from a host system through a receiving terminal.

[0123] The control circuit 112 may check transition and timing of each of the input signals IDATA, I-DE, and Vsync, and may generate a delay control signal DDT and a sensing control signal SST based on the input signals IDATA, I-DE, and Vsync.

[0124] The delay circuit 113 may delay the input image data IDATA of each frame by a first vertical blank period having a fixed length based on the delay control signal DDT, and may delay the transition period of the input data enable signal I-DE of each frame by the first vertical blank period. The delay circuit 113 may delay the input image data IDATA and the input data enable signal I-DE by using an external memory outside the timing controller 11 to generate delayed image data DDATA and delayed data enable signal D-DE. In addition, the delay circuit 113 may supply the input data enable signal I-DE, the delayed data enable signal D-DE, and the delayed image data DDATA to the signal output circuit 114 through the output terminal.

[0125] In each frame, the signal output circuit 114 may generate first to third data control signals DDC and first to third gate control signals GDC for controlling the operation timing of the panel driving circuit, so that the sensing driving operation, the brightness recovery driving operation, and the display driving operation are sequentially performed. The signal output circuit 114 may supply the delayed image data DDATA together with the first to third data control signals DDC and the first to third gate control signals GDC to the panel driving circuit.

[0126] According to an embodiment of the present disclosure, even when the frame frequency is changed based on an input image in the process of compensating for an electrical characteristic deviation between pixels based on an external compensation method, a user may not recognize the position of a compensation pixel.

[0127] The effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.

[0128] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. An electroluminescent display device, comprising: A display panel, the display panel comprising pixels, the pixels comprising a driving element and a light emitting device; a panel driving circuit that supplies a first data voltage for a display driving operation and a display scanning signal synchronized with the first data voltage to the pixel in a vertical effective period following a first vertical blank period, and maintains the first data voltage in the pixel during a second vertical blank period following the vertical effective period; as well as a sensing circuit configured to sense an electrical characteristic of the driving element in a sensing period in the first vertical blank period, wherein the length of the first vertical blank period is fixed regardless of a change in the frame frequency, and the length of the second vertical blank period varies based on a change in the frame frequency, wherein the brightness recovery period is between the end time of the sensing period and the generation time of the display scanning signal, and The length of the brightness recovery period corresponding to the same pixel group line is constant regardless of the change of the frame frequency.

2. The electroluminescent display device according to claim 1, wherein: The length of the first vertical blank period is fixedly set based on a highest frame frequency within a predetermined range of variable frame frequencies.

3. The electroluminescent display device according to claim 2, wherein: The predetermined range of the variable frame frequency includes a first frame frequency and a second frame frequency higher than the first frame frequency, and A length of the second vertical blank period at the first frame frequency is longer than a length of the second vertical blank period at the second frame frequency.

4. The electroluminescent display device according to claim 1, wherein: The panel driving circuit supplies a second data voltage for a sensing driving operation and a sensing scanning signal synchronized with the second data voltage to the pixel in the sensing period, and During the sensing period, the driving element operates based on the second data voltage, and the light emitting device does not emit light.

5. The electroluminescent display device according to claim 1, wherein: The panel driving circuit supplies a third data voltage and a brightness recovery scanning signal synchronized with the third data voltage to the pixel in the brightness recovery period.

6. The electroluminescent display device according to claim 5, wherein: The third data voltage is different from the first data voltage.

7. The electroluminescent display device according to claim 6, wherein: The third data voltage is generated by applying a compensation gain to the first data voltage.

8. The electroluminescent display device according to claim 7, wherein: The pixel is included in one of a plurality of pixel group lines to which the display scanning signal is sequentially supplied, In the same frame, the length of the brightness recovery period is longer in the second pixel group line than in the first pixel group line, and The display scanning signal is supplied earlier in the first pixel group line than in the second pixel group line.

9. The electroluminescent display device according to claim 8, wherein: A compensation gain when the pixel is included in the first pixel group line is greater than a compensation gain when the pixel is included in the second pixel group line.

10. The electroluminescent display device according to claim 1, further comprising: a host system that outputs input image data and an input data enable signal in synchronization with a variable frame frequency; as well as A timing controller delays the input image data and the input data enable signal by using a memory.

11. The electroluminescent display device according to claim 10, wherein: The input image data is delayed by the first vertical blank period, and the input data enable signal is delayed by the first vertical blank period.

12. The electroluminescent display device according to claim 11, wherein: During the vertical effective period, a first gate control signal and a first data control signal generated based on delayed image data obtained by the delay and a delayed data enable signal synchronized with the delayed image data are supplied to the panel driving circuit, and During the first vertical blank period, second and third gate control signals and second and third data control signals generated based on the input data enable signal are supplied to the panel driving circuit.

13. The electroluminescent display device according to claim 12, wherein: The panel driving circuit: generating the first data voltage and the display scanning signal based on the first gate control signal and the first data control signal, generating a second data voltage for a sensing driving operation and a sensing scan signal synchronized with the second data voltage based on the second gate control signal and the second data control signal, and A third data voltage and a brightness recovery scanning signal synchronized with the third data voltage are generated based on the third gate control signal and the third data control signal.

14. An electroluminescent display device comprising: A display panel, the display panel comprising pixels, the pixels comprising a driving element and a light emitting device; as well as a gate driver, wherein the gate driver sequentially outputs a first scanning signal synchronized with a sensing data voltage, a second scanning signal synchronized with a brightness recovery data voltage, and a third scanning signal synchronized with a display data voltage to a same gate line connected to the pixel in the same frame, in, The pixels are driven at a first frame frequency in a first frame and at a second frame frequency lower than the first frame frequency in a second frame, and An interval between a rising edge of the second scanning signal and a rising edge of the third scanning signal is the same in the first frame and the second frame.

15. The electroluminescent display device according to claim 14, wherein: In the same frame, The first scanning signal and the second scanning signal are output in a first vertical blank period, and The third scanning signal is output in a vertical effective period that is later in time than the first vertical blank period.

16. The electroluminescent display device according to claim 15, wherein: The length of the first vertical blank period is the same in the first frame and the second frame, and The length of the vertical effective period is the same in the first frame and the second frame.

17. The electroluminescent display device according to claim 15, wherein: A second vertical blank period that is later in time than the vertical effective period is in the same frame, and The length of the second vertical blank period is different in the first frame and the second frame.

18. The electroluminescent display device according to claim 17, wherein: A length of the second vertical blank period in the second frame is longer than a length of the second vertical blank period in the first frame.

19. The electroluminescent display device according to claim 14, wherein: In the same frame, the interval varies according to an order in which the same gate line is supplied with a combination of the first, second, and third scan signals with respect to other gate lines.

Images