Method for forming a semiconductor structure

Abstract

An embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, a gate dielectric layer, and an undoped polysilicon layer stacked in sequence; performing a thermal doping process to dope a first doping ion in the polysilicon layer; performing an ion implantation process to dope a second doping ion in a preset region of the polysilicon layer, and in a direction perpendicular to the surface of the substrate, there is a preset distance between the preset region and the surface of the polysilicon layer facing away from the gate dielectric layer. The present invention is beneficial to reducing the capacitance equivalent thickness of the semiconductor structure and increasing the capacitance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductors, and particularly to a method for forming a semiconductor structure. Background Art

[0002] The capacitance of a transistor is one of the performance indicators of the transistor. In the prior art, the capacitance of the transistor is often increased by thinning the physical thickness of the gate dielectric layer. However, this approach has the risk of breakdown due to the overly thin gate dielectric layer.

[0003] The current main technical means is to reduce the thickness of the gate depletion layer while keeping the thickness of the gate dielectric layer unchanged, so as to reduce the equivalent capacitance thickness and increase the capacitance of the transistor. Summary of the Invention

[0004] Embodiments of the present invention provide a method for forming a semiconductor structure, which is beneficial to reducing the equivalent capacitance thickness of the semiconductor structure and increasing the capacitance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising providing a substrate, a gate dielectric layer, and an undoped polysilicon layer stacked in sequence; performing a thermal doping process to dope a first doping ion in the polysilicon layer; performing an ion implantation process to dope a second doping ion in a preset region of the polysilicon layer, and in a direction perpendicular to the surface of the substrate, there is a preset spacing between the preset region and the surface of the polysilicon layer facing away from the gate dielectric layer.

[0006] In addition, the preset spacing is 1 nm to 10 nm. Since the concentration difference is the basic condition for diffusion, after the thermal doping process is completed, in the direction from the top surface to the bottom surface of the polysilicon layer, the concentration of the first doping ion actually decreases step by step. Therefore, the deeper the preset region is, the greater the concentration difference between the preset region and the surrounding region is, the faster the diffusion rate of the second doping ion is, and the higher the concentration of the second doping ion in the region of the polysilicon layer close to the gate dielectric layer is; correspondingly, when carriers migrate under the action of an electric field to form a depletion layer, if the number of migrating carriers is certain, the higher the concentration of the second doping ion in the part of the polysilicon layer close to the gate dielectric layer is, the smaller the thickness of the depletion layer is, the smaller the equivalent capacitance thickness is, and the larger the capacitance of the transistor is; at the same time, to avoid greater damage to the polysilicon layer due to the longer range of the ion implantation process, it is necessary to limit the preset spacing to ensure good performance of the polysilicon layer.

[0007] In addition, the second doping ion is different from the first doping ion, and the weight of the second doping ion is less than that of the first doping ion. Compared with heavy ion implantation, light ion implantation generates a lower damage density in the polysilicon layer. The lower density of damage can be better repaired through a heat treatment process performed before or after, thereby ensuring that the polysilicon layer has good performance.

[0008] In addition, the second doping ion includes at least one of boron ions, boron fluoride ions, or boron difluoride ions.

[0009] In addition, the thermal doping process includes a doping process and a first heat treatment process performed in sequence. The doping process dopes the first doping ion in the surface layer region of the polysilicon layer far from the gate dielectric layer, and the first heat treatment process causes the first doping ion to diffuse in the polysilicon layer.

[0010] In addition, the doping process includes a plasma ion implantation process. When performing ion implantation by the plasma ion implantation process, there is no screening by an analyzing electric field. The ion implantation amount per unit time is relatively large, the production capacity is high, and a first doping ion with a relatively high concentration can be doped in the surface layer region.

[0011] In addition, the concentration of the first doping ion doped by the plasma ion implantation process in the surface layer region is greater than the solid solubility limit of the first doping ion in the polysilicon layer.

[0012] In addition, the first heat treatment process includes a rapid thermal annealing process. The rapid thermal annealing process has a short annealing time, which is beneficial to reducing the thermal shock suffered by the polysilicon layer and ensuring that the polysilicon layer has excellent structural performance. In addition, compared with furnace annealing, the rapid thermal annealing process has the advantages of less thermal budget, less movement of impurities in silicon, less contamination, and short processing time.

[0013] In addition, after performing the ion implantation process, a second heat treatment process is performed, and the second doping ion diffuses by relying on the second heat treatment process. The second doping ion can diffuse by relying on a heat treatment process performed later, and the heat treatment process performed later is beneficial to repairing the damage caused by the ion implantation process. In this way, it is beneficial to make the region of the polysilicon layer close to the gate dielectric layer have a higher concentration of the second doping ion, and it is beneficial to make the polysilicon layer have less structural damage.

[0014] In addition, after performing the ion implantation process, a blocking layer is formed on the surface of the polysilicon layer far from the gate dielectric layer, and the blocking layer is used to block ion migration. The blocking layer is used to block the further migration of the first doping ion and the second doping ion, thereby controlling the capacitance equivalent thickness range and ensuring that the semiconductor structure has a relatively reasonable capacitance equivalent thickness.

[0015] In addition, it further includes forming a metal blocking film on the surface of the polysilicon layer away from the gate dielectric layer; performing a second heat treatment process on the metal blocking film to form a metal blocking layer, and the second doped ions diffuse by relying on the second heat treatment process.

[0016] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0017] In the above technical solution, performing an ion implantation process after the thermal doping process can make the doping ion concentration at any position in the polysilicon layer exceed the solid solubility limit of the doping ions in the substrate, which is beneficial to thinning the thickness of the depletion layer and thus increasing the capacitance; in addition, doping the second doped ions in a preset area having a spacing from the top surface is beneficial to improving the diffusion rate of the second doped ions and the doping ion concentration in the part of the polysilicon layer close to the gate dielectric layer, which is beneficial to making the thickness of the depletion layer thinner when the number of carrier migrations is certain, that is, the capacitance equivalent thickness is thinner and the capacitance of the semiconductor structure is larger. Description of the Drawings

[0018] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a proportional limitation.

[0019] Figures 1 to 3 Schematic diagrams corresponding to the steps of a method for forming a semiconductor structure;

[0020] Figure 4 Schematic diagram of the change of the doping ion concentration at a certain position in the polysilicon layer with the doping time;

[0021] Figure 5 Schematic diagram of the change of the capacitance equivalent thickness of the polysilicon layer with the doping time;

[0022] Figures 6 to 11 Schematic diagrams corresponding to the steps of a method for forming a semiconductor structure provided by an embodiment of the present invention;

[0023] Figure 12 and Figure 13 Schematic diagrams corresponding to the steps of a method for forming a semiconductor structure provided by another embodiment of the present invention.

[0024] Wherein, 11, 21, 31: substrate; 12, 22, 32: gate dielectric layer; 130, 230: undoped polysilicon layer; 131, 231: initial doping region; 13, 23, 33: doped polysilicon layer; 232: preset area; d: preset spacing; 24: blocking layer; 341: metal blocking film; 34: metal blocking layer. Detailed implementation mode

[0025] Reference Figures 1 to 3 , Figures 1 to 3 is a schematic diagram of a method for forming a semiconductor structure.

[0026] The method for forming a semiconductor structure includes: providing a substrate 11, a gate dielectric layer 12, and an undoped polysilicon layer 130 stacked in sequence; performing a doping process to dope doping ions in the surface region of the undoped polysilicon layer 130 facing away from the gate dielectric layer 12 to form an initial doped region 131; performing a heat treatment process to cause the doping ions in the initial doped region 131 to diffuse downward to form a doped polysilicon layer 13.

[0027] It should be noted that the thermal doping process of doping ions can generally be divided into two types: limited source diffusion and constant surface source diffusion. Limited source diffusion means that during the diffusion process, the total number of doping ions in the thin layer on the surface of the polysilicon layer doped before diffusion is limited and remains unchanged, and these limited doping ions diffuse into other regions in the polysilicon layer; constant surface source diffusion means that the polysilicon layer is always in an atmosphere containing a source during the diffusion process, that is, the concentration of the thin layer on the surface of the polysilicon layer remains unchanged, and only the number of doping ions in the polysilicon layer increases continuously over time.

[0028] Simply put, limited source diffusion means performing a heat treatment process after the doping process, and constant surface source diffusion means performing a heat treatment process during the doping process. However, no matter which diffusion method is used, it will be limited by the solid solubility of doping ions.

[0029] Specifically, since the concentration difference is one of the basic conditions for diffusion, during the thermal doping process, in the diffusion direction of the doping ions, the concentration of the doping ions must decrease step by step. For limited source diffusion, when the doping ions in the surface thin layer complete the redistribution of the concentration step-by-step decrease, the diffusion will stop; for constant surface source diffusion, when the concentration of the doping ions in the surface thin layer is higher than the solid solubility limit and the diffusion can continue relying on the concentration difference, the diffusion will stop.

[0030] That is to say, whether it is limited source diffusion or constant surface source diffusion, due to the limitation of the concentration difference, the concentration of doping ions in some regions cannot reach the solid solubility limit, and the concentration of doping ions at any position will not exceed the solid solubility limit. This results in a limited total number of doping ions in the polysilicon layer, and the doping ions are more concentrated in the part of the polysilicon layer facing away from the gate dielectric layer. When the doping ions migrate under the action of an electric field to form a depletion layer, since the concentration of doping ions in the region close to the gate dielectric layer is relatively low, it is easier to form a thicker depletion layer, thereby resulting in a larger equivalent thickness of the capacitor and a smaller capacitance value.

[0031] Reference Figure 4 , Figure 4 is a schematic diagram showing the change of the doping ion concentration at a certain position in the polysilicon layer with the doping time. The horizontal axis represents the doping time, and the vertical axis represents the doping ion concentration at a certain position. As the doping process proceeds, the doping ion concentration at a certain position tends to saturate and cannot break through the solid solubility limit, which may lead to the ineffectiveness of the doping process or the stoppage of the diffusion process; reference Figure 5 , Figure 5 is a schematic diagram showing the change of the capacitance equivalent thickness of the polysilicon layer with the doping time. The horizontal axis represents the doping time, and the vertical axis represents the capacitance equivalent thickness. As the doping process proceeds, due to the saturation of the doping ion concentration in the polysilicon layer, the capacitance equivalent thickness also tends to saturate.

[0032] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure. After performing a thermal doping process, an ion implantation process is carried out, so that the doping ion concentration in the polysilicon layer can exceed the solid solubility limit of the doping ions, which is beneficial to thinning the thickness of the depletion layer and thus reducing the capacitance equivalent thickness. In addition, doping a second doping ion in the region spaced from the top surface is beneficial to increasing the diffusion rate of the second doping ion and increasing the doping ion concentration in the part of the polysilicon layer close to the gate dielectric layer, which is beneficial to making the thickness of the depletion layer thinner, that is, the capacitance equivalent thickness is thinner and the capacitance is larger when the number of carrier migrations is constant.

[0033] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present invention, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0034] Figures 6 to 11 is a schematic diagram corresponding to each step of a method for forming a semiconductor structure provided by an embodiment of the present invention.

[0035] Reference Figure 6 , a substrate 21, a gate dielectric layer 22, and an undoped polysilicon layer 230 are provided and stacked in sequence.

[0036] Doping ions can be doped in the substrate 21 to form a doped region and a channel region located between adjacent doped regions. After doping the doping ions in the substrate 21, the substrate 21, the gate dielectric layer 22, and the doped polysilicon layer together can form a MOS transistor. The type of the MOS transistor depends on the type of doping ions doped in the substrate 21. The types of MOS transistors include NMOS transistors and PMOS transistors.

[0037] In this embodiment, the gate dielectric layer 22 is a nitrogen-doped oxide layer. The nitrogen-doped oxide layer has a good ion blocking effect, which is beneficial to preventing the doped ions in the polysilicon layer after doping from penetrating into the substrate 21, thereby ensuring that the substrate 21 has good performance.

[0038] The ion doping of the undoped polysilicon layer 230 may include multiple steps or be achieved by at least one process. In the embodiment of the present invention, the undoped polysilicon layer 230 is ion-doped by a thermal doping process. Specifically, taking the limited-source diffusion process as an example, the ion doping of the undoped polysilicon layer 230 includes the following steps:

[0039] Reference Figure 7 , a doping process is carried out to dope the first doping ions in the surface layer region of the undoped polysilicon layer 230 facing away from the gate dielectric layer 22 to form an initial doped region 231.

[0040] In this embodiment, the first doping ions can be doped by a plasma ion implantation process. The type of the first doping ions includes N-type ions or P-type ions. In this article, the type of the first doping ions is taken as an example of P-type ions. The plasma ion implantation process has lower requirements for the target temperature and has a higher doping rate, which is beneficial to avoiding damage to the polysilicon layer caused by the thermal shock formed by heating. In addition, when the plasma ion implantation process performs ion implantation, it does not pass through the analysis electric field screening, and the amount of ions implanted per unit time is relatively large, the production capacity is high, and the initial doped region 231 can have a higher concentration of the first doping ions.

[0041] In this embodiment, the concentration of the first doping ions in the initial doped region 231 is greater than the solid solubility limit of the first doping ions in the polysilicon layer. In this way, it is beneficial to increase the total number of doped ions in the limited-source diffusion, and further increase the concentration of the first doping ions in the doped polysilicon layer.

[0042] Reference Figure 8 , a first heat treatment process is carried out to make the first doping ions located in the initial doped region 231 diffuse downward to form a doped polysilicon layer 23.

[0043] In this embodiment, the first heat treatment process includes rapid thermal processing (RTP), such as a rapid thermal annealing process. The rapid thermal annealing process can heat the entire polysilicon layer to a temperature range of 400°C to 1300°C in a very short time, and has a short annealing time, which is beneficial to reducing the thermal shock received by the doped polysilicon layer 23 and ensuring that the doped polysilicon layer 23 has better structural performance. In addition, compared with furnace annealing, the rapid thermal annealing process has the advantages of less thermal budget, less movement of impurities in silicon, less contamination, and short processing time.

[0044] It should be noted that since the concentration difference is the basic condition for diffusion, after the first heat treatment process is completed, in the direction from the top surface of the doped polysilicon layer 23 towards the bottom surface of the doped polysilicon layer 23, the concentration of the first doping ions actually decreases step by step. In addition, after the first heat treatment process is completed, the actual concentration of the first doping ions at each position in the doped polysilicon layer 23 is also related to the type of the first doping ions (the solubility is different for different doping ion types), the energy of the first heat treatment process, the thickness of the undoped polysilicon layer 230 (refer to Figure 6 ) in the direction perpendicular to the surface of the substrate 21, and the concentration of the first doping ions in the initial doping region 231 (refer to Figure 7 ).

[0045] Specifically, the higher the solubility of the first doping ions, the higher the doping concentration of the first doping ions at each position in the doped polysilicon layer 23; when the energy of the first heat treatment process is relatively high, the first doping ions in the surface layer region can achieve a greater degree of diffusion, and the concentration of the first doping ions in the region of the doped polysilicon layer 23 close to the gate dielectric layer 22 is higher; the thicker the doped polysilicon layer 23 in the direction perpendicular to the surface of the substrate 21, the more the concentration gradient of the first doping ions in the diffusion direction, the more times the first doping ions are diluted in the diffusion direction, and the lower the concentration of the first doping ions in the part of the doped polysilicon layer 23 close to the gate dielectric layer 22; the higher the concentration of the first doping ions in the initial doping region 231, the higher the doping concentration of the first doping ions at each position in the doped polysilicon layer 23.

[0046] Refer to Figure 9 , after the thermal doping process, an ion implantation process is carried out to dope the second doping ions in the preset region 232 of the doped polysilicon layer 23.

[0047] In this embodiment, the second doping ions are the same as the first doping ions, and the second doping ions include boron ions or boron-like ions, and the boron-like ions include BF 2+ or BF2 + or at least one of them.

[0048] In this embodiment, in the direction perpendicular to the surface of the substrate 21, there is a preset distance d between the preset region 232 and the surface of the doped polysilicon layer 23 facing away from the gate dielectric layer 22. Carrying out the ion implantation process after the thermal doping process can make the doping ion concentration at any position in the doped polysilicon layer 23 exceed the solubility limit of the doping ions. When a fixed number of carriers (i.e., the second doping ions) migrate in the direction away from the gate dielectric layer 22 under the action of an electric field, the higher the concentration of the second doping ions in the region close to the gate dielectric layer 22, the thinner the thickness of the depletion layer, and the smaller the capacitance equivalent thickness.

[0049] In addition, since the concentration of the first doping ions decreases step by step in the direction of the doped polysilicon layer 23 facing the gate dielectric layer 22 after doping, doping the second doping ions in the preset region 232 having a spacing from the top surface is beneficial to increasing the difference in the doping ion concentration between the preset region 232 and the regions on both sides of the preset region 232, thereby increasing the diffusion rate of the second doping ions and shortening the process cycle.

[0050] It should be noted that the diffusion rate of the second doping ions is related to the type of the thermal doping process. Compared with the limited-source diffusion process, after the constant-surface-source diffusion process, the doping ion concentration at any position in the doped polysilicon layer 23 is higher. Correspondingly, if the dose injected by the ion implantation process in the preset region 232 is the same, the concentration difference between the preset region and the adjacent regions will be smaller and the diffusion speed will be slower.

[0051] Furthermore, doping the second doping ions in the preset region 232 having a spacing from the top surface is beneficial to shortening the spacing between the preset region 232 and the surface of the doped polysilicon layer 23 close to the gate dielectric layer 22, thereby making it easier for the second doping ions to diffuse to the region of the doped polysilicon layer 23 close to the gate dielectric layer 22, thus increasing the doping ion concentration in the part of the doped polysilicon layer 23 close to the gate dielectric layer 22. As a result, when the number of carrier migrations is constant, the thickness of the depletion layer is thinner, that is, the capacitance equivalent thickness is thinner and the capacitance of the semiconductor structure is larger.

[0052] In this embodiment, the preset spacing d is 1 nm to 10 nm, for example, 3 nm, 5 nm or 7 nm. Since the concentration of the first doping ions decreases step by step in the direction of the doped polysilicon layer 23 facing the gate dielectric layer 22, the larger the preset spacing d, the larger the concentration difference between the doped region and the surrounding regions, the faster the diffusion speed of the second doping ions, and the higher the doping ion concentration on the side of the doped polysilicon layer 23 close to the gate dielectric layer 22. At the same time, in order to avoid causing great damage to the doped polysilicon layer 23 due to the long range of the ion implantation process, it is necessary to limit the maximum value of the preset spacing d to ensure that the doped polysilicon layer 23 has good performance. In this embodiment, referring to Figure 10 , the second doping ions can diffuse by relying on the first heat treatment process in the thermal doping process. Specifically, since the heat absorbed by the doped polysilicon layer 23 during the first heat treatment process takes a certain time to conduct and release, the second doping ions can diffuse by relying on the waste heat of the first heat treatment process. In other embodiments, the second doping ions diffuse by relying on the second heat treatment process performed after the ion implantation process.

[0053] Referring to Figure 11, after performing the ion implantation process, a blocking layer 24 is formed on the surface of the doped polysilicon layer 23 away from the gate dielectric layer 22, and the blocking layer 24 is used to block ion migration.

[0054] Specifically, the blocking layer is used to block the further migration of the first doped ions and the second doped ions, so as to ensure and then control the capacitance equivalent thickness range, and ensure that the semiconductor structure has a relatively reasonable capacitance equivalent thickness.

[0055] In this embodiment, the ion implantation process is performed after the thermal doping process, so that the concentration of the doped ions in the polysilicon layer can exceed the solid solubility limit of the doped ions, which is beneficial to thinning the thickness of the depletion layer, and then reducing the capacitance equivalent thickness; in addition, the second doped ions are doped in the area with a distance from the top surface, which is beneficial to improving the diffusion rate of the second doped ions and the doping ion concentration of the part of the polysilicon layer close to the gate dielectric layer, which is beneficial to making the thickness of the depletion layer thinner when the number of carrier migrations is certain, that is, the capacitance equivalent thickness is thinner and the capacitance of the semiconductor structure is larger.

[0056] Another embodiment of the present invention also provides a method for forming a semiconductor structure. Different from the previous embodiment, in this embodiment, the second doped ions are different from the first doped ions, and the second doped ions rely on the second heat treatment process performed later for diffusion. The following will be combined with Figure 12 and Figure 13 for detailed description. Figure 12 and Figure 13 are schematic diagrams corresponding to the steps of the method for forming a semiconductor structure provided by another embodiment of the present invention. For the same or corresponding parts as the previous embodiment, reference can be made to the corresponding description of the previous embodiment, and details will not be repeated below.

[0057] In this embodiment, the second doped ions are different from the first doped ions, and the weight of the second doped ions is less than the weight of the first doped ions. Specifically, the first doped ions can be heavy ions, and the second doped ions can be light ions. Compared with heavy ion implantation, the damage density generated by light ion implantation on the doped polysilicon layer 33 is lower, and the lower density of damage can be better repaired by the second heat treatment process performed before or after, so as to ensure that the doped polysilicon layer 33 has good performance.

[0058] In this embodiment, after performing the ion implantation process, a second heat treatment process is performed, and the second doped ions rely on the second heat treatment process performed after the ion implantation process for diffusion. The second heat treatment process performed after the ion implantation process can be either specifically for diffusing the second doped ions or for processing or forming other components or film layers.

[0059] Compared with the diffusion using the first heat treatment process performed before ion implantation, the diffusion using the second heat treatment process performed later, on the one hand, does not require controlling the time interval between the thermal doping process and the ion implantation process, so that after the thermal doping process, there is more time for steps such as cleaning and inspection, which is beneficial to improving the process flexibility; on the other hand, the second heat treatment process performed later can be one or more times, which is beneficial to ensuring that the second doped ions are completely diffused, and then making the region of the polysilicon layer 33 close to the gate dielectric layer 32 have doped ions with a higher concentration, resulting in a smaller capacitance equivalent thickness and a larger capacitance of the MOS transistor.

[0060] Specifically, referring to Figure 12 , after the ion implantation process, a metal barrier film 341 is formed on the surface of the doped polysilicon layer 33 away from the gate dielectric layer 32; referring to Figure 13 , the metal barrier film 341 is subjected to a second heat treatment process to form a metal barrier layer 34. Among them, the second doped ions are diffused by the second heat treatment process performed on the metal barrier film 341.

[0061] In this embodiment, the weight of the second doped ions is less than the weight of the first doped ions, which is beneficial to ensuring that the damage caused by the ion implantation process can be effectively repaired by the second heat treatment process; in addition, the second doped ions can be diffused by the second heat treatment process performed later, which is beneficial to ensuring that the second doped ions can be effectively diffused, making the region of the polysilicon layer close to the gate dielectric layer have doped ions with a higher concentration, and then resulting in a smaller capacitance equivalent thickness and a larger capacitance of the MOS transistor.

[0062] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, a gate dielectric layer, and an undoped polysilicon layer stacked in sequence; Performing a thermal doping process to dope a first doping ion in the polysilicon layer; Performing an ion implantation process to dope a second doping ion in a preset region of the polysilicon layer. In the direction perpendicular to the surface of the substrate, there is a preset spacing between the preset region and the surface of the polysilicon layer facing away from the gate dielectric layer. The second doping ion is different from the first doping ion, and the weight of the second doping ion is less than the weight of the first doping ion.

2. The method for forming a semiconductor structure according to claim 1, wherein The preset spacing is 1 nm to 10 nm.

3. The method for forming a semiconductor structure according to claim 1, wherein The second doping ion includes at least one of boron ions, boron fluoride ions, or boron difluoride ions.

4. The method for forming a semiconductor structure according to claim 1, wherein The thermal doping process includes a doping process and a first heat treatment process performed in sequence. The doping process dopes the first doping ion in the surface layer region of the polysilicon layer away from the gate dielectric layer, and the first heat treatment process causes the first doping ion to diffuse in the polysilicon layer.

5. The method for forming a semiconductor structure according to claim 4, wherein, The doping process includes a plasma ion implantation process.

6. The method for forming a semiconductor structure according to claim 5, wherein, The concentration of the first doping ion doped in the surface layer region by the plasma ion implantation process is greater than the solid solubility limit of the first doping ion in the polysilicon layer.

7. The method for forming a semiconductor structure according to claim 4, wherein The first heat treatment process includes a rapid thermal annealing process.

8. The method for forming a semiconductor structure according to claim 1, wherein After performing the ion implantation process, a second heat treatment process is performed, and the second doping ion diffuses by means of the second heat treatment process.

9. The method for forming a semiconductor structure according to claim 1, wherein After performing the ion implantation process, a blocking layer is formed on the surface of the polysilicon layer away from the gate dielectric layer, and the blocking layer is used to block ion migration.

10. The method for forming a semiconductor structure according to claim 1, wherein, It further includes forming a metal blocking film on the surface of the polysilicon layer away from the gate dielectric layer; Performing a second heat treatment process on the metal blocking film to form a metal blocking layer, and the second doping ion diffuses by means of the second heat treatment process.

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