A method for manufacturing a shielded gate trench MOSFET

Abstract

The present invention discloses a method for manufacturing a shielded gate trench MOSFET, comprising forming a plurality of first doped regions of a second conductivity type in an area of ​​an epitaxial layer corresponding to a cell area and forming a second doped region of the second conductivity type in an area of ​​the epitaxial layer corresponding to a shielded gate connection area; forming a third doped region of the second conductivity type in a surface layer of the epitaxial layer, and forming a trench at a position of the epitaxial layer corresponding to the first doped region, the trench extending to a partial area of ​​the first doped region; depositing polysilicon in the trench, and forming a fourth doped region of the first conductivity type in the third doped region. The present invention adopts the first doped region as a shielded gate, replacing the polysilicon shielded gate in the traditional method, and therefore does not require a deep trench process, nor does it require the production of a polysilicon interlayer dielectric in a narrow trench, thereby avoiding the quality instability and reliability problems of the deep trench process and the polysilicon interlayer dielectric process that are difficult to control in terms of process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a shielded gate trench MOSFET. Background Art

[0002] MOSFET chip is a discrete device that belongs to the category of semiconductor power devices. It belongs to the same semiconductor chip field as integrated circuits. Integrated circuits use process methods to integrate thousands of transistors into the same chip, while MOSFET is a single transistor composed of thousands of cells of the same structure in parallel.

[0003] Key dynamic parameters of MOSFETs include parasitic capacitance, switching time, and gate parasitic resistance. Parasitic capacitance includes gate-source parasitic capacitance Cgs, gate-drain parasitic capacitance Cgd, and drain-source parasitic capacitance Cds. From an application perspective, MOSFET parasitic capacitance can be summarized as input capacitance Ciss = Cgs + Cgd, output capacitance Coss = Cds + Cdg, and reverse transfer capacitance Crss = Cdg. Reverse transfer capacitance Crss is also called Miller capacitance. Input capacitance and Miller capacitance play a dominant role in MOSFET switching losses. The larger the chip area, the lower the chip's on-resistance, but the larger the area of ​​the parasitic capacitance, the larger the input capacitance and Miller capacitance. Minimizing the MOSFET's input capacitance and Miller capacitance while maintaining a given on-resistance is the responsibility of chip engineers.

[0004] Existing shielded-gate trench MOSFET manufacturing methods require the creation of deep trenches to reduce the MOSFET's input capacitance and Miller capacitance. Two layers of polysilicon are then fabricated within the trenches. The second layer of polysilicon serves as the MOSFET's polysilicon gate, while the first layer of polysilicon serves as the shield gate, buried beneath the polysilicon gate. The shield gate is not exposed as an independent port, but is connected to the source region (source) within the chip using metal wiring. The shield gate is surrounded by dielectric layers above, on the sides, and below. The dielectric layer above the shield gate and below the polysilicon gate is called the "interpolysilicon dielectric." The interpolysilicon dielectric acts as an isolation layer between the shield gate and the polysilicon gate to prevent leakage between the two.

[0005] In actual processes, it is very difficult to produce deep trenches and polysilicon interlayer dielectrics. They are highly dependent on equipment and processes, and are prone to process fluctuations and reliability issues. Summary of the Invention

[0006] The present invention provides a method for manufacturing a shielded gate trench MOSFET, aiming to solve the existing problem that deep trenches cannot be avoided in order to reduce the input capacitance and Miller capacitance of the MOSFET.

[0007] According to an embodiment of the present application, a method for manufacturing a shielded gate trench MOSFET is provided, characterized in that it includes the following steps: growing an epitaxial layer of a first conductivity type on the surface of a substrate of a first conductivity type; forming a plurality of first doped regions of a second conductivity type in an area of ​​the epitaxial layer corresponding to a cell area and forming a second doped region of the second conductivity type in an area of ​​the epitaxial layer corresponding to a shielding gate connection area; forming a third doped region of the second conductivity type in a surface layer of the epitaxial layer, and forming a trench at a position of the epitaxial layer corresponding to the first doped region, wherein the trench extends to a portion of the first doped region; growing an oxide layer on the sidewalls of the trench and on the top of the epitaxial layer, and activating the first doped region, the second doped region, and the third doped region. dopants in the doped region; depositing polysilicon in the trench, removing the polysilicon outside the trench, and forming a fourth doped region of the first conductivity type in the third doped region; depositing a dielectric layer on the oxide layer and the polysilicon, and forming a first contact hole, a second contact hole and a third contact hole in the dielectric layer, and depositing metal in the first contact hole, the second contact hole and the third contact hole to form a first metal connection, a second metal connection and a third metal connection; the first contact hole passes through the dielectric layer and enters the polysilicon in the trench, the second contact hole passes through the dielectric layer and the oxide layer in sequence to enter the third doped region, and the third contact hole passes through the dielectric layer, the oxide layer and the fourth doped region in sequence to enter the third doped region.

[0008] Preferably, the thickness of the epitaxial layer is 4-15 microns; the ion implantation process for forming the first doping region and the second doping region is multiple ion implantations, the energy and dosage of each ion implantation are different, and the first doping region and the second doping region are distributed in a set area of ​​the epitaxial layer from the surface to a preset depth in a vertical area, and the preset depth is 2 / 4-3 / 4 of the thickness of the epitaxial layer.

[0009] Preferably, during the implantation process, the first doping region and the second doping region are formed by adopting a multiple-time ion implantation process with graded energy and dose.

[0010] Preferably, the depth of the trench is 1-2 microns, and the width of the trench is greater than the width of the first doping region.

[0011] Preferably, the doping concentration of the third doping region is greater than the doping concentrations of the first doping region and the second doping region; the depth of the third doping region is 0.6-1.2 microns, and the lower surface of the third doping region overlaps with the top height of the first doping region and the second doping region.

[0012] Preferably, a high-temperature oxidation process is used, and when an oxide layer is grown on the sidewall of the trench, the dopants in the first doping region, the second doping region and the third doping region are simultaneously activated under the same high-temperature oxidation process; under the same high-temperature oxidation process, the dopants in the first doping region, the second doping region and the third doping region undergo thermal diffusion; the temperature of the high-temperature oxidation process is 950-1100 degrees Celsius, and the process time is 10-60 minutes.

[0013] Preferably, the depth of the fourth doping region is 1 / 9-1 / 3 of the depth of the third doping region.

[0014] Preferably, the first doping region is connected to the second doping region.

[0015] Compared with the prior art, the method for manufacturing a shielded gate trench MOSFET provided by the present invention has the following beneficial effects:

[0016] 1. In shielded-gate trench MOSFETs fabricated using the method of this invention, the first doped region 3.1 is brought into the same potential as the source via the second metal connection 11.2 and the third metal connection 11.3. When a high voltage appears between the drain and source of the MOSFET, the PN junction formed by the first doped region 3.1 and the epitaxial layer 2 at the drain terminal becomes reverse biased, and the depletion layer of the PN junction expands laterally, thereby laterally connecting the depletion layers of adjacent PN junctions. Based on the principle of charge balance, this increases the longitudinal breakdown voltage, thereby increasing the drain-source breakdown voltage of the MOSFET or, while achieving a given breakdown voltage, achieving a lower on-resistance per unit area. Furthermore, in MOSFETs fabricated using the present invention, the first doped region 3.1 (connected to the source) is primarily located below the polysilicon gate, thereby reducing the area of ​​the MOS capacitor between the polysilicon gate and the drain terminal, thereby reducing the Miller capacitance.

[0017] 2. The present invention adopts the first doped region 3.1 as the shield gate of the MOSFET, replacing the polysilicon shield gate in the traditional method. The first doped region 3.1 and the epitaxial layer 2 at the drain end form a large-area PN junction, which increases the drain-source parasitic capacitance Cds. When the MOSFET is subjected to a reverse pulse signal, it has a greater energy absorption capacity than the traditional shielded gate MOSFET, thereby improving the avalanche current and surge capability of the device.

[0018] 3. The present invention uses the first doped region 3.1 as the shield gate of the MOSFET, replacing the polysilicon shield gate in the traditional method. Therefore, the present invention does not need to adopt a deep trench process or to produce a polysilicon interlayer dielectric in a narrow trench, thereby avoiding the difficult-to-control deep trench process and the quality instability and reliability problems of the polysilicon interlayer dielectric process.

[0019] 4. The present invention first forms a shielding gate and a body region, and then forms a groove: in the cell region, a groove etching process is used to divide the body region into individual cells (i.e., the region between adjacent grooves), and a groove etching process is used to etch away the first doped region 3.1 on the surface of the cell region, and it is always ensured that the groove 5 of the cell region completely covers the first doped region 3.1 (W2>W1), thereby achieving the continuity of the conductive channel and avoiding the first doped region 3.1 and the third doped region 4 of the cell region being connected as one, resulting in the MOSFET being unable to turn on; in the shielding gate connection region, the second doped region 3.2 and the third doped region 4 are connected as one and are led out from the surface through the second contact hole 9.2 and the second metal connection 11.2, while the first doped region 3.1 and the second doped region 3.2 are integrated inside the chip, thereby simply and cleverly achieving the electrical connection of the shielding gate.

[0020] 5. The first doping region 3.1 and the second doping region 3.2 formed in the present invention are formed by a multiple injection process with varying energy and dosage, that is, the doping concentration decreases from the surface to the preset depth. As is well known, when the MOSFET is subjected to reverse pressure, the potential increases from the surface to the preset depth. The present invention uses the first doping region 3.1 and the second doping region 3.2 with decreasing doping concentration from the surface to the preset depth, which can better achieve charge balance at various depth positions, thereby improving the breakdown voltage of the MOSFET.

[0021] 6. The present invention first forms the shield gate and the body region, and then forms the trench and the polysilicon gate, and utilizes the thermal budget of high-temperature oxidation to grow the gate oxide layer to achieve activation and trace thermal diffusion of the shield gate and body region dopants. The entire process does not require an additional high-temperature annealing process, thereby minimizing the thermal budget, that is, minimizing the diffusion of dopants in the substrate into the epitaxial layer, thereby improving the breakdown voltage of the MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 This is a flow chart of a method for manufacturing a shielded gate trench MOSFET provided by the first embodiment of the present invention.

[0024] Figure 2 It is a structural schematic diagram of growing an epitaxial layer on a substrate surface and forming a first doping region and a second doping region.

[0025] Figure 3 It is a schematic structural diagram of forming the third doping region and the trench.

[0026] Figure 4 It is a schematic diagram of the structure of growing oxide layer and depositing polysilicon.

[0027] Figure 5 It is a schematic diagram of the structure for forming the fourth doping region.

[0028] Figure 6 It is a schematic diagram of the structure for forming a contact hole.

[0029] Figure 7 It is a schematic diagram of the structure for forming metal wiring.

[0030] Figure 8 It is a top view of the chip structure after the contact holes are formed.

[0031] Description of labels:

[0032] 1. Substrate; 2. Epitaxial layer; 3.1. First doped region; 3.2. Second doped region; 4. Third doped region; 5. Trench; 6. Oxide layer; 7. Polysilicon; 8. Fourth doped region; 9.1. First contact hole; 9.2. Second contact hole; 9.3. Third contact hole; 10. Dielectric layer; 11.1. First metal connection; 11.2. Second metal connection; 11.3. Third metal connection. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0034] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0035] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0036] Please combine Figure 1 The first embodiment of the present invention discloses a method for manufacturing a shielded gate trench MOSFET, which specifically includes the following steps:

[0037] Step S1: growing an epitaxial layer 2 of the first conductivity type on a surface of a substrate 1 of the first conductivity type.

[0038] Step S2: forming a plurality of first doping regions 3.1 of the second conductivity type in the region of the epitaxial layer 2 corresponding to the cell region and forming a second doping region 3.2 of the second conductivity type in the region of the epitaxial layer 2 corresponding to the shielding gate connection region. Figure 2 .

[0039] Step S3: forming a third doping region 4 of the second conductivity type in the surface layer of the epitaxial layer 2, and forming a trench 5 at a position corresponding to the first doping region 3.1 in the epitaxial layer 2, the trench 5 extending to a portion of the first doping region 3.1. Figure 3 .

[0040] Step S4: Grow an oxide layer 6 on the sidewalls of the trench 5 and the top of the epitaxial layer 2, and activate the dopants in the first doping region 3.1, the second doping region 3.2 and the third doping region 4. Figure 4 .

[0041] Step S5: depositing polysilicon 7 in the trench 5, removing the polysilicon 7 outside the trench 5, and forming a fourth doping region 8 of the first conductivity type in the third doping region 4. Figure 4-Figure 5 .

[0042] Step S6: Deposit a dielectric layer 10 on the oxide layer 6 and the polysilicon 7, and form a first contact hole 9.1, a second contact hole 9.2, and a third contact hole 9.3 in the dielectric layer 10, and deposit metal in the first contact hole 9.1, the second contact hole 9.2, and the third contact hole 9.3 to form a first metal connection 11.1, a second metal connection 11.2, and a third metal connection 11.3. Figure 6-Figure 7 .

[0043] The first contact hole 9.1 passes through the dielectric layer 10 and enters the polysilicon 7 in the trench 5, the second contact hole 9.2 passes through the dielectric layer 10 and the oxide layer 6 in sequence and enters the third doped region 4, and the third contact hole 9.3 passes through the dielectric layer 10, the oxide layer 6, and the fourth doped region 8 in sequence and enters the third doped region 4.

[0044] It can be understood that in step S2, photolithography and ion implantation processes are used to form the first doped region 3.1 and the second doped region 3.2. The first doped region 3.1 is located in the cell region of the MOSFET, and the second doped region 3.2 is located in the shield gate connection region of the MOSFET. There are multiple first doped regions 3.1. In this embodiment, there are two first doped regions 3.1, and the first doped regions 3.1 and the second doped regions 3.2 have the same conductivity type. For example, when the MOSFET is an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type, and vice versa.

[0045] It will be understood that in step S2, the first doping region 3.1 and the second doping region 3.2 are formed by multiple ion implantation processes with graded energy and dose. Specifically, the number of ion implantations is two or more, and the energy and dose of each ion implantation are different. When the implantation energy is high, the implantation dose is low, and when the implantation energy is low, the implantation dose is high. That is, the first doping region 3.1 and the second doping region 3.2 are formed by multiple ion implantation processes with graded energy and dose.

[0046] It is understood that in step S2, the thickness of the epitaxial layer 2 is 4-15 microns, and the first doped region 3.1 and the second doped region 3.2 are distributed in a predetermined region of the epitaxial layer 2 from the surface to a predetermined depth, wherein the predetermined depth is 2 / 4 to 3 / 4 of the thickness of the epitaxial layer. Optionally, as an embodiment, the tops of the first doped region 3.1 and the second doped region 3.2 are 0.5-1 microns from the upper surface of the epitaxial layer 2.

[0047] It is understood that in step S3, the doping concentration of the third doping region 4 is greater than the doping concentrations of the first doping region 3.1 and the second doping region 3.2. The depth of the third doping region 4 is 0.6-1.2 microns, and the bottom surface of the third doping region 4 overlaps with the top height of the first doping region 3.1 and the second doping region 3.2.

[0048] It can be understood that in step S3, an ion implantation process is used to form a third doping region 4 of the second conductivity type in the surface layer of the epitaxial layer 2, so that the third doping region 4 covers part of the first doping region 3.1 and part of the second doping region 3.2, and then a trench 5 is formed in the region of the epitaxial layer 2. The position and number of the trench 5 correspond to the first doping region 3.1 one by one, and the trench 5 passes through the third doping region 4 and overlaps with a part of the first doping region 3.1, forming a superimposed shape. Specifically, the depth of the trench 5 is 1-2 microns, and the width of the trench 5 (such as Figure 3 The size W2 shown in FIG) is larger than the width of the first doping region 3.1 (as shown in FIG). Figure 3The third doped region 4 is the body region of the MOSFET.

[0049] It can be understood that in step S4, a high-temperature oxidation process is adopted, the temperature of the high-temperature oxidation process is 950-1100 degrees Celsius, and the process time is 10-60 minutes. When the oxide layer 6 is grown on the sidewall of the trench 5, the dopants in the first doping region 3.1, the second doping region 3.2 and the third doping region 4 are synchronously activated under the same high-temperature oxidation process. At the same time, under the same high-temperature oxidation process, the dopants in the first doping region 3.1, the second doping region 3.2 and the third doping region 4 undergo thermal diffusion, and the width of the first doping region 3.1 after thermal diffusion is still smaller than the width of the trench 5.

[0050] It can be understood that activating the dopants in the first doping region 3.1, the second doping region 3.2 and the third doping region 4 causes the dopants in the first doping region 3.1, the second doping region 3.2 and the third doping region 4 to exhibit N-type or P-type electrical characteristics, while before activation, these dopants have no electrical properties.

[0051] It can be understood that in step S5 , the fourth doped region 8 is the source region of the MOSFET.

[0052] It will be appreciated that in step S6, the number and location of first contact holes 9.1 correspond one-to-one with the first doped regions 3.1, and each first contact hole 9.1 penetrates the dielectric layer 10 and enters the polysilicon 7 within the trench 5, and is then filled with metal to form a first metal connection 11.1. Second contact holes 9.2 are opened corresponding to the second doped regions 3.2, penetrate the dielectric layer 10 and the oxide layer 6 and enter the third doped region 4, and are then filled with metal to form a second metal connection 11.2. Third contact holes 9.3 sequentially penetrate the dielectric layer 10, the oxide layer 6, and the fourth doped region 8 and enter the third doped region 4, and are then filled with metal to form a third metal connection 11.3.

[0053] It can be understood that in step S6, the second metal connection line 11.2 and the third metal connection line 11.3 are interconnected by metal, that is, the shield gate and the source are interconnected.

[0054] At this point, the main structure of the MOSFET chip has been completed. The subsequent processes for the passivation layer and backside processing of the MOSFET are common practices for those skilled in the art and will not be described in detail here. Among them, the backside of the MOSFET, namely the substrate 1, is connected to the drain of the MOSFET. The substrate 1 and the epitaxial layer 2 form the drain terminal of the MOSFET.

[0055] Please combine Figure 7 and Figure 8In the MOSFET cell region (i.e., the area of ​​the first doped region 3.1), the fourth doped region 8 serves as the MOSFET's source region, and the third doped region 4 serves as the MOSFET's body region. Adjacent trenches 5 contain the source region, the body region, and a third contact hole 9.3. The third contact hole 9.3 penetrates the source region into the body region, ensuring that the source and body regions have the same potential. Each trench 5 in the cell region is filled with polysilicon 7, serving as the polysilicon gate of the MOSFET. The bottom of each trench 5 is covered by a first doped region 3.1, which serves as the shield gate of the MOSFET. An oxide layer 6 separates the polysilicon 7 (polysilicon gate) and the first doped region 3.1 (shield gate).

[0056] See Figure 8 It can be seen that, when viewed from above, the second doping region 3.2 is connected to the first doping region 3.1, that is, the second doping region 3.2 and the first doping region 3.1 are integrated. The first doping region 3.1 of the cell region cannot be led out by wires because it is covered under the polysilicon 7 (polysilicon gate), and can only be led out by punching holes in the area of ​​the second doping region 3.2, that is, the second doping region 3.2 serves as the shielding gate connection area of ​​the MOSFET. In the shielding gate connection area of ​​the MOSFET, the second doping region 3.2 is led out through the second contact hole 9.2 in the third doping region 4 on its surface. Because the second doping region 3.2 and the third doping region 4 are the same type of doping regions (second conductive type), the two have the same potential. The second contact hole 9.2 located in the third doping region 4 realizes the electrical signal lead-out of the second doping region 3.2, that is, the electrical signal lead-out of the first doping region 3.1, i.e., the shielding gate. Figure 8 In the figure, the two dotted boxes are grooves 5.

[0057] In the manufacturing method of the present invention, the mechanism by which the first doped region 3.1 achieves the shielded gate effect is as follows: the first doped region 3.1 is brought to the same potential as the source via the second metal connection 11.2 and the third metal connection 11.3. When a high voltage appears between the drain and source of the MOSFET, the PN junction formed by the first doped region 3.1 and the epitaxial layer 2 at the drain end is reverse biased, and the depletion layer of the PN junction expands laterally, so that the depletion layers of adjacent PN junctions are laterally connected.

[0058] In an embodiment of the present invention, there are multiple first doped regions 3.1 (two are shown in the figure), and the multiple first doped regions 3.1 are arranged at equal intervals. The first doped region 3.1 corresponds to the cell region of the MOSFET, the second doped region 3.2 corresponds to the shield gate connection region of the MOSFET, the oxide layer 6 is the gate oxide layer of the MOSFET, the third doped region 4 is the body region of the MOSFET, the polysilicon 7 retained in the trench 5 is the polysilicon gate of the MOSFET, the fourth doped region 8 is the source region of the MOSFET, the substrate 1 is connected to the drain of the MOSFET, and the substrate 1 and the epitaxial layer 2 are the drain terminal of the MOSFET.

[0059] Compared with the prior art, the method for manufacturing a shielded gate trench MOSFET provided by the present invention has the following beneficial effects:

[0060] 1. In shielded-gate trench MOSFETs fabricated using the method of this invention, the first doped region 3.1 is brought into the same potential as the source via the second metal connection 11.2 and the third metal connection 11.3. When a high voltage appears between the drain and source of the MOSFET, the PN junction formed by the first doped region 3.1 and the epitaxial layer 2 at the drain terminal becomes reverse biased, and the depletion layer of the PN junction expands laterally, thereby laterally connecting the depletion layers of adjacent PN junctions. Based on the principle of charge balance, this increases the longitudinal breakdown voltage, thereby increasing the drain-source breakdown voltage of the MOSFET or, while achieving a given breakdown voltage, achieving a lower on-resistance per unit area. Furthermore, in MOSFETs fabricated using the present invention, the first doped region 3.1 (connected to the source) is primarily located below the polysilicon gate, thereby reducing the area of ​​the MOS capacitor between the polysilicon gate and the drain terminal, thereby reducing the Miller capacitance.

[0061] 2. The present invention adopts the first doped region 3.1 as the shield gate of the MOSFET, replacing the polysilicon shield gate in the traditional method. The first doped region 3.1 and the epitaxial layer 2 at the drain end form a large-area PN junction, which increases the drain-source parasitic capacitance Cds. When the MOSFET is subjected to a reverse pulse signal, it has a greater energy absorption capacity than the traditional shielded gate MOSFET, thereby improving the avalanche current and surge capability of the device.

[0062] 3. The present invention uses the first doped region 3.1 as the shield gate of the MOSFET, replacing the polysilicon shield gate in the traditional method. Therefore, the present invention does not need to adopt a deep trench process, nor does it need to produce a polysilicon interlayer dielectric in a narrow trench, thereby avoiding the quality instability and reliability problems of the deep trench process and the polysilicon interlayer dielectric process that are difficult to control in terms of process.

[0063] 4. The present invention first forms a shielding gate and a body region, and then forms a groove: in the cell region, a groove etching process is used to divide the body region into individual cells (i.e., the region between adjacent grooves), and a groove etching process is used to etch away the first doped region 3.1 on the surface of the cell region, and it is always ensured that the groove 5 of the cell region completely covers the first doped region 3.1 (W2>W1), thereby achieving the continuity of the conductive channel and avoiding the first doped region 3.1 and the third doped region 4 of the cell region being connected as one, resulting in the MOSFET being unable to turn on; in the shielding gate connection region, the second doped region 3.2 and the third doped region 4 are connected as one and are led out from the surface through the second contact hole 9.2 and the second metal connection 11.2, while the first doped region 3.1 and the second doped region 3.2 are integrated inside the chip, thereby simply and cleverly achieving the electrical connection of the shielding gate.

[0064] 5. The first doping region 3.1 and the second doping region 3.2 formed in the present invention are formed by a multiple injection process with varying energy and dosage, that is, the doping concentration decreases from the surface to the preset depth. As is well known, when the MOSFET is subjected to reverse pressure, the potential increases from the surface to the preset depth. The present invention uses the first doping region 3.1 and the second doping region 3.2 with decreasing doping concentration from the surface to the preset depth, which can better achieve charge balance at various depth positions, thereby improving the breakdown voltage of the MOSFET.

[0065] 6. The present invention first forms the shield gate and the body region, and then forms the trench and the polysilicon gate, and utilizes the thermal budget of high-temperature oxidation to grow the gate oxide layer to achieve activation and trace thermal diffusion of the shield gate and body region dopants. The entire process does not require an additional high-temperature annealing process, thereby minimizing the thermal budget, that is, minimizing the diffusion of dopants in the substrate into the epitaxial layer, thereby improving the breakdown voltage of the MOSFET.

[0066] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A method for manufacturing a shielded gate trench MOSFET, characterized in that: The following steps are involved: growing an epitaxial layer of the first conductivity type on a surface of a substrate of the first conductivity type, wherein the epitaxial layer has a thickness of 4-15 microns; A plurality of first doped regions of a second conductivity type are formed in regions of the epitaxial layer corresponding to the cell regions, and a second doped region of the second conductivity type is formed in regions of the epitaxial layer corresponding to the shield gate connection region. The ion implantation process for forming the first doped regions and the second doped regions is multiple ion implantations, with each ion implantation having different energy and dose. The first doped regions and the second doped regions are distributed in a vertical region from the surface to a preset depth in a set region of the epitaxial layer. The preset depth is 2 / 4 to 3 / 4 of the thickness of the epitaxial layer. During the implantation process, the first doped regions and the second doped regions are formed using multiple ion implantations with graded energy and dose. forming a third doped region of the second conductivity type in a surface layer of the epitaxial layer, and forming a trench at a position of the epitaxial layer corresponding to the first doped region, wherein the trench extends to a portion of the first doped region, has a depth of 1-2 microns, and has a width greater than that of the first doped region; growing an oxide layer on the trench sidewalls and the top of the epitaxial layer, and activating dopants in the first doping region, the second doping region, and the third doping region; Depositing polysilicon in the trench and covering the oxide layer, removing the polysilicon outside the trench, and forming a fourth doped region of the first conductivity type in the third doped region, wherein the fourth doped region is located in the cell region; Depositing a dielectric layer on the oxide layer and the polysilicon, forming a first contact hole, a second contact hole, and a third contact hole in the dielectric layer, and depositing metal in the first contact hole, the second contact hole, and the third contact hole to form a first metal connection line, a second metal connection line, and a third metal connection line; The first contact hole passes through the dielectric layer and enters the polysilicon in the trench, the second contact hole passes through the dielectric layer and the oxide layer in sequence and enters the third doped region, and the third contact hole passes through the dielectric layer, the oxide layer and the fourth doped region in sequence and enters the third doped region.

2. The method for manufacturing a shielded gate trench MOSFET according to claim 1, wherein: The doping concentration of the third doping region is greater than the doping concentration of the first doping region and the second doping region; The depth of the third doping region is 0.6-1.2 microns, and the bottom surface of the third doping region overlaps with the top heights of the first doping region and the second doping region.

3. The method for manufacturing a shielded gate trench MOSFET according to claim 1, wherein: A high temperature oxidation process is used to simultaneously activate dopants in the first doping region, the second doping region, and the third doping region when growing an oxide layer on the sidewall of the trench in the same high temperature oxidation process; Under the same high-temperature oxidation process, the dopants in the first doping region, the second doping region, and the third doping region undergo thermal diffusion; The temperature of the high-temperature oxidation process is 950-1100 degrees Celsius, and the process time is 10-60 minutes.

4. The method for manufacturing a shielded gate trench MOSFET according to claim 1, wherein: The depth of the fourth doping region is 1 / 9-1 / 3 of the depth of the third doping region.

5. The method for manufacturing a shielded gate trench MOSFET according to claim 1, wherein: The first doping region is connected to the second doping region.

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