Configurable computer memory architecture

Abstract

A configurable computer storage architecture includes a storage device that includes an array of storage cells, word lines, column select lines, and data lines (including local and non-local data lines). One or more of the lines includes a first segment and a second segment separated by a gap that can prevent the transmission of an electrical signal from the first segment to the second segment. A signal can be transmitted between the two segments or prevented from being transmitted between the two segments, depending on how the computer storage architecture is configured. In this way, the storage device can be adapted for different uses.

Description

Background Art

[0001] Three-dimensional (3D) dynamic random access memory (DRAM) refers to a memory architecture in which DRAM die are stacked with logic die using, for example, hybrid bonding technology and electrically connected to the logic die. 3D-DRAM can reduce memory access latency and increase memory access bandwidth. 3D-DRAM has good sequential bandwidth, but poor random and fine-grained access due to a lack of bank-level parallelism and high input / output (IO) latency (the time spent waiting for IO operations to complete).

[0002] Configuring 3D-DRAM for different use cases enables those use cases to be executed more efficiently. However, some manufacturers are reluctant to produce 3D-DRAM configured for uncommon use cases because the market for those 3D-DRAMs is small. On the other hand, manufacturers that produce 3D-DRAM configured for less common use cases charge more for those 3D-DRAMs because they are not produced in large quantities. Summary of the Invention

[0003] A solution to the above problem is provided according to an embodiment of the present invention. An embodiment of the present invention relates to a configurable computer storage architecture.

[0004] In one embodiment, a configurable computer memory architecture includes a memory device comprising a memory cell array, word lines, column select lines, and data lines (including local and non-local data lines). The memory device may be a dynamic random access memory (DRAM). One or more of these lines includes a first segment and a second segment separated by a gap, wherein the gap prevents an electrical signal from passing from the first segment to the second segment. Depending on how the computer memory architecture is configured, signals may be passed or blocked between the two segments.

[0005] In an embodiment, a configurable computer memory architecture includes: a first chiplet, the first chiplet including the memory device described above; and a second chiplet bonded (e.g., hybrid bonded) to the first chiplet. Therefore, in an embodiment, this computer memory architecture can be referred to as a three-dimensional DRAM (3D-DRAM). The second chiplet may include circuitry that can be used to configure the computer memory architecture. For example, the circuitry on the second chiplet can be used to connect two segments of a line separated by a gap as described above, or to read data from or into a segment of a data line. In this way, the memory device can be adapted for different use cases.

[0006] Thus, a standard version of the first chiplet and a standard version of the second chiplet can be manufactured, and the version of the first chiplet and the version of the second chiplet can be bonded to each other (e.g., hybrid bonding), and can then be configured according to how the computer memory architecture is used, for example, by using circuitry on the second chiplet to connect selected segments on the first chiplet. Because the first chiplet and the second chiplet are standardized, they can be mass-produced, reducing manufacturing costs. Additionally, because the computer memory architecture can be configured according to its intended use, it is more suitable for the functions to be performed, and therefore can perform those functions more quickly and more efficiently. For example, latency is reduced, bandwidth is increased, and utilization is improved. Generally speaking, computer system memory (e.g., 3D-DRAM) according to the present invention is flexible and can meet different needs and different use cases.

[0007] These and other objects and advantages of the various embodiments of the present invention will become apparent to those skilled in the art after reading the following detailed description of the embodiments that are illustrated in the various drawing figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are incorporated in and constitute a part of this specification, in which like elements are designated by like numerals, and together with the detailed description, serve to explain the principles of the present disclosure.

[0009] Figure 1 A block diagram illustrating a configurable computer storage architecture in accordance with an embodiment of the present invention.

[0010] Figure 2 A block diagram illustrating memory devices on a first die of a configurable computer memory architecture in accordance with an embodiment of the present invention.

[0011] Figure 3 An example of two lines each divided into two segments of the memory device according to the embodiment of the present invention is shown.

[0012] Figure 4 An example of a line dividing a storage device into a first section and a second section in an embodiment of the present invention is shown.

[0013] Figure 5 Also shown is an embodiment according to the present invention. Figure 3 and Figure 4 .

[0014] Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D and Figure 6E Examples of different configurations of computer memory architectures in accordance with embodiments of the present invention are shown.

[0015] Figure 7 Included are two timelines illustrating signal sequences for a conventional three-dimensional dynamic random access memory (3D-DRAM) architecture relative to a 3D-DRAM configured as a pseudo-bank architecture in accordance with an embodiment of the present invention.

[0016] Figure 8 is a flowchart of an example of a method for configuring a computer storage architecture in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] Reference will now be made in detail to various embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although described in conjunction with these embodiments, it should be understood that they are not intended to limit the present disclosure to these embodiments. On the contrary, the present disclosure is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the present disclosure as defined by the appended claims. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it should be understood that the present disclosure can be practiced without these specific details. In other cases, well-known methods, processes, components and circuits will not be described in detail to avoid unnecessarily confusing various aspects of the present disclosure.

[0018] The illustrations are not necessarily drawn to scale and only illustrate portions of the depicted devices and structures, as well as the individual layers that form those structures. To simplify discussion and illustration, only one or two devices or structures may be described, but more than one or two devices or structures may actually be present or formed. Additionally, although certain elements, components, and layers have been discussed, embodiments of the present invention are not limited to those elements, components, and layers. For example, other elements, components, layers, etc. may also be present in addition to those discussed.

[0019] Figure 1 FIG. 1 is a block diagram of a configurable computer storage architecture 100 according to an embodiment of the present invention. The computer storage architecture 100 includes a first chip 120, which is specifically combined with Figure 2 Further description. The computer storage architecture 100 also includes a second chip 160, which will be specifically combined with Figures 6A-6E The first chip die 120 and the second chip die 160 are bonded to each other via a bonding layer 130. In an embodiment, the computer memory architecture of the present invention may be referred to as a three-dimensional dynamic random access memory (3D-DRAM).

[0020] In one embodiment, the bonding layer 130 is a hybrid bonding layer. Generally speaking, hybrid bonding describes a type of bonding that combines metal interconnects with other forms of bonding (e.g., silicon fusion bonding). That is, hybrid bonding can include, for example, wiring that allows communication between layers bonded by hybrid bonding.

[0021] Figure 2 In an embodiment according to the present invention, Figure 1 FIG. 1 is a block diagram of a memory device 200 provided or implemented on a first chip die 120. The memory device 200 may be a DRAM. Figure 2 Only example portions of the memory device 200, example components of the memory device, and example numbering of those components are shown; however, the invention is not limited to these embodiments.

[0022] Generally speaking, memory device 200 includes a memory cell array or memory matrix, word lines, column select lines, and data lines (including local and non-local data lines). More specifically, in an embodiment, memory device 200 includes a certain number of subarrays including subarray 0 and subarray N, where N is an integer. Any specific number of subarrays may be provided between subarray 0 and subarray N.

[0023] In an embodiment, each of the sub-arrays 0-N includes Figure 2 2020; a plurality of sense amplifiers coupled to the MAT 2020, illustrated as sense amplifiers (SA) 204; a plurality of column selectors, illustrated as column selectors (CS) 205; a plurality of global or master word lines (GWL / MWL), illustrated as GWL / MWL 206 and 207; a plurality of local word lines, illustrated as local word lines (LWL) 208; a plurality of local word line decoders, illustrated as LWL decoder (LWD) 210; and a plurality of local data lines, illustrated as local data lines (LDL) 212, 213, 214, and 215. The GWL / MWL are coupled to a global row decoder (GRD) 216, which can receive a row address (RA) 217.

[0024] Subarrays 0-N are traversed by a plurality of global or master data lines (GDL / MDL), illustrated as GDL / MDL 218 , 219 , 220 , and 221 ; and by a plurality of column select lines (CSL), illustrated as CSL 222 , 223 , 224 , and 225 .

[0025] The memory device 200 also includes a global column decoder (GCD) 230 coupled to the CSL and capable of receiving a column address (CA) 232, a global SA shown as a global SA (GSA) 234, and a burst selector (BS) 236 coupled to the GDL / MDLS and coupled to a data bus (DB) 238.

[0026] In an embodiment according to the present invention, one or more of the word lines, column select lines, and data lines of the memory device 200 may be separated into a first segment and a second segment by a gap or opening. The gap may prevent an electrical signal from being transmitted from the first segment to the second segment. However, as will be further described below, whether an electrical signal can be transmitted between two such segments (e.g., from one segment to another segment) or is prevented from being transmitted between two such segments depends on the computer memory architecture 100 ( Figure 1 ) is configured.

[0027] exist Figure 2 In the example of FIG, gap 241a is located on GWL / MWL 206, gap 241b is located on GWL / MWL 207, gap 242a is located on LDL 212, gap 242b is located on LDL 213, gap 243a is located on LDL 214, gap 243b is located on LDL 215, gap 244a is located on CSL 222, gap 244b is located on CSL 223, gap 245a is located on CSL 224, gap 245b is located on CSL 225, gap 246a is located on GDL / MDL 218, gap 246b is located on GDL / MDL 219, gap 247a is located on GDL / MDL 220, and gap 247b is located on GDL / MDL 221. In the following combination Figure 3 and Figure 4 Provide additional information.

[0028] Continue to refer Figure 2 In various embodiments, a subarray, such as subarray 0, may include or exclude all of gaps 241a, 241b, 242a, 242b, 243a, and 243b (241-243). In various embodiments, other subarrays, such as subarray N, may include or exclude gaps such as gaps 241-243. In other words, in embodiments according to the present invention, a particular subarray may include none, some, or all of gaps 241-243, and not all subarrays may be configured in the same manner with respect to the presence or location of such gaps.

[0029] Additionally, in different embodiments, gaps like gaps 244a, 244b, 245a, 245b, 246a, 246b, 247a, and 247b (244-247) may or may not be spaced apart. Figure 2 In other words, in different embodiments, the gap may not be located on any CLS, may be located on some or all of the CLSs in the CSL, and the gap may not be located on any GDL / MDL, may be located on some or all of the GDL / MDLs.

[0030] Therefore, the storage device according to the embodiment of the present invention may only include Figure 2 A portion of the gap shown in the example, or may include Figure 2 All of the gaps shown in the example.

[0031] Each of the gaps 241-243 and 244-247 divides a corresponding line (eg, a word line, a column select line, or a data line) of the memory device 200 into a first segment and a second segment. Figures 6A-6E Except as further described in the examples of FIG, a first segment and a second segment of a line separated by a gap in the memory device 200 are not connected to each other. As will be described in those examples, how a signal is transmitted or blocked from transmitting between the two segments depends on the memory architecture 100 ( Figure 1 ) is configured.

[0032] Figure 3 A storage device 200 ( Figure 2 ) is a top view of an example 300 of two parallel lines 302 and 304 each divided into two segments. Figure 2 , first line 302 and second line 304 may be GWL / MWL 206 and 207, LDL 212 and 213 and / or 214 and 215, GDL / MDL 218 and 219 and / or 220 and 221 and / or CSL 222 and 223 and / or 224 and 225. Gap 303 divides first line 302 into first segment 312 and second segment 313, while another gap 305 divides second line 304 into first segment 314 and second segment 315. Gaps 303 and 305 are examples of gaps 241-247.

[0033] exist Figure 3 In example 300, a first pin (or terminal or contact) 321 is connected to an end of segment 312, a second pin 322 is connected to an end of segment 313, a third pin 323 is connected to an end of segment 314, and a fourth pin 324 is connected to an end of segment 315. Pins 321-324 may be connected to the end of the memory device 200 ( Figure 2 ) is accessed, thereby allowing connections to be made to the respective ends of segments 312-315. As will be described further below, it is possible to Figure 1 ) is appropriately configured to make an electrical connection between pins 321 and 322 and / or an electrical connection between pins 323 and 324.

[0034] Figure 4 The storage device 200 ( Figure 2) is divided into a first segment 412 and a second segment 413. The line 402 can be a line described above (e.g., Figure 2 Gap 403 divides line 402 into a first segment 412 and a second segment 413. Gap 403 is an example of gaps 241-247.

[0035] exist Figure 4 In the example 400, the first pin (or contact) 421 is connected to the end of the segment 412, and the second pin 422 is connected to the end of the segment 413. The pins 421 and 422 may be connected to the end of the memory device 200 ( Figure 2 ) is accessed, thereby allowing connections to be made to the respective ends of segments 412 and 413. As will be described further below, it is possible to Figure 1 ) to make an electrical connection between pins 421 and 422.

[0036] Figure 5 FIG. 1 shows an embodiment of the present invention. Figure 3 and Figure 4 Side view (relative to top view) of Examples 300 and 400. Side view from Figure 3 and Figure 4 In an embodiment, the first connector 501 is connected to the first pin 321 or 421 of the examples 300 and 400, and the second connector 502 is connected to the second pin 322 or 422 of the examples 300 and 400. The first connector 501 and the second connector 502 are connected from the second chip die 160 ( Figure 1 ) extends into and through the hybrid bonding layer 130. In a similar manner, a third connector (not shown) can also be connected to the third pin 323 of the example 300, and a fourth connector (not shown) can be connected to the fourth pin 324 of the example 300. As mentioned above, the pins 321 / 322 / 421 / 422 are accessible from outside the first chip die 120. Figure 5 In the example shown, pins 321 / 322 / 421 / 422 are located below the surface of first die 120 and connectors 501 and 502 extend into first die 120. Alternatively, pins 321 / 322 / 421 / 422 can be located on the surface of first die 120 or be open (exposed) to the surface.

[0037] Figures 6A-6E Examples of different configurations of the memory architecture 100 according to embodiments of the present invention are shown. Figures 6A-6D The examples show different ways of connecting the above segments by bridging the gaps between them, and Figure 6EShows an example of how the pins on the line segment can be used to read data out or read data in. Figures 6A-6E , pins 622 and 644 correspond to, for example, Figure 3 and Figure 4 Pins 321 / 322 / 421 / 422.

[0038] exist Figure 6A In the example of FIG. 1 , the second chip 160 includes a multiplexer (MUX) 604 coupled to the first connector 501 and to the second connector 502 via the hybrid bonding layer 130 . The multiplexer 604 is operable to connect the first connector 501 and the second connector 502 under the control of an input signal 606 . That is, in this example, depending on the value of the input signal 606 , the first connector 501 can be connected to the second connector 502 , or the first connector can be disconnected from the second connector 502 . In one embodiment, the second chip 160 includes a decoder (DEC) 602 coupled to the multiplexer 604 , and the multiplexer is also operable to connect the decoder and the second connector 502 and to select between an input from the first connector 501 and an input from the decoder under the control of the input signal 606 . Therefore, in this example, depending on the value of the input signal 606 , either a signal from the first connector 501 or a signal from the decoder 602 can be selected and provided to the second connector 502 .

[0039] exist Figure 6B In the example of FIG, the second chip die 160 includes a flip-flop (or register) 612 coupled to the first connector 501 and to the second connector 502 via the hybrid bonding layer 130. The flip-flop 612 is operable to connect the first connector 501 and the second connector 502 under the control of an input signal 616. That is, in this example, depending on the value of the input signal 616, the first connector 501 can be connected to the second connector 502, or the first connector can be disconnected from the second connector.

[0040] exist Figure 6C In the example shown, the first connector 501 is connected to the second connector 502 through the connector 622. In the illustrated example, the connector 622 is in the hybrid bonding layer 130; however, the connector 622 may instead be located in the second die 160.

[0041] exist Figure 6DIn the example of FIG, the second chip die 160 includes a switch 632 coupled to the first connector 501 and to the second connector 502 through the hybrid bonding layer 130. The switch 632 is operable to connect the first connector 501 and the second connector 502 under the control of an input signal 636. That is, in this example, depending on the value of the input signal 636, the first connector 501 can be connected to the second connector 502, or the first connector can be disconnected from the second connector.

[0042] exist Figure 6E In the example of FIG, the second die 160 is operable to receive (read) input from the first connector 501 through the hybrid bonding layer 130. In an embodiment, the second die 160 is operable to send (write) input to the second connector 502 through the hybrid bonding layer 130. The input written to the second connector 502 may or may not be the input read from the first connector 501.

[0043] Figures 6A-6E The examples can be used in different combinations to configure the memory architecture 100 in different ways for different use cases. Figure 1 Table 1 provides an example of how the memory architecture 100 can be configured in different ways for different use cases. Embodiments according to the present invention are not limited to the examples of Table 1.

[0044] Table 1: Example configuration

[0045]

[0046] In Table 1, DDR refers to double data rate, pseudo-bank simulates a fast memory bank but is not an actual memory bank, SLP refers to sub-level parallelism, Half-DRAM refers to an architecture in which DRAM is organized so that only half a row is activated, High BW refers to High Bandwidth Memory (HBM), and tCCD Opt refers to optimization of tCCD (column command latency). The entries in the columns / rows of Table 1 refer to figures in this article; for example, "6C" refers to Figure 6C An example of how to read Table 1 is as follows: To convert the memory architecture 100 ( Figure 1 ) is configured as HBM, Figure 2 The GWL segment uses Figure 6A 、 Figure 6B or Figure 6C Configuration to connect; Figure 2 The CSL segment uses Figure 6A or Figure 6C Configuration to connect; Figure 2 The GDL segment uses Figure 6E configuration to connect; and Figure 2 LDL segment use Figure 6C configuration to connect.

[0047] Also refer to Figure 1 , note that the physical layout of the die 120 and 160 described above is formed during the corresponding fabrication of those die. Figure 6A 、 Figure 6B and Figure 6D In the exemplary embodiment, the configuration of chipset 160 depends on the values ​​of input signals 606, 616, and 636, respectively. Different computer memory architectures can be formed by assembling chipset 120 with different versions of chipset 160. In other words, while the different versions of chipset 120 and chipset 160 are each standardized, chipset 120 can be combined with versions of chipset 160 that are selected and configured based on the needs or preferences of a user to produce a computer memory architecture customized to one or more predetermined use cases of the user.

[0048] In addition to the other advantages and benefits described herein, the architecture according to embodiments of the present invention provides benefits such as the following: The pseudo-bank and SLP architecture according to embodiments of the present invention advantageously hides activation (see Figure 7 (example), improves bandwidth utilization, and reduces latency. The semi-DRAM architecture according to embodiments of the present invention advantageously reduces activation power, is flexible, and improves bandwidth utilization. The high-BW architecture according to embodiments of the present invention increases input / output at the subarray level. The tCCD Opt architecture according to embodiments of the present invention reduces tCCD latency when accessing predefined memory areas.

[0049] Figure 7 Included are two timelines 701 and 702 showing a comparison of signal sequences for a conventional 3D-DRAM architecture versus a 3D-DRAM configured as a pseudo-bank architecture in an embodiment according to the present invention. As seen in Table 1, in the pseudo-bank architecture, Figure 2 The GWL segment, CSL segment and LDL segment are used Figure 6C configuration to connect, and Figure 2 The GDL segment uses Figure 6D configuration (using switch 632) to connect.

[0050] refer to Figure 7In a conventional 3D-DRAM, in timeline 701, an activation signal (ACT) is sent for a subarray (e.g., SUB-0); a dual read (RD) of the subarray is signaled; a precharge signal (PRE) is sent; followed by an activation signal for a second subarray (e.g., SUB-1) and a read signal for the second subarray. In timeline 702 of a 3D-DRAM configured as a pseudo-bank architecture according to an embodiment of the present invention, an activation signal is sent for a subarray (e.g., SUB-0); switch 632 is turned off (SW-OFF); a dual read of the subarray is signaled, and in parallel, a precharge signal is sent, followed by an activation signal for a second subarray (e.g., SUB-1); a precharge signal is sent; switch 632 is turned on (SW-ON); and a read of the second subarray is signaled. Thus, for a 3D-DRAM configured as a pseudo-bank architecture according to an embodiment of the present invention, the first precharge signal and activation signal for the second array, and therefore the read signal for the second array, are sent earlier than the corresponding signals for a conventional architecture.

[0051] Figure 8 is a configuration according to an embodiment of the present invention Figure 1 Flowchart 800 of an example of a method of computer memory architecture 100 .

[0052] exist Figure 8 In block 802 , information for identifying and / or selecting a use case for the computer storage architecture 100 is accessed.

[0053] In block 804 , a control signal is generated according to the identified or selected use case.

[0054] In block 806, control is set in the computer storage architecture 100 ( Figure 1 ) of the second chip 160 to connect the first connector 501 to the second connector 502 ( Figure 5 ).

[0055] In one embodiment, reference Figure 6A , a component provided in the second chip die 160 is a multiplexer 604, which is controlled by a signal 606 to select input from the first connector 501 and send the input from the first connector to the second connector 502. In such an embodiment, the second chip die also includes a decoder 602, in which case the multiplexer 604 is controlled by a signal 606 to select input from the decoder (rather than from the first connector 501) and send the input from the decoder to the second connector 502.

[0056] In one embodiment, reference Figure 6B, the component provided in the second chip die 160 is a flip-flop 612 , which is controlled by a signal 616 to connect the first connector and the second connector.

[0057] In one embodiment, reference Figure 6D , the component provided in the second chip die 160 is a switch 632. In this embodiment, the switch 632 is controlled by a signal 636 to turn on the switch to connect the first connector 501 and the second connector 502, and to turn off the switch to disconnect the first connector from the second connector.

[0058] The process parameters and step sequences described and / or illustrated herein are provided as examples only and can be varied as needed. For example, although the steps illustrated and / or described herein may be shown or discussed in a particular order, the steps do not necessarily need to be performed in the order illustrated or discussed. The various example methods described and / or illustrated herein may also omit one or more of the steps described or illustrated herein or include additional steps in addition to those disclosed.

[0059] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in this disclosure is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the disclosure.

[0060] Thus, embodiments in accordance with the present invention have been described.While the present disclosure has been described in terms of particular embodiments, the invention should not be construed as limited by such embodiments but rather should be construed in accordance with the following claims.

Claims

1. A computer system storage device, comprising: a plurality of memory cell arrays; as well as a plurality of lines coupled to the memory cell array, wherein the plurality of lines include a plurality of word lines, a plurality of column select lines, and a plurality of data lines; wherein a first line of the plurality of lines includes a first segment and a second segment separated by a first gap, the first gap being configured to prevent electrical signals from being transmitted from the first segment to the second segment; A first pin is connected to a first segment of the first wire, and a second pin is connected to a second segment of the first wire.

2. The computer system memory device of claim 1, wherein the first pin and the second pin are accessible at an external surface of the computer system memory device.

3. The computer system memory device of claim 1 , wherein the first line is a first word line of a first memory cell and a second memory cell of one of the plurality of memory cell arrays, wherein the second word line of the first memory cell and the second memory cell comprises a first segment and a second segment separated by a second gap, the second gap preventing an electrical signal from being transmitted from the first segment of the second word line to the second segment of the second word line.

4. The computer system memory device according to claim 1 , wherein the first line is a first column selection line coupled to one of the plurality of memory cell arrays, and wherein a second column selection line coupled to the memory cell array includes a first segment and a second segment separated by a second gap, the second gap preventing an electrical signal from being transmitted from the first segment of the second column selection line to the second column selection line.

5. The computer system memory device of claim 1 , wherein the first line is a first global data line coupled to one of the plurality of memory cell arrays, wherein a second global data line coupled to the memory cell array includes a first segment and a second segment separated by a second gap, the second gap preventing an electrical signal from being transmitted from the first segment of the second global data line to the second segment of the second global data line.

6. The computer system memory device of claim 1 , wherein the first line is a local data line of a memory cell of one of the plurality of memory cell arrays, wherein a second local data line coupled to the memory cell comprises a first segment and a second segment separated by a second gap, the second gap preventing an electrical signal from being transmitted from the first segment of the second local data line to the second local data line.

7. A configurable computer storage architecture comprising: A first chip, the first chip comprising: a plurality of memory cell arrays; a plurality of lines coupled to the memory cell array, wherein the plurality of lines include a plurality of word lines, a plurality of column select lines, and a plurality of data lines, wherein a first line of the plurality of lines includes a first segment and a second segment separated by a first gap, the first gap preventing an electrical signal from being transmitted from the first segment to the second segment; connected to a first pin of a first segment of said first wire; and a second pin connected to a second segment of the first wire; a second chip die coupled to the first chip die; and A first connector is coupled to the first pin.

8. The configurable computer memory architecture of claim 7 , wherein the first line is a first word line of a first memory cell and a second memory cell of one of the plurality of memory cell arrays, wherein the second word line of the first memory cell and the second memory cell comprises a first segment and a second segment separated by a second gap, the second gap preventing an electrical signal from propagating from the first segment of the second word line to the second segment of the second word line.

9. The configurable computer memory architecture of claim 7 , wherein the first line is a first column select line coupled to one of the plurality of memory cell arrays, wherein a second column select line coupled to the memory cell array includes a first segment and a second segment separated by a second gap, the second gap preventing an electrical signal from being transmitted from the first segment of the second column select line to the second segment of the second column select line.

10. The configurable computer memory architecture of claim 7 , wherein the first line is a first global data line coupled to one of the plurality of memory cell arrays, wherein a second global data line coupled to the memory cell array comprises a first segment and a second segment separated by a second gap, the second gap preventing electrical signals from propagating from the first segment of the second global data line to the second global data line.

11. The configurable computer memory architecture of claim 7 , wherein the first line is a local data line of a memory cell of one of the plurality of memory cell arrays, wherein a second local data line coupled to the memory cell comprises a first segment and a second segment separated by a second gap, the second gap preventing electrical signals from propagating from the first segment of the second local data line to the second local data line.

12. The configurable computer storage architecture of claim 7 , further comprising a second connector coupled to the second pin, wherein the second chip comprises a trigger coupled to the first connector and the second connector, and wherein the trigger is operable to connect the first connector and the second connector.

13. The configurable computer storage architecture of claim 7 , further comprising a second connector coupled to the second pin, wherein the second chip comprises a multiplexer coupled to the first connector and the second connector, and wherein the multiplexer is operable to connect the first connector and the second connector.

14. The configurable computer storage architecture of claim 13 , wherein the second chiplet further comprises a decoder coupled to the multiplexer, wherein the multiplexer is also operable to connect the decoder and the second connector, and wherein the multiplexer is also operable to select between input from the first connector and input from the decoder.

15. The configurable computer storage architecture of claim 7 further comprising a second connector coupled to the second pin, wherein the second chip comprises a switch coupled to the first connector and the second connector, and wherein the switch is operable to connect the first connector and the second connector.

16. The configurable computer storage architecture of claim 7, wherein the second chiplet is operable to receive input from the first pin through the first connector.

17. The configurable computer storage architecture of claim 7, further comprising a second connector coupled to the second pins, wherein the second die is operable to write input to the second pins through the second connector.

18. The configurable computer memory architecture of claim 7, further comprising a hybrid bonding layer between the first die and the second die.

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