Calibration of dual-path pulse width modulation system

Abstract

This application relates to the calibration of a dual-path pulse width modulation system, and more particularly to a system that may include: a digital pulse width modulator subsystem; a first path coupled to the output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage; a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator; a controller that selects between the first path and the second path for processing the signal based on one or more characteristics of the signal; and a calibration system configured to calibrate at least one of a first gain of the first path and a second gain of the second path such that, when switching between the first path and the second path or vice versa, the first gain and the second gain are at least approximately equal, thereby minimizing artifacts caused by the switching.

Description

[0001] This application is a divisional application of Chinese patent application No. 201880078493.7, filed on October 3, 2018, entitled "Calibration of a Dual-Path Pulse Width Modulation System". Technical Field

[0002] This disclosure generally relates to circuitry for audio or haptic devices, including but not limited to personal audio devices (such as cordless phones and media players) or devices that include haptic modules. Background Technology

[0003] Personal audio devices, including cordless phones (such as mobile / cellular phones), MP3 players, and other user audio devices, are widely used. Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers. This circuitry typically includes a power amplifier for driving the audio output signal to the headphones or speakers. Generally, the power amplifier amplifies the audio signal by drawing power from a power source and controls the audio output signal to match the shape of the input signal but with a larger amplitude.

[0004] An example of an audio amplifier is a Class D amplifier. A Class D amplifier (also known as a "switching amplifier") can be an electronic amplifier in which the amplifying device (e.g., a transistor, typically a metal-oxide-semiconductor field-effect transistor) operates as an electronic switch. In a Class D amplifier, the signal to be amplified can be converted into a series of pulses by pulse width modulation, pulse density modulation, or another modulation method, such that the signal is converted into a modulated signal, where the pulse characteristics of the modulated signal (e.g., pulse width, pulse density, etc.) are a function of the signal magnitude. After amplification by a Class D amplifier, the output pulse train can be converted back into an unmodulated analog signal by passing it through a passive low-pass filter, which can be built into the Class D amplifier or a load driven by the Class D amplifier. Class D amplifiers are commonly used because they can be more power efficient than linear analog amplifiers (because Class D amplifiers dissipate less power when heated in active devices compared to linear analog amplifiers).

[0005] Typically, a closed-loop PWM amplifier is chosen to provide an accurate load voltage with ideal total harmonic distortion (THD) and power supply rejection ratio (PSRR). A closed-loop PWM amplifier typically takes an analog voltage input and a sensed feedback voltage signal, which is fed through a closed-loop analog PWM modulator to drive the voltage across the speaker load.

[0006] However, depending on the specific application, the option of using a single PWM amplifier circuit in either open-loop or closed-loop mode to drive the load may be desirable. When using such a single PWM amplifier circuit, perceptible audio artifacts may occur when switching between open-loop and closed-loop operation, and therefore, it may be desirable to reduce or eliminate these audio artifacts. Summary of the Invention

[0007] Based on the teachings of this disclosure, one or more disadvantages or problems associated with existing methods of processing signals using amplifiers can be reduced or eliminated.

[0008] According to embodiments of this disclosure, the system may include: a digital pulse width modulator subsystem; a first path coupled to the output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage; a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, wherein one of the first path and the second path is selected based on one or more characteristics of the signal to process the signal; and a calibration system configured to calibrate at least one of a first gain of the first path and a second gain of the second path, such that when switching between the first path and the second path or vice versa, the first gain and the second gain are at least approximately equal, thereby minimizing artifacts caused by the switching.

[0009] According to these and other embodiments of the present disclosure, a method can be provided for use in a system comprising a digital pulse width modulator subsystem, a first path coupled to the output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, and a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, wherein one of the first path and the second path is selected to process the signal based on one or more characteristics of the signal. The method may include calibrating at least one of a first gain of the first path and a second gain of the second path such that, when switching between the first and second paths or vice versa, the first gain and the second gain are at least substantially equal, thereby minimizing artifacts caused by the switching.

[0010] The technical advantages of this disclosure will be apparent to those skilled in the art from the accompanying drawings, description, and claims. The objects and advantages of the embodiments will be realized and achieved, at least by means of the elements, features, and combinations particularly pointed out in the claims.

[0011] It should be understood that the foregoing general description and the following detailed description are illustrative and explanatory, and do not limit the claims set forth in this disclosure. Attached Figure Description

[0012] A more complete understanding of this embodiment and its advantages can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which the same reference numerals denote the same features, and wherein:

[0013] Figure 1 This is an illustration of an example personal audio device according to an embodiment of the present disclosure;

[0014] Figure 2 This is a block diagram of selected components of an example audio integrated circuit in a personal audio device according to embodiments of the present disclosure;

[0015] Figure 3 This is a block diagram of selected components of an example pulse width modulation amplifier according to an embodiment of the present disclosure;

[0016] Figure 4 This is a block diagram of selected components (including components for calibrating path gain) of an example reconfigurable PWM modulator according to embodiments of the present disclosure;

[0017] Figure 5 This is a block diagram of selected components (including components for calibrating path gain) of a reconfigurable PWM modulator according to another example of an embodiment of this disclosure; and

[0018] Figure 6 This is a block diagram of selected components (including components for calibrating path gain) of a reconfigurable PWM modulator according to another example of an embodiment of this disclosure. Detailed Implementation

[0019] Figure 1 This is an illustration of an example personal audio device 1 according to an embodiment of the present disclosure. Figure 1 A personal audio device 1 is depicted, which is coupled to headphones 3 in the form of a pair of earbud speakers 8A and 8B. Figure 1 The earphone 3 depicted is merely an example, and it should be understood that the personal audio device 1 can be used to connect to various audio transducers, including but not limited to headphones, earbuds, in-ear headphones, and external speakers. The plug 4 can be used to provide electrical terminals for connection between the earphone 3 and the personal audio device 1. The personal audio device 1 can provide a display for the user and receive user input using a touchscreen 2, or a standard liquid crystal display (LCD) can be combined with various buttons, sliders, and / or knobs on the surface and / or sides of the personal audio device 1. Figure 1 As also shown, the personal audio device 1 may include an audio integrated circuit (IC) 9 for generating analog audio signals for transmission to headphones 3 and / or another audio transducer (e.g., a speaker).

[0020] Figure 2This is a block diagram of selected components of an example audio IC 9 for a personal audio device according to embodiments of the present disclosure. In some embodiments, the example audio IC 9 may be used to implement... Figure 1 Audio IC 9 in the middle. For example... Figure 2 As shown, the microcontroller core 18 (e.g., a digital signal processor or "DSP") can provide a digital audio input signal DIG_IN to the digital-to-analog converter (DAC) 14, which can convert the digital audio input signal into an analog input signal V. IN The DCA 14 can provide analog signal V. IN Amplifier 16 can amplify or attenuate the analog input signal V. IN To provide audio output signal V OUT It can operate speakers, headphone transducers, line-level signal outputs and / or other suitable outputs.

[0021] Figure 3 This is a block diagram of selected components of an example pulse width modulation amplifier 22 according to an embodiment of the present disclosure. In some embodiments, the example pulse width modulation amplifier 22 may be used to implement... Figure 2 Amplifier 16 in the middle. (e.g.) Figure 3 As shown, the example pulse width modulation amplifier 22 may include a digital PWM modulator subsystem 24 and an analog PWM modulator 26, as well as a direct bypass function implemented by a multiplexer 28.

[0022] When the ANALOG MODULATOR BYPASS control signal received by multiplexer 28 is invalid, reconfigurable PWM modulator 22 can be configured to operate in analog closed-loop mode by using analog PWM modulator 26. In analog closed-loop mode, the input signal V IN It can be modulated by the digital PWM modulator subsystem 24. The analog PWM modulator 26 can receive its input from the digital PWM modulator subsystem 24, and the analog PWM modulator 26 can be used such that the output of the analog PWM modulator 26, as received and driven by the driver stage 34B, is driven into the output signal V. OUT The driver stage 34B may include multiple output switches configured to generate an output signal V from a modulated signal generated by the analog PWM modulator 26. OUT .

[0023] When the ANALOG MODULATOR BYPASS control signal received by multiplexer 28 is valid, the reconfigurable PWM modulator 22 can also be configured to operate in digital open-loop mode using digital PWM modulator subsystem 24. In digital open-loop mode, analog PWM modulator 26 and the driver stage 34B driven by analog PWM modulator 26 can be bypassed by multiplexer 28, and digital PWM modulator subsystem 24 can be utilized to make the input signal V IN The output of the digital PWM modulator subsystem 24, which is modulated by the digital PWM modulator subsystem 24 and is received and driven by the open-loop driver stage 34A, is driven as the output signal V. OUT The driver stage 34A may include multiple output switches configured to generate an output signal V from the modulated signal generated by the digital PWM modulator subsystem 24. OUT .

[0024] Changing the reconfigurable PWM modulator 22 from analog closed-loop mode and digital open-loop mode (and vice versa) can be achieved by using multiplexer 28 to select which of driver stages 34A and driver stage 34B drives the output signal V. OUT To achieve this.

[0025] In some embodiments, control circuitry (not shown) may be used to control multiplexer 28 to select a signal processing path for reconfigurable PWM modulator 22. For example, the selection of such multiplexer control signals may be based on the input signal V to the amplifier. IN One or more characteristics (e.g., magnitude, frequency, or input signal V) IN Other characteristics). Therefore, the reconfigurable PWM modulator 22 may include a digital pulse width modulator subsystem (e.g., digital PWM modulator subsystem 24), a first path coupled to the output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage (e.g., driver stage 34A), and a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator (e.g., analog PWM modulator 26), wherein one of the first path and the second path is selected for processing the signal based on one or more characteristics of the signal.

[0026] Advantageously, the aforementioned systems and methods for implementing and using systems including reconfigurable amplifiers can switch between analog closed-loop modulation amplifiers or digital open-loop modulation amplifiers using minimal additional digital logic compared to existing amplifier systems. However, the aforementioned systems may be susceptible to perceptible audio artifacts (such as “pops” and “clicks”) unless steps are taken to reduce or avoid them. Therefore, as follows regarding… Figure 4-6Described in more detail, the reconfigurable PWM modulator 22 may include a calibration subsystem configured to calibrate at least one of a first gain of a first path (the open-loop path of the digital PWM modulator subsystem 24 and the driver stage 34A) and a second gain of a second path (the closed-loop path of the analog PWM modulator 26d) such that the first and second gains are approximately equal when switching between the first and second paths, or vice versa, thereby minimizing perceptible audio artifacts caused by the switching.

[0027] Figure 4 This is a block diagram of selected components of an example reconfigurable PWM modulator 22A according to embodiments of the present disclosure. In some embodiments, the example reconfigurable PWM modulator 22A can be used to implement... Figure 3 The reconfigurable PWM modulator 22 in the example. Figure 4 As shown, a single digital PWM modulator 24A can be used to implement the digital PWM modulator subsystem 24, and the analog PWM modulator 26 can include a first-stage integrator 40, followed by one or more additional-stage integrators 42, and then a quantizer 44 that can generate an analog PWM signal to the driver stage 34B. A buffer 46 can be coupled between the digital PWM modulator 24A and the analog PWM modulator 26 to buffer the digital PWM signal generated by the digital PWM modulator 24A to the input of the analog PWM modulator 26. Gain resistors 48 and 49 can also be used to define the gain of the analog PWM modulator 26.

[0028] like Figure 4 As shown, the gains of buffer 46, gain resistor 48, and / or gain resistor 49 can be variable. When calibration is possible, the first-stage integrator 40 of the analog PWM modulator 26 can again be used as a combination of filter and comparator to detect the gain of the open-loop path including the driver stage 34A. Because one input to the comparator implemented using the first-stage integrator 40 is a digital signal generated by the digital PWM modulator 24A (or, in an alternative embodiment, the input signal to the digital PWM modulator 24A), and the other input to the comparator implemented using the first-stage integrator 40 is the output of the driver stage 34A, the output of the first-stage integrator 40 indicates the gain of the open-loop path when calibration is possible. This detected gain can then be used to appropriately set the gain of buffer 46, the resistance of gain resistor 48, and / or the resistance of gain resistor 49 so that the gain of the closed-loop path including the analog PWM modulator 26 matches the gain of the open-loop path.

[0029] Figure 5This is a block diagram of selected components of an example reconfigurable PWM modulator 22B according to embodiments of the present disclosure. In some embodiments, the example reconfigurable PWM modulator 22B can be used to implement... Figure 3 The reconfigurable PWM modulator 22 in the example. Figure 5 As shown, Figure 2 The digital PWM modulation subsystem 24 can be implemented using a first digital PWM modulator 24B and a second digital PWM modulator subsystem 24C. The digital PWM modulator 24B can drive an open-loop driver stage 34A, while the digital PWM modulator 24C can drive an analog PWM modulator 26 via a buffer 46 configured to buffer the digital PWM signal generated by the digital PWM modulator 24C and input to the analog PWM modulator 26. Gain resistors 48 and 49 can also be used to define the gain of the analog PWM modulator 26.

[0030] For example Figure 5 As shown, gain element 50 can be coupled between the inputs of reconfigurable PWM modulator 22B and digital PWM modulator 24B, and gain element 52 can be coupled between the inputs of reconfigurable PWM modulator 22B and digital PWM modulator 24C. Gain element 50 can apply a coarse gain setting to the open-loop path, while gain element 52 can apply a smaller, finer gain setting to the closed-loop path. At the output signal V... OUT The calibration engine 54 can detect the signal as it is filtered by analog filter 59, converted from analog to digital by ADC 58, and filtered by digital filter 56. This filtering ensures that calibration is performed solely based on the in-band signal components. The calibration engine 54 can also sense the input signal, allowing it to compare the input signal with the output signal V. OUT The digital domain representation is compared to determine the gain of the open-loop path. Although not shown, this comparison can be performed on the input signal and the output signal V before they are received by the calibration engine 54. OUT The digital filtering performed is similar to digital filtering, and the input signal and output signal V OUT Matching can also be delayed to properly measure the gain. Based on the determined gain, calibration engine 54 can calibrate gain element 50 and / or gain element 52 in the digital domain prior to digital modulation, such that the open-loop and closed-loop paths have the same path gain. In some embodiments, calibration engine 54 may also be able to change the resistance of gain resistor 48 and / or the resistance of gain resistor 49 to calibrate the gain of the open-loop and closed-loop paths.

[0031] During operation, Figure 5 The calibration system shown can calibrate the actual reproduced components represented by the input signal, or it can calibrate based on inaudible pilot tones that can only be used for calibration.

[0032] Figure 6 This is a block diagram of selected components of an example reconfigurable PWM modulator 22C according to embodiments of the present disclosure. In some embodiments, the example reconfigurable PWM modulator 22C can be used to implement... Figure 3 The reconfigurable PWM modulator 22 in the example. Figure 6 As shown, Figure 2 The digital PWM modulation subsystem 24 can be implemented using a single digital PWM modulator 24D. The digital PWM modulator 24D can drive the open-loop driver stage 34A, while the digital PWM modulator 24C can drive the analog PWM modulator 26 via a buffer 46 configured to buffer the digital PWM signal generated by the digital PWM modulator 24C to the analog PWM modulator 26.

[0033] For example Figure 6 As shown, gain element 60 can be coupled between the inputs of the reconfigurable PWM modulator 22C and the digital PWM modulator 24D. Before modulation by the PWM modulator 22C, gain element 60 can apply a variable gain to the input signal. At the output signal V... OUT The calibration engine 64 can detect the signal as it is filtered by analog filter 69, converted from analog to digital by ADC 68, and filtered by digital filter 66. This filtering ensures that calibration is performed solely based on in-band signal components. The calibration engine 64 can also sense the input signal, allowing it to compare the input signal with the output signal V. OUT The digital domain representation is compared to determine the gain of the open-loop path. Although not shown, this comparison can be performed on the input signal and the output signal V before they are received by the calibration engine 64. OUT The digital filtering performed is similar to digital filtering, and the input signal and output signal V OUT Matching can also be delayed to measure the gain appropriately. Based on the determined gain, calibration engine 64 can calibrate the gain element 60 in the digital domain before digital modulation, so that the open-loop and closed-loop paths have the same path gain.

[0034] The gain calibration performed according to this paper ensures that when switching between open-loop and closed-loop paths or vice versa, the first gain of the open-loop path and the second gain of the closed-loop path are approximately equal, so as to minimize artifacts caused by the switching.

[0035] Gain calibration performed according to this document can be performed at any suitable time. For example, in some embodiments, the calibration subsystem disclosed herein can be configured to calibrate the gain during product testing of the reconfigurable PWM modulator 22 or the device where the reconfigurable PWM modulator 22 resides, such that a calibration is performed before its final use. As another example, the calibration subsystem disclosed herein can be configured to calibrate the gain in real time while the audio components of the input signal are being played back. As a specific example of real-time calibration, such as Figure 5 and 6 As described in the document, when an open-loop path is selected, the calibration subsystem can be configured to detect the output of the open-loop path in order to calibrate the gain.

[0036] In these and other embodiments, the calibration subsystem can be configured to perform calibration in a series of steps while the audio components of the input signal are being played back, in order to minimize user-perceptible audio artifacts. For example, if the calibration subsystem determines that the gain should be changed by a factor of x, the calibration subsystem can change the gain in a series of steps of y, wherein during each step, the gain is changed by an amount of x / y. In some such embodiments, the calibration subsystem is further configured to switch between the zero-crossing point of the input signal and the zero-crossing point of the pulse-width modulated signal derived from the input signal within the system at consecutive steps in a series of steps.

[0037] In these and other embodiments, the calibration subsystem may be further configured (e.g., from a temperature sensor, not shown) to receive a temperature signal indicating the temperature associated with the reconfigurable PWM modulator 22 and to calibrate the gain by applying a correction factor to one or more path gains.

[0038] In these and other embodiments, the calibration subsystem may be able to perform calibration at intermittent intervals. For example, the calibration subsystem may perform calibration over a period of time and terminate calibration over another period of time before recalibrating. As another example, the calibration subsystem may initiate calibration of at least one of a first gain and a second gain in response to a change in temperature.

[0039] In these and other embodiments, the calibration subsystem may be further configured to initiate gain calibration only when the input signal (e.g., the input signal to a reconfigurable PWM modulator) is greater than a threshold size. In this embodiment, the calibration subsystem may be further configured to abort gain calibration if the input signal drops below the threshold size during the calibration process.

[0040] In these and other embodiments, the calibration subsystem may be further configured to initiate gain calibration only when the open-loop path is selected for processing. In this embodiment, the calibration subsystem may be further configured to abort gain calibration if the closed-loop path is selected for processing at any time during the calibration process.

[0041] As used herein, when two or more elements are referred to as being “coupled” to each other, the term means that the two or more elements are in electronic or mechanical communication (if applicable), whether indirectly or directly connected, with or without an intermediary element.

[0042] This disclosure includes all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments that will be understood by those skilled in the art. Similarly, where appropriate, the appended claims include all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments that will be understood by those skilled in the art. Furthermore, in the appended claims, references to means, systems, or components adapted to, arranged to, capable of, configured to, enabled, operable, or operated to perform a particular function include that means, system, or component, whether or not it or the particular function is activated, turned on, or unlocked, provided that the means, system, or component is so adapted, arranged, capable of, configured, enabled, operable, or operated. All examples and conditional language described herein are intended for educational purposes to aid the reader in understanding the inventive content and concepts contributed by the inventors to advance the art, and are to be construed as not being limited to such specifically described examples and conditions. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions, and alterations can be made to this disclosure without departing from the spirit and scope thereof.

Claims

1. A dual-path pulse width modulation system includes: Digital pulse width modulator subsystem; The first path, which is coupled to the output of the digital pulse width modulator subsystem, is configured to drive the open-loop driver stage; The second path, coupled to the output of the digital pulse width modulator subsystem, is configured to drive a closed-loop analog pulse width modulator, wherein one of the first path and the second path is selected to process the signal based on one or more characteristics of the signal. as well as The calibration subsystem is configured as follows: The calibration is performed intermittently so that when switching between the first path and the second path or vice versa, the first gain of the first path and the second gain of the second path are equal, so as to minimize artifacts caused by the switching. Receive a temperature signal indicating the temperature of the system; and In response to a change in temperature, calibration is initiated for at least one of the first gain and the second gain. The calibration subsystem is configured to detect the first gain of the first path in the analog domain using the integrator of the closed-loop analog pulse width modulator, and to match the second gain of the second path based on the detected first gain. When calibration is initiated, the integrator is configured to receive the output of the digital pulse width modulator subsystem at one input and the output of the open-loop driver stage at another input, such that the output of the integrator indicates the detected first gain.

2. The system according to claim 1, wherein the digital pulse width modulator subsystem comprises: A first digital pulse width modulator is configured to drive the first path; as well as A second digital pulse width modulator is configured to drive the second path.

3. The system of claim 1, wherein the digital pulse width modulator subsystem comprises a single pulse width modulator that drives both the first path and the second path.

4. The system of claim 1, wherein the calibration subsystem is further configured to use an integrator of the closed-loop analog pulse width modulator to detect the gain of the first path.

5. The system of claim 1, wherein the calibration subsystem is further configured to detect the second gain in the analog domain.

6. The system of claim 5, wherein the calibration subsystem is further configured to calibrate either the first gain, the second gain, or both the first gain and the second gain in the analog domain.

7. The system of claim 5, wherein the calibration subsystem is further configured to calibrate either the first gain, the second gain, or both the first gain and the second gain in the digital domain.

8. The system of claim 1, wherein the calibration subsystem is further configured to detect at least one of the first gain and the second gain in the digital domain by using an analog-to-digital converter.

9. The system of claim 8, wherein the calibration subsystem calibrates either the first gain, the second gain, or both the first gain and the second gain in the digital domain.

10. The system of claim 1, wherein the calibration subsystem is configured to calibrate at least one of the first gain and the second gain during a product test of the system.

11. The system of claim 1, wherein the calibration subsystem is configured to calibrate at least one of the first gain and the second gain in real time while the audio components of the signal are being played back to the transducer.

12. The system of claim 11, wherein the calibration subsystem is configured to detect the output of the first path when the first path is activated, so as to calibrate at least one of the first gain and the second gain.

13. The system of claim 11, wherein the calibration subsystem is configured to perform calibration in a series of steps while the audio components of the signal are being played back to the transducer, so as to minimize user-perceptible audio artifacts.

14. The system of claim 13, wherein the calibration subsystem is further configured to switch between successive steps in a series of steps at one of the zero-crossing points of the input signal and the zero-crossing points of the pulse width modulation signal derived from the input signal within the system.

15. A dual-path pulse width modulation system includes: Digital pulse width modulator subsystem; The first path, which is coupled to the output of the digital pulse width modulator subsystem, is configured to drive the open-loop driver stage; The second path, coupled to the output of the digital pulse width modulator subsystem, is configured to drive a closed-loop analog pulse width modulator, wherein one of the first path and the second path is selected to process the signal based on one or more characteristics of the signal. as well as A calibration subsystem is configured to detect a first gain of the first path in the analog domain using an integrator of the closed-loop analog pulse width modulator, and to match a second gain of the second path to the detected first gain, such that when switching between the first and second paths or vice versa, the first gain of the first path and the second gain of the second path are equal, in order to minimize artifacts caused by the switching. When calibration is initiated, the integrator is configured to receive the output of the digital pulse width modulator subsystem at one input and the output of the open-loop driver stage at another input, such that the output of the integrator indicates the detected first gain.

16. The system of claim 15, wherein the calibration subsystem is configured to disable calibration of at least one of the first gain and the second gain if the input signal is below a threshold value.

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