Matching circuit

Abstract

A matching circuit includes an input terminal, an output terminal, a first impedance component, a first set of switching devices, a second impedance component, a second set of switching devices, and a controller. The first impedance component includes a first terminal coupled between the input terminal and the output terminal, and a second terminal. The first set of switching devices includes a first terminal coupled to the second terminal of the first impedance component, and a second terminal coupled to a reference terminal. The second impedance component includes a first terminal coupled between the second terminal of the first impedance component and the first terminal of the first set of switching devices, and a second terminal. The second set of switching devices includes a first terminal coupled to the second terminal of the second impedance component, and a second terminal coupled to the reference terminal. The controller is used to control the first set of switching devices and the second set of switching devices based on a detection signal.

Description

Technical Field

[0001] This invention relates to a matching circuit, and more particularly to a matching circuit for a radio frequency communication system. Background Technology

[0002] In communication systems, data is carried on radio frequency (RF) signals for wireless transmission. However, before wireless transmission, during the transmission from the signal source to the load, the output impedance of the signal source and the input impedance of the load may differ. This impedance mismatch can cause signal reflection, resulting in power loss. Therefore, a matching circuit is installed between the signal source and the load to reduce RF signal reflection and achieve maximum power transmission.

[0003] Conventional matching circuits use multiple parallel capacitor branches and select one or more capacitor branches from these parallel branches to provide multiple impedances. However, in order to effectively isolate unselected capacitor branches, conventional matching circuits use multiple stacked transistors of the same number in a certain capacitor branch, which makes it difficult to reduce the area of ​​the matching circuit and increases manufacturing costs. Summary of the Invention

[0004] This invention provides a matching circuit, comprising an input terminal, an output terminal, a first impedance component, a first set of switching devices, a second impedance component, a second set of switching devices, and a controller. The first impedance component includes a first terminal coupled between the input terminal and the output terminal, and a second terminal. The first set of switching devices includes a first terminal coupled to the second terminal of the first impedance component, a second terminal coupled to a reference terminal, and a plurality of control terminals. The second impedance component includes a first terminal coupled between the second terminal of the first impedance component and the first terminal of the first set of switching devices, and a second terminal. The second set of switching devices includes a first terminal coupled to the second terminal of the second impedance component, a second terminal coupled to the reference terminal, and a plurality of control terminals. The controller is coupled to the control terminals of the first set of switching devices and the control terminals of the second set of switching devices, and is used to control the first set of switching devices and the second set of switching devices based on a detection signal. The first set of switching devices includes a plurality of first transistors connected in series, and the second set of switching devices includes a plurality of second transistors connected in series, wherein the number of the plurality of first transistors is different from the number of the plurality of second transistors. Attached Figure Description

[0005] Figure 1 This is a block diagram of a radio frequency circuit in an embodiment of the present invention.

[0006] Figure 2 This is for Figure 1 A circuit diagram of a matching circuit.

[0007] Figure 3 This is for Figure 1The circuit diagram of another matching circuit.

[0008] Figure 4 This is for Figure 1 The circuit diagram of another matching circuit.

[0009] Figure 5 This is for Figure 1 The circuit diagram of another matching circuit.

[0010] Symbol Explanation

[0011] 1: Radio Frequency Circuit

[0012] 10: Preamplifier Circuit

[0013] 12: Matching circuit

[0014] 120: Detector

[0015] 122: Controller

[0016] 14: Power stage circuit

[0017] 20, 24, 30, 32: Capacitors

[0018] 40, 44, 50, 52: Impedance components

[0019] 22: First set of switching devices

[0020] 26: Second set of switching devices

[0021] 34: Third set of switching devices

[0022] Cdg: Drain-to-gate parasitic capacitance

[0023] Cgs: Gate-to-source parasitic capacitance

[0024] N1: Input terminal

[0025] N2: Output terminal

[0026] N3: Reference end

[0027] M11 to M1i: First transistors

[0028] M21 to M2j: Second transistor

[0029] M31 to M3k: Third transistor

[0030] GND: Reference voltage

[0031] Sd: Detection signal

[0032] Srf: Input signal

[0033] Srf': Output signal

[0034] SW1, SW2, SW3: Control signals Detailed Implementation

[0035] Figure 1 This is a block diagram of a radio frequency (RF) circuit 1 according to an embodiment of the present invention. The RF circuit 1 can operate on RF signals and may include a pre-stage circuit 10, a matching circuit 12, and a post-stage circuit 14. The matching circuit 12 may be coupled between the pre-stage circuit 10 and the post-stage circuit 14.

[0036] The preamplifier circuit 10 and the output circuit 14 can be power amplifiers, low-noise amplifiers, antennas, or other radio frequency (RF) circuits. For example, if the RF circuit 1 is a transmitter, the preamplifier circuit 10 can be a power amplifier, and the output circuit 14 can be an antenna; if the RF circuit 1 is a receiver, the preamplifier circuit 10 can be an antenna, and the output circuit 14 can be a low-noise amplifier. The preamplifier circuit 10 can output the input signal Srf to the matching circuit 12, and the matching circuit 12 can output the output signal Srf' to the output circuit 14. The input signal Srf and the output signal Srf' can have radio frequency frequencies.

[0037] Matching circuit 12 can be adjusted to different modes based on the electrical characteristics measured from the input signal Srf, the preamplifier circuit 10, and / or the power amplifier circuit 14, thereby providing a plurality of possible impedances. The electrical characteristics may be the frequency of the input signal Srf, the power of the input signal Srf, the phase of the input signal Srf, the output impedance of the preamplifier circuit 10, and / or the temperature of the preamplifier circuit 10.

[0038] Matching circuit 12 may include a detector 120 and a controller 122 coupled to the detector 120. Detector 120 can detect electrical characteristics to generate a detection signal Sd. Controller 122 can control matching circuit 12 to provide a suitable impedance based on the detection signal Sd, thereby generating an output signal Srf' based on the input signal Srf, and transmitting the output signal Srf' to the subsequent circuit 14.

[0039] Figure 2This is a circuit diagram of a matching circuit 12. The matching circuit 12 can provide several capacitance values, from which a capacitance value can be selected. The matching circuit 12 may include a detector 120, a controller 122, an input terminal N1, an output terminal N2, a capacitor 20, a first set of switching devices 22, a capacitor 24, and a second set of switching devices 26. The input terminal N1 may be coupled to the preceding stage circuit 10, and the output terminal N2 may be coupled to the following stage circuit 14. The capacitor 20 may include a first terminal coupled between the input terminal N1 and the output terminal N2; and a second terminal. The first set of switching devices 22 may include a first terminal coupled to the second terminal of the capacitor 20; a second terminal coupled to a reference terminal N3; and a plurality of control terminals. The reference terminal N3 may provide a reference voltage GND, such as 0V or other fixed voltage. The capacitor 24 may include a first terminal coupled to the second terminal of the capacitor 20 and the first terminal of the first set of switching devices 22; and a second terminal. The second set of switching devices 26 may include a first terminal coupled to the second terminal of capacitor 24; a second terminal coupled to reference terminal N3; and a plurality of control terminals. Controller 122 may be coupled to a plurality of control terminals of the first set of switching devices 22 and a plurality of control terminals of the second set of switching devices 26.

[0040] Capacitor 20 may have a capacitance value C1, and capacitor 24 may have a capacitance value C2. The capacitance values ​​C1 and C2 may be the same or different. For example, capacitance value C1 may be 'a', and capacitance value C2 may be 2a.

[0041] The first set of switching devices 22 includes a plurality of first transistors M11 to M1i connected in series, where i is the number of first transistors M11 to M1i, and i is a positive integer. The first set of switching devices 22 can control the coupling between the second terminal of capacitor 20 and the reference terminal N3 according to the switch control signal SW1. The control signal SW1 can be set to an enable level or a disable level. When the control signal SW1 is set to the enable level, the first transistors M11 to M1i can be turned on to couple the second terminal of capacitor 20 to the reference terminal N3; when the control signal SW1 is set to the disable level, the first transistors M11 to M1i can be turned off to isolate the second terminal of capacitor 20 from the reference terminal N3. The enable level can be a high level, for example, 0.7V; the disable level can be a low level, for example, 0V. The second set of switching devices 26 includes a plurality of second transistors M21 to M2j connected in series, where j is the number of second transistors M21 to M2j, and j is a positive integer. The second set of switching devices 26 can control the coupling between the second terminal of capacitor 24 and the reference terminal N3 according to the switching control signal SW2. The control signal SW2 can be set to an enable level or a disable level. When the control signal SW2 is set to the enable level, the second transistors M21 to M2j can be turned on to couple the second terminal of capacitor 24 to the reference terminal N3; when the control signal SW2 is set to the disable level, the second transistors M21 to M2j can be turned off to isolate the second terminal of capacitor 24 from the reference terminal N3. The first transistors M11 to M1i and the second transistors M21 to M2j can be N-type metal-oxide-semiconductor field-effect transistors (MOSFETs) of the same size. In some embodiments, the first transistors M11 to M1i and the second transistors M21 to M2j can be P-type MOSFETs of the same size, with the enable level being a low level and the disable level being a high level.

[0042] Since each of the first transistors M11 to M1i has a drain-to-gate parasitic capacitance Cdg and a gate-to-source parasitic capacitance Cgs, even if the control signal SW1 is set to the disabled level, the voltage of the input signal Srf can still be coupled to the reference terminal N3 via capacitor 20 and the respective gate parasitic capacitance Cdg and source parasitic capacitance Cgs of the first transistors M11 to M1i. If the number of first transistors M11 to M1i is insufficient and / or the voltage amplitude of the input signal Srf is too large, causing the voltage to be coupled to the reference terminal N3 via capacitor 20 and the respective parasitic capacitances Cdg and Cgs of the first transistors M11 to M1i, the voltage difference between the gate and source of the first transistors M11 to M1i may exceed the critical voltage, making it impossible for the first transistors M11 to M1i to be substantially turned off, and the second terminal of capacitor 20 cannot be substantially isolated from the reference terminal N3. Therefore, the number i of the first transistors M11 to M1i can be set sufficiently to substantially isolate the second terminal of capacitor 20 from the reference terminal N3. For example, when the power of the input signal Srf is 36dBm, the number i can be set to 12 so that when the control signal SW1 is set to the disabled level, the second terminal of capacitor 20 is substantially isolated from the reference terminal N3. The number i can be positively correlated with the maximum voltage across the second terminal of capacitor 20 to the reference terminal N3 when the matching circuit 12 is operating. For example, when the maximum voltage across the voltage is 4V, the number i can be 12, and when the maximum voltage across the voltage is (4 / 3)V, the number i can be 4 (=12 / 3). For example, the number i of the first transistors M11 to M1i can be the same as or different from the number j of the second transistors M21 to M2j. In some embodiments, when the capacitance value C2 of capacitor 24 is greater than the capacitance value C1 of capacitor 20 by a certain degree, for example, the capacitance value C2 is 10 times the capacitance value C1, the number i of the first transistors M11 to M1i and the number j of the second transistors M21 to M2j can be designed to be the same. In other embodiments, the number i of the first transistors M11 to M1i can be greater than the number j of the second transistors M21 to M2j. For example, when the capacitance value C1 is a and the capacitance value C2 is 2a, the number i can be 4 and the number j can be 1. In some embodiments, the second set of switching devices 26 can be used to provide a more accurate matching impedance. In other embodiments, the second set of switching devices 26 can be selectively removed from the matching circuit 12 to couple capacitor 24 to the reference terminal N3, thereby further reducing the area of ​​the matching circuit 12.

[0043] Depending on the states of the first set of switching devices 22 and the second set of switching devices 26, the matching circuit 12 can be set to either the first mode or the second mode, providing corresponding equivalent capacitance values ​​as shown in Table 1:

[0044] Table 1

[0045] First set of switching devices 22 Second set of switching devices 26 Equivalent capacitance value First Mode Deadline Conductivity <![CDATA[(1 / C1+1 / C2) -1 ]]> Second Mode Conductivity On / Off C1

[0046] In the first mode, the controller 122 can turn off the first set of switching devices 22 and turn on the second set of switching devices 26 to set capacitors 20 and 24 in series and enable the matching circuit 12 to provide an equivalent capacitance value (1 / C1+1 / C2). -1 The equivalent capacitance value of the first mode can be derived from the capacitance values ​​C1 and C2. For example, when the capacitance value C1 is a and the capacitance value C2 is 2a, the equivalent capacitance value of the first mode can be (2 / 3)a.

[0047] In the second mode, the controller 122 can turn on the first set of switching devices 22 and turn on or off the second set of switching devices 26 to couple the second terminal of capacitor 20 to the reference terminal N3, and cause the matching circuit 12 to provide the equivalent capacitance value C1 for the second mode. For example, when the capacitance value C1 is a, the equivalent capacitance value for the second mode can be a. The equivalent capacitance value (a) for the second mode is greater than the equivalent capacitance value ((2 / 3)a) for the first mode.

[0048] The detection signal Sd can correspond to different modes, such as the first mode or the second mode. The controller 122 can generate control signals SW1 and SW2 based on the detection signal Sd, using control signal SW1 to control the first set of switching devices 22, and using control signal SW2 to control the second set of switching devices 26.

[0049] In some embodiments, the detector 120 can detect the frequency of the input signal Srf and generate a detection signal Sd based on the frequency of the input signal Srf. In some embodiments, the controller 122 can select a higher equivalent capacitance value for higher frequencies of the input signal Srf and a lower equivalent capacitance value for lower frequencies of the input signal Srf. If the detection signal Sd indicates that the frequency of the input signal Srf is lower than a frequency threshold, the controller 122 can control the first set of switching devices 22 and the second set of switching devices 26 to operate in a first mode. If the detection signal Sd indicates that the frequency of the input signal Srf is higher than a frequency threshold, the controller 122 can control the first set of switching devices 22 and the second set of switching devices 26 to operate in a second mode. Therefore, the equivalent capacitance value in the second mode is greater than the equivalent capacitance value in the first mode. For a given frequency (f), since the impedance (Z) of a capacitor is inversely proportional to its capacitance (C), i.e., Z = 1 / (j*2πf*C), the equivalent impedance of the matching circuit 12 in the second mode is less than that in the first mode, and the operating frequency in the second mode is higher than that in the first mode. The matching circuit 12 can be used as a variable resonator, allowing frequency components near the operating frequency in the input signal Srf to pass through and attenuating frequency components far from the operating frequency in the input signal Srf to generate the output signal Srf'. Therefore, the subsequent circuit 14 does not need to further process the output signal Srf', thereby reducing the circuit complexity of the subsequent circuit 14. The degree of frequency component attenuation can increase with the distance between the frequency component and the resonant frequency. For example, in some embodiments, the frequency to be attenuated can be greater than or lower than the operating frequency. For instance, in the second mode, the resonant frequency can be 5 GHz, and frequency components of 6 GHz and 2.5 GHz can be attenuated, and the 5 GHz frequency component can pass through the matching circuit 12, so that the output signal Srf' includes the 5 GHz frequency but does not include the 2.5 GHz and 6 GHz frequency components. Similarly, in the first mode, the resonant frequency can be 4.5 GHz, and the frequency components of 6 GHz and 2.5 GHz can be attenuated. The 4.5 GHz frequency component can pass through the matching circuit 12, so that the output signal Srf' contains the 4.5 GHz frequency component but does not contain the 2.5 GHz and 6 GHz frequency components.

[0050] In other embodiments, the controller 122 may select a higher equivalent capacitance value for a lower frequency input signal Srf and a lower equivalent capacitance value for a higher frequency input signal Srf. If the detection signal Sd indicates that the frequency of the input signal Srf is higher than a frequency threshold, the controller 122 may control the first set of switching devices 22 and the second set of switching devices 26 to operate in a first mode. If the detection signal Sd indicates that the frequency of the input signal Srf is lower than a frequency threshold, the controller 122 may control the first set of switching devices 22 and the second set of switching devices 26 to operate in a second mode. Since the impedance (Z) of a capacitor is inversely proportional to the product of its capacitance (C) and the signal frequency (f), i.e., Z = 1 / (j*2πf*C), choosing a lower equivalent capacitance value for high-frequency input signals Srf and a higher equivalent capacitance value for low-frequency input signals Srf ensures that the impedance of the matching circuit 12 remains substantially constant and is independent of the frequency of the input signal Srf. This is suitable for transmitting wideband input signals Srf between the front-end circuit 10 and the back-end circuit 14. Therefore, in this embodiment, the matching circuit 12 can be applied to a large bandwidth range.

[0051] In some embodiments, the input signal Srf may remain substantially constant in frequency, and the detector 120 may detect the power of the input signal Srf and generate a detection signal Sd based on the power of the input signal Srf. The controller 122 may select a higher equivalent capacitance value for the higher power input signal Srf and a lower equivalent capacitance value for the lower power input signal Srf. If the detection signal Sd indicates that the power of the input signal Srf is below a power threshold, the controller 122 may control the first set of switching devices 22 and the second set of switching devices 26 to operate in a first mode. If the detection signal Sd indicates that the power of the input signal Srf is above a power threshold, the controller 122 may control the first set of switching devices 22 and the second set of switching devices 26 to operate in a second mode. For higher power input signal Srf, the lower equivalent impedance of the second mode provides a stronger attenuation effect on input signal Srf; for lower power input signal Srf, the higher equivalent impedance of the first mode provides a weaker attenuation effect on input signal Srf, thereby keeping the power of output signal Srf' substantially constant.

[0052] In some embodiments, the input signal Srf may remain substantially constant in frequency, and the detector 120 may detect the phase of the input signal Srf and generate a detection signal Sd based on the phase of the input signal Srf. The controller 122 may select a higher equivalent capacitance value for the leading phase of the input signal Srf and a lower equivalent capacitance value for the lagging phase of the input signal Srf. If the detection signal Sd indicates that the phase of the input signal Srf leads the reference signal, the controller 122 may control the first set of switching devices 22 and the second set of switching devices 26 to operate in a second mode. If the detection signal Sd indicates that the phase of the input signal Srf lags the reference signal, the controller 122 may control the first set of switching devices 22 and the second set of switching devices 26 to operate in a first mode. The reference signal may be generated by internal or external circuitry; for example, it may be generated using an oscillator. For the leading phase of the input signal Srf, the lower equivalent impedance of the second mode can cancel the excessive phase lead in the input signal Srf; for the lagging phase of the input signal Srf, the higher equivalent impedance of the first mode can cancel the excessive phase lag in the input signal Srf, thereby keeping the phase of the output signal Srf' substantially constant.

[0053] In some embodiments, the input signal Srf can remain substantially constant in frequency. Detector 120 can detect the output impedance of the preamplifier circuit 10 and generate a detection signal Sd based on the output impedance of the preamplifier circuit 10. Controller 122 can select a higher equivalent capacitance value for a lower output impedance of the preamplifier circuit 10 and a lower equivalent capacitance value for a higher output impedance of the preamplifier circuit 10. If the detection signal Sd indicates that the output impedance of the preamplifier circuit 10 is below an impedance threshold, controller 122 can control the first set of switching devices 22 and the second set of switching devices 26 to operate in a second mode. If the detection signal Sd indicates that the output impedance of the preamplifier circuit 10 is above an impedance threshold, controller 122 can control the first set of switching devices 22 and the second set of switching devices 26 to operate in a first mode. For the lower output impedance (R1) of the preamplifier circuit 10, the higher equivalent capacitance (Ch) of the matching circuit 12 in the second mode can generate the time constant (τ=Rl*Ch) of the matching circuit 12, and for the higher output impedance (Rh) of the preamplifier circuit 10, the lower equivalent impedance (Cl) of the matching circuit 12 in the first mode can keep the time constant of the matching circuit 12 substantially unchanged (τ=Rh*Cl), thereby keeping the delay of the output signal Srf′ substantially constant.

[0054] In some embodiments, the input signal Srf can remain substantially constant in frequency, and the detector 120 can detect the temperature of the preamplifier circuit 10 and generate a detection signal Sd based on the temperature of the preamplifier circuit 10. The preamplifier circuit 10 can be a power amplifier, and the gain of the power amplifier decreases as the temperature increases, i.e., the higher the temperature, the lower the gain. Therefore, the controller 122 can select a higher equivalent capacitance value for the lower temperature of the preamplifier circuit 10 and a lower equivalent capacitance value for the higher temperature of the preamplifier circuit 10. If the detection signal Sd indicates that the temperature of the preamplifier circuit 10 is below a temperature threshold, the controller 122 can control the first set of switching devices 22 and the second set of switching devices 26 to operate in a second mode. If the detection signal Sd indicates that the temperature of the preamplifier circuit 10 is above a temperature threshold, the controller 122 can control the first set of switching devices 22 and the second set of switching devices 26 to operate in a first mode. For the lower temperature of the preceding circuit 10, the lower equivalent impedance of the second mode provides a stronger attenuation effect on the input signal Srf; for the higher temperature of the preceding circuit 10, the higher equivalent impedance of the first mode provides a weaker attenuation effect on the input signal Srf, thereby keeping the power of the output signal Srf' substantially constant.

[0055] In some embodiments, a first mode may correspond to a first frequency, a second mode may correspond to a second frequency, and / or the second frequency may be greater than the first frequency. For example, the first frequency may be 2.3 GHz, and the second frequency may be 2.4 GHz. When the input signal Srf is 2.3 GHz, the matching circuit 12 may be set to the first mode to perform impedance matching for the 2.3 GHz input signal Srf; when the input signal Srf is 2.4 GHz, the matching circuit 12 may be set to the second mode to perform impedance matching for the 2.4 GHz input signal Srf. In other embodiments, the operating mode of the matching circuit 12 may be set according to the output impedance of the preceding stage circuit of the matching circuit 12. For example, the output impedance of the preceding stage circuit may be an on-resistance or a off-resistance. When the output impedance of the preceding stage circuit is an on-resistance, it may be set to the first mode to perform impedance matching for the on-resistance; when the output impedance of the preceding stage circuit is a off-resistance, it may be set to the second mode to perform impedance matching for the off-resistance. In yet another embodiment, the operating mode of the matching circuit 12 may also be set according to the input impedance of the following stage circuit of the matching circuit 12.

[0056] Matching circuit 12 controls the isolation between the second terminal of capacitor 20 and reference terminal N3 using first transistors M11 to M1i, and controls the isolation between the second terminal of capacitor 24 and reference terminal N3 using second transistors M21 to M2j. Since the maximum voltage across capacitor 24 and reference terminal N3 is less than the maximum voltage across capacitor 20 and reference terminal N3, the number j of second transistors M21 to M2j is less than the number i of first transistors M11 to M1i. Compared to the related art method of selecting from multiple parallel capacitor branches to generate different matching impedances, matching circuit 12 uses a smaller total number of transistors (i+j), thus reducing the area of ​​matching circuit 12 and manufacturing costs. Furthermore, compared to related art matching circuits, because the total number of transistors (i+j) in matching circuit 12 is reduced, the transistor sizes of first transistors M11 to M1i and second transistors M21 to M2j can be reduced to achieve the same equivalent resistance value as related art matching circuits, further reducing the area of ​​matching circuit 12.

[0057] Figure 3 This is a circuit diagram of another matching circuit 12 in an embodiment of the present invention. Figure 3 and Figure 2 The main difference in the matching circuit 12 is that it also includes capacitors 30 and 32, and a third set of switching devices 34. The following explains capacitors 30, 32, and the third set of switching devices 34.

[0058] Capacitor 30 includes a first terminal coupled to input terminal N1 and a second terminal coupled to reference terminal N3. Capacitor 32 includes a first terminal coupled between the second terminal of capacitor 24 and the first terminal of the second set of switching devices 26, and a second terminal. The third set of switching devices 34 includes a first terminal coupled to the second terminal of capacitor 32, and a second terminal coupled to reference terminal N3.

[0059] Capacitor 30 may have a capacitance value of b, and capacitor 32 may have a capacitance value of C3. The capacitance value b may be greater than the capacitance values ​​C1 to C3. The capacitance values ​​C1 to C3 may be the same or different. For example, the capacitance value C1 may be a, the capacitance value C2 may be 2a, and the capacitance value C3 may be (2 / 3)a.

[0060] The third set of switching devices 34 includes a third transistor M31. In some embodiments, the third set of switching devices 34 includes third transistors M31 to M3k, where k is the number of third transistors M31 to M3k, and k is a positive integer. The number i of first transistors M11 to M1i and / or the number j of second transistors M21 to M2j may be greater than the number k of third transistors M31 to M3k. In some embodiments, the third set of switching devices 34 can be used to provide a more accurate matching impedance. In other embodiments, the third set of switching devices 34 may be selectively removed from the matching circuit 12 to couple the second terminal of capacitor 32 to the reference terminal N3, thereby further reducing the area of ​​the matching circuit 1. Figure 3 For example, the third set of switching devices 34 includes a third transistor M31. The third set of switching devices 34 can control the coupling between the second terminal of capacitor 32 and the reference terminal N3 according to the switching control signal SW3. The control signal SW3 can be set to an enable level or a disable level. When the control signal SW3 is set to the enable level, the third transistor M31 can be turned on to couple the second terminal of the control capacitor 32 to the reference terminal N3; when the control signal SW3 is set to the disable level, the third transistor M31 can be turned off to isolate the second terminal of capacitor 32 from the reference terminal N3. The third transistor M31, the first transistors M11 to M1i, and the second transistors M21 to M2j can be N-type MOSFETs of the same size. In some embodiments, the third transistor M31, the first transistors M11 to M1i, and the second transistors M21 to M2j can be P-type MOSFETs of the same size.

[0061] Based on the states of the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34, the matching circuit 12 can be set to the third mode, the fourth mode, or the fifth mode, respectively providing the corresponding equivalent capacitance values, as shown in Table 2:

[0062] Table 2

[0063]

[0064] In the third mode, the controller 122 can turn off the first set of switching devices 22, turn off the second set of switching devices 26, and turn on the third set of switching devices 34 to set capacitors 20, 24 and 32 in series, and enable the matching circuit 12 to provide the equivalent capacitance value b+(1 / C1+1 / C2+1 / C3) for the third mode. -1 The equivalent capacitance value of the third mode can be derived from the capacitance values ​​b, C1, C2, and C3. For example, when the capacitance value C1 is a, the capacitance value C2 is 2a, and the capacitance value C3 is (2 / 3)a, the equivalent capacitance value of the third mode can be b + (1 / 3)a.

[0065] In the fourth mode, the controller 122 may turn off the first set of switching devices 22, turn on the second set of switching devices 26, and turn on or off the third set of switching devices 34 to set the capacitors 20 and 24 in series and to make the matching circuit 12 provide an equivalent capacitance value of the fourth mode b+(1 / C1+1 / C2). -1 . The equivalent capacitance value of the fourth mode can be derived based on the capacitance values b, C1, and C2. For example, when the capacitance value C1 is a and the capacitance value C2 is 2a, the equivalent capacitance value of the fourth mode can be b+(2 / 3)a. The equivalent capacitance value (b+(2 / 3)a) of the fourth mode is greater than the equivalent capacitance value (b+(1 / 3)a) of the third mode.

[0066] In the fifth mode, the controller 122 may turn on the first set of switching devices 22, turn on or off the second set of switching devices 26, and turn on or off the third set of switching devices 34 to make the matching circuit 12 provide an equivalent capacitance value of the fifth mode (b+C1). For example, when the capacitance value C1 is a, the equivalent capacitance value of the fifth mode can be (b+a). The equivalent capacitance value (b+a) of the fifth mode is greater than the equivalent capacitance value (b+(2 / 3)a) of the fourth mode. When the first set of switching devices 22 can be turned on, regardless of whether the second set of switching devices 26 and the third set of switching devices 34 are turned on or off, the matching circuit 12 can generate an equivalent capacitance value of (b+a).

[0067] In some embodiments, the capacitance values C1, C2, and C3 are values that decrease in sequence (C1>C2>C3), and the matching circuit 12 can provide a larger equivalent capacitance range than when the capacitance values C1, C2, and C3 increase in sequence (C1<C2<C3). In the case where the capacitance values C1, C2, and C3 decrease in sequence, the equivalent capacitance value of the third mode is less than and closest to the capacitance value C3. In other words, the equivalent capacitance value of the third mode is dominated by the capacitance value C3. In an example, the capacitance value C1 can be 10 pF, the capacitance value C2 can be 4 pF, and the capacitance value C3 can be 1 pF. Then, the equivalent capacitance value of the fifth mode can be 10 pF, the equivalent capacitance value of the fourth mode can be 2.8 pF, and the equivalent capacitance value of the third mode can be 0.74 pF. The matching circuit 12 can provide a range of equivalent capacitance values between 0.74 pF and 10 pF. In contrast, in the case where the capacitance values C1, C2, and C3 increase in sequence, the capacitance value C1 can be 1 pF, the capacitance value C2 can be 4 pF, and the capacitance value C3 can be 10 pF. The matching circuit 12 can only provide a range of equivalent capacitance values between 0.74 and 1 pF.

[0068] The detection signal Sd may correspond to different modes, such as the third mode, the fourth mode, or the fifth mode. The controller 122 may generate a control signal SW3 based on the detection signal Sd and use the control signal SW3 to control the third set of switching devices 34. Similar to Figure 2 Matching circuit 12 in the middle, Figure 3 The matching circuit 12 can be adjusted to different modes according to its electrical characteristics.

[0069] In some embodiments, the detector 120 can detect the frequency of the input signal Srf and generate a detection signal Sd based on the frequency of the input signal Srf. In some embodiments, the controller 122 can select a higher equivalent capacitance value for higher frequencies of the input signal Srf, a medium equivalent capacitance value for intermediate frequencies of the input signal Srf, and a lower equivalent capacitance value for lower frequencies of the input signal Srf. If the detection signal Sd indicates that the frequency of the input signal Srf is below a low-frequency threshold, the controller 122 can control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a third mode. If the detection signal Sd indicates that the frequency of the input signal Srf is between a low-frequency threshold and a high-frequency threshold, the controller 122 can control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a fourth mode. The high-frequency threshold is higher than the low-frequency threshold. If the detected signal Sd indicates that the frequency of the input signal Srf is higher than the high-frequency threshold, the controller 122 can control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in the fifth mode. The equivalent impedance of the matching circuit 12 in the fifth mode is less than that in the fourth mode, and the equivalent impedance of the matching circuit 12 in the fourth mode is less than that in the third mode. Therefore, the operating frequency of the fifth mode is higher than that of the fourth mode, and the operating frequency of the fourth mode is higher than that of the third mode. For example, the operating frequency of the fifth mode can be 5 GHz, the operating frequency of the fourth mode can be 4.5 GHz, and the operating frequency of the third mode can be 4 GHz. The matching circuit 12 can transmit frequency components near the operating frequency of the selected mode and filter out frequency components far from the operating frequency of the selected mode. Therefore, the subsequent circuit 14 does not need to further process the output signal Srf', thereby reducing the circuit complexity of the subsequent circuit 14.

[0070] In other embodiments, the controller 122 may select a higher equivalent capacitance value for lower frequencies of the input signal Srf, a medium equivalent capacitance value for mid frequencies of the input signal Srf, and a lower equivalent capacitance value for higher frequencies of the input signal Srf. If the detection signal Sd indicates that the frequency of the input signal Srf is higher than a higher frequency threshold, the controller 122 may control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a third mode. If the detection signal Sd indicates that the frequency of the input signal Srf is between a high-frequency threshold and a low-frequency threshold, the controller 122 may control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a fourth mode, where the high-frequency threshold is higher than the low-frequency threshold. If the detection signal Sd indicates that the frequency of the input signal Srf is lower than the low-frequency threshold, the controller 122 may control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a fifth mode. Since the impedance (Z) of a capacitor is inversely proportional to the product of its capacitance (C) and the signal frequency (f), i.e., Z = 1 / (j*2πf*C), choosing a higher equivalent capacitance value for high-frequency input signals Srf and a lower equivalent capacitance value for low-frequency input signals Srf ensures that the impedance of the matching circuit 12 remains substantially constant and is independent of the frequency of the input frequency Srf. This is suitable for transmitting wideband input signals Srf between the preamplifier circuit 10 and the cascade circuit 14.

[0071] In some embodiments, the input signal Srf may remain substantially constant in frequency, and the detector 120 may detect the power of the input signal Srf and generate a detection signal Sd based on the power of the input signal Srf. The controller 122 may select a higher equivalent capacitance value for a higher power input signal Srf and a lower equivalent capacitance value for a lower power input signal Srf. If the detection signal Sd indicates that the power of the input signal Srf is below a low power threshold, the controller 122 may control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a third mode. If the detection signal Sd indicates that the power of the input signal Srf is between a low power threshold and a high power threshold, the controller 122 may control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a fourth mode. The high power threshold is higher than the low power threshold. If the detection signal Sd indicates that the power of the input signal Srf is higher than the high power threshold, the controller 122 can control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in the fifth mode. For the higher power of the input signal Srf, the lower equivalent impedance of the fifth mode can provide a stronger attenuation effect on the input signal Srf; for the lower power of the input signal Srf, the higher equivalent impedance of the third mode can provide a weaker attenuation effect on the input signal Srf, thereby keeping the power of the output signal Srf' substantially constant.

[0072] In some embodiments, the input signal Srf may remain substantially constant in frequency, and the detector 120 may detect the phase of the input signal Srf and generate a detection signal Sd based on the phase of the input signal Srf. The controller 122 may select a higher equivalent capacitance value for the leading phase of the input signal Srf and a lower equivalent capacitance value for the lagging phase of the input signal Srf. If the detection signal Sd indicates that the phase of the input signal Srf leads the reference signal by more than a first phase angle, the controller 122 may control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a fifth mode. If the detection signal Sd indicates that the phase of the input signal Srf leads the reference signal by less than a first phase angle or lags the reference signal by less than a second phase angle, the controller 122 may control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a fourth mode. If the detection signal Sd indicates that the phase of the input signal Srf lags behind the reference signal by more than a second phase angle, the controller 122 can control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a third mode. The reference signal can be generated by internal or external circuitry, for example, using an oscillator. For the leading phase of the input signal Srf, the lower equivalent impedance of the fifth mode can cancel the excessive phase lead in the input signal Srf; for the lagging phase of the input signal Srf, the higher equivalent impedance of the third mode can cancel the excessive phase lag in the input signal Srf, thereby keeping the phase of the output signal Srf' substantially constant.

[0073] In some embodiments, the input signal Srf can remain substantially constant in frequency. Detector 120 can detect the output impedance of the preamplifier circuit 10 and generate a detection signal Sd based on the output impedance of the preamplifier circuit 10. Controller 122 can select a higher equivalent capacitance value for the lower output impedance of the preamplifier circuit 10, a medium equivalent capacitance value for the intermediate output impedance of the preamplifier circuit 10, and a lower equivalent capacitance value for the higher output impedance of the preamplifier circuit 10. If the detection signal Sd indicates that the output impedance of the preamplifier circuit 10 is below a low impedance threshold, controller 122 can control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a fifth mode. If the detection signal Sd indicates that the output impedance of the preamplifier circuit 10 is between the low impedance threshold and the high impedance threshold, controller 122 can control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a fourth mode. The high impedance threshold is higher than the low impedance threshold. If the detection signal Sd indicates that the output impedance of the preamplifier circuit 10 is higher than the high impedance threshold, the controller 122 can control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in the third mode. For the lower output impedance (R1) of the preamplifier circuit 10, the higher equivalent capacitance value (Ch) of the matching circuit 12 in the fifth mode can generate the time constant (τ=Rl*Ch) of the matching circuit 12, and for the higher output impedance (Rh) of the preamplifier circuit 10, the lower equivalent impedance value (Cl) of the matching circuit 12 in the third mode can keep the time constant of the matching circuit 12 substantially unchanged (τ=Rh*Cl), thereby keeping the delay of the output signal Srf′ substantially constant.

[0074] In some embodiments, the input signal Srf can remain substantially constant in frequency, and the detector 120 can detect the temperature of the preamplifier circuit 10 and generate a detection signal Sd based on the temperature of the preamplifier circuit 10. The preamplifier circuit 10 can be a power amplifier, and the gain of the power amplifier decreases as the temperature increases, i.e., the higher the temperature, the lower the gain. Therefore, the controller 122 can select a higher equivalent capacitance value for the lower temperature of the preamplifier circuit 10, a medium equivalent capacitance value for the intermediate temperature of the preamplifier circuit 10, and a lower equivalent capacitance value for the higher temperature of the preamplifier circuit 10. If the detection signal Sd indicates that the temperature of the preamplifier circuit 10 is below a low temperature threshold, the controller 122 can control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a fifth mode. If the detection signal Sd indicates that the temperature of the preamplifier circuit 10 is between the low temperature threshold and the high temperature threshold, the controller 122 can control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in a fourth mode. The high-temperature threshold is higher than the low-temperature threshold. If the detection signal Sd indicates that the temperature of the preamplifier circuit 10 is higher than the high-temperature threshold, the controller 122 can control the first set of switching devices 22, the second set of switching devices 26, and the third set of switching devices 34 to operate in the third mode. For the lower temperature of the preamplifier circuit 10, the lower equivalent impedance of the fifth mode can provide a stronger attenuation effect on the input signal Srf; for the higher temperature of the preamplifier circuit 10, the higher equivalent impedance of the third mode can provide a weaker attenuation effect on the input signal Srf, thereby keeping the power of the output signal Srf' substantially constant.

[0075] In some embodiments, the third mode corresponds to the first frequency, the fourth mode corresponds to the second frequency, and the fifth mode corresponds to the third frequency. The third frequency may be different from the second frequency, for example, the third frequency is greater than the second frequency. The second frequency may be different from the first frequency. For example, the first frequency may be 2.3 GHz, the second frequency may be 2.4 GHz, and the third frequency may be 2.5 GHz. When the input signal Srf is 2.3 GHz, the matching circuit 12 may be set to the third mode to perform impedance matching for the 2.3 GHz input signal Srf; when the input signal Srf is 2.4 GHz, the matching circuit 12 may be set to the fourth mode to perform impedance matching for the 2.4 GHz input signal Srf; when the input signal Srf is 2.5 GHz, the matching circuit 12 may be set to the fifth mode to perform impedance matching for the 2.5 GHz input signal Srf. In other embodiments, the operating mode of the matching circuit 12 may also be set according to the output impedance of the preceding stage circuit of the matching circuit 12.

[0076] Although the matching circuit 12 selects from three impedance branches—capacitor 20 and the first set of switching devices 22, capacitor 24 and the second set of switching devices 26, and capacitor 32 and the third set of switching devices 34—to provide three equivalent capacitance values, in other embodiments of the invention, more impedance branches may be included according to the same principle, and more equivalent capacitance values ​​may be provided by selecting from all impedance branches.

[0077] Compared to the method in related technologies that selects from multiple parallel capacitor branches to generate different matching impedances, the total number of transistors (i+j+1) used in the matching circuit 12 is less, thus reducing the transistor size, the area of ​​the matching circuit 12, and / or reducing manufacturing costs.

[0078] Although the matching circuit 12 in the above embodiment is described using capacitors 20, 24, 30 and 32, other impedance components, such as resistors or inductors, may be used instead of capacitors in other embodiments of the present invention. Figure 4 This is a circuit diagram of another matching circuit 12 in an embodiment of the present invention. Figure 4 and Figure 2 The main difference in the matching circuit 12 is that capacitors 20 and 24 are replaced by impedance components 40 and 44, respectively. The matching circuit 12 may include an input terminal N1, an output terminal N2, an impedance component 40, a first set of switching devices 22, an impedance component 44, and a second set of switching devices 26. The input terminal N1 may be coupled to a signal source, and the output terminal N2 may be coupled to a load. The impedance component 40 includes a first terminal coupled between the input terminal N1 and the output terminal N2, and a second terminal. The first set of switching devices 22 includes a first terminal coupled to the second terminal of the impedance component 40, and a second terminal coupled to a reference terminal N3. The reference terminal N3 can provide a reference voltage GND. The impedance component 44 includes a first terminal coupled between the second terminal of the impedance component 40 and the first terminal of the first set of switching devices 22, and a second terminal. The second set of switching devices 26 includes a first terminal coupled to the second terminal of the impedance component 44, and a second terminal coupled to the reference terminal N3. The first set of switching devices 22 includes a plurality of first transistors M11 to M1i connected in series, and the second set of switching devices 26 includes a plurality of second transistors M21 to M2j connected in series. The number i of the plurality of first transistors is different from the number j of the plurality of second transistors. In the first mode, the first set of switching devices 22 is turned off to allow Figure 4 The matching circuit 12 provides a first equivalent matching impedance; in the second mode, the first set of switching devices 22 is turned on to enable... Figure 4 The matching circuit 12 provides a second equivalent matching impedance. The second equivalent matching impedance is different from the first equivalent matching impedance.

[0079] Figure 5 and Figure 3The main difference in the matching circuit 12 is that capacitors 20, 24, 32, and 30 are replaced by impedance components 40, 44, 52, and 50, respectively. Impedance component 50 includes a first terminal coupled to input terminal N1 and a second terminal coupled to reference terminal N3. Impedance component 52 includes a first terminal coupled between the second terminal of impedance component 44 and the first terminal of the second set of switching devices 26, and a second terminal. The third set of switching devices 34 includes a first terminal coupled to the second terminal of impedance component 52, and a second terminal coupled to reference terminal N3. The third set of switching devices 34 includes at least one third transistor M31 or a plurality of third transistors M31 to M3k connected in series, wherein the number i of the plurality of first transistors, the number j of the plurality of second transistors, and the number k of third transistors are all different. In the third mode, the first set of switching devices 22 is turned off, the second set of switching devices 26 is turned off, and the third set of switching devices 34 is turned on to... Figure 5 Matching circuit 12 provides a first equivalent matching impedance; in the fourth mode, the first set of switching devices 22 is turned off and the second set of switching devices 26 is turned on to enable... Figure 5 The matching circuit 12 provides a second equivalent matching impedance. In the fifth mode, the first set of switching devices 22 is turned on to enable... Figure 5 The matching circuit 12 provides a third equivalent matching impedance. The first, second, and third equivalent matching impedances are all different. The impedance component can be, for example, a capacitive component, a resistive component, or an inductive component, or a combination thereof, and can achieve the effects of the aforementioned embodiments.

[0080] Figures 2 to 5 The matching circuit 12 can measure the electrical characteristics of the circuit, provide a suitable impedance based on the electrical characteristics of the circuit, thereby filtering out unwanted frequency components of the input signal Srf, providing broadband transmission, maintaining substantially constant output power, maintaining substantially constant output phase, and / or maintaining substantially constant output delay.

[0081] The above are merely preferred embodiments of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention shall be covered by the present invention.

Claims

1. A matching circuit, characterized in that, Include: One input terminal and one output terminal; A first impedance component includes a first terminal coupled between the input terminal and the output terminal, and a second terminal; A first set of switching devices includes a first terminal coupled to the second terminal of the first resistive component, and a second terminal. Coupled to a reference terminal and a plurality of control terminals; A second impedance component includes a first terminal coupled between the second terminal of the first impedance component and the first terminal of the first set of switching devices, and a second terminal; A second set of switching devices includes a first terminal coupled to the second terminal of the second resistive component, the second terminal... Coupled to the reference terminal and a plurality of control terminals; and A controller is coupled to the control terminals of the first set of switching devices and the control terminals of the second set of switching devices. Used to control the first set of switching devices and the second set of switching devices according to a detection signal corresponding to a first mode or a second mode, thereby adjusting the equivalent impedance of the matching circuit, such that: In this first mode, the matching circuit provides a first equivalent impedance. In this second mode, the matching circuit provides a second equivalent impedance. The second equivalent impedance is different from the first equivalent impedance; The first set of switching devices includes a plurality of first transistors connected in series, and the second set of switching devices includes a plurality of second transistors connected in series. The number of the plurality of first transistors is different from the number of the plurality of second transistors.

2. The matching circuit as described in claim 1, characterized in that, It also includes a detector coupled to the controller for detecting a frequency of an input signal and generating the detection signal based on the frequency of the input signal.

3. The matching circuit as described in claim 1, characterized in that, It also includes a detector coupled to the controller for detecting a power of an input signal and generating the detection signal based on the power of the input signal.

4. The matching circuit as described in claim 1, characterized in that, It also includes a detector coupled to the controller for detecting a phase of an input signal and generating the detection signal based on the phase of the input signal.

5. The matching circuit as described in claim 1, characterized in that, It also includes a detector coupled to the controller for detecting an output impedance of a preamplifier circuit and generating a detection signal based on the output impedance of the preamplifier circuit.

6. The matching circuit as described in claim 1, characterized in that, It also includes a detector coupled to the controller for detecting a temperature of a preamplifier circuit and generating a detection signal based on the temperature of the preamplifier circuit.

7. The matching circuit as described in claim 1, characterized in that, The first impedance component and the second impedance component are capacitors.

8. The matching circuit as described in claim 7, characterized in that, In the first mode, the controller is used to turn off the first set of switching devices so that the matching circuit provides a first equivalent capacitance value; and in the second mode, the controller is used to turn on the first set of switching devices so that the matching circuit provides a second equivalent capacitance value, the second equivalent capacitance value being higher than the first equivalent capacitance value.

9. The matching circuit as described in claim 1, characterized in that, The number of the plurality of first transistors is greater than the number of the plurality of second transistors.

10. The matching circuit as described in claim 1, characterized in that, Also includes: A third impedance component includes a first terminal coupled to the input terminal and a second terminal coupled to the reference terminal.

11. The matching circuit as described in claim 10, characterized in that, The third impedance component is a capacitor.

12. The matching circuit as described in claim 1, characterized in that, It also includes a third impedance component, including a first terminal coupled between the second terminal of the second impedance component and the first terminal of the second set of switching devices, and a second terminal.

13. The matching circuit as described in claim 12, characterized in that, The first impedance component, the second impedance component, and the third impedance component are capacitors.

14. The matching circuit as described in claim 13, characterized in that, in: In a third mode, the first set of switching devices is turned off and the second set of switching devices is turned off so that the matching circuit provides a first equivalent capacitance value; In a fourth mode, the first set of switching devices is turned off and the second set of switching devices is turned on so that the matching circuit provides a second equivalent capacitance value, which is greater than the first equivalent capacitance value; and In a fifth mode, the first set of switching devices is turned on so that the matching circuit provides a third equivalent capacitance value, which is greater than the second equivalent capacitance value.

15. The matching circuit as described in claim 14, characterized in that, in: In the fifth mode, the first set of switching devices is turned on and the second set of switching devices is turned off so that the matching circuit provides the third equivalent capacitance value.

16. The matching circuit as described in claim 14, characterized in that, in: In the fifth mode, the first set of switching devices is turned on and the second set of switching devices is turned on so that the matching circuit provides the third equivalent capacitance value.

17. The matching circuit as described in claim 12, characterized in that, in: The second terminal of the third impedance component is coupled to the reference terminal.

18. The matching circuit as described in claim 12, characterized in that, in: The second terminal of the third impedance component is coupled to a third set of switching devices.

19. The matching circuit as described in claim 18, characterized in that, The first set of switching devices includes a plurality of first transistors connected in series, the second set of switching devices includes a plurality of second transistors connected in series, and the third set of switching devices includes at least one third transistor, wherein the number of the plurality of first transistors or the number of the plurality of second transistors is greater than the number of the at least one third transistor.

20. The matching circuit as described in claim 18, characterized in that, The first set of switching devices includes a plurality of first transistors connected in series, the second set of switching devices includes a plurality of second transistors connected in series, and the third set of switching devices includes at least one third transistor, wherein the number of the plurality of first transistors and the number of the plurality of second transistors are both greater than the number of the at least one third transistor.

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