Method of manufacturing a semiconductor chip with sidewall seal

Abstract

A method of manufacturing a semiconductor chip having a sidewall seal is described. The method includes forming a dicing groove in a semiconductor wafer. The sidewalls of the dicing groove are anodized to generate an anodized layer at the sidewalls of the dicing groove. The semiconductor chip is separated from the semiconductor wafer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor chip manufacturing, and in particular to sidewall sealing of semiconductor chips. BACKGROUND

[0002] During and after separating a semiconductor chip from a semiconductor wafer, the sidewall of the semiconductor chip is susceptible to mechanical and chemical damage. In particular, metal plating and / or soldering processes applied after chip separation, for example during packaging, can negatively affect chip sidewall integrity and can for example lead to chip breakage. SUMMARY

[0003] According to an aspect of the present disclosure, a method of manufacturing a semiconductor chip having a sidewall seal comprises forming a dicing trench in a semiconductor wafer. The sidewall of the dicing trench is anodized to generate an anodization layer at the sidewall of the dicing trench. The semiconductor chip is separated from the semiconductor wafer.

[0004] According to an aspect of the present disclosure, a semiconductor chip comprises an anodization layer at its sidewall. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 is a flowchart schematically illustrating an exemplary method of manufacturing a semiconductor chip having an anodization layer as a sidewall seal.

[0006] Figure 2 is a schematic diagram of a process of anodizing the sidewall of a dicing trench to generate an anodization layer at the sidewall.

[0007] Figure 3 is a schematic diagram of a metal-oxide-semiconductor (MOS) structure during anodization for n-type semiconductors (left side) and p-type semiconductors (right side), taking into account: (a) space-charge zone (SCZ), (b) space-charge density p, (c) charge carrier concentrations N of negative and positive charge carriers (i.e. Nn for electrons and Np for holes), and (d) electric field E.

[0008] Figure 4 is a schematic diagram of a process of implanting n-type dopants or p-type dopants into the sidewall of a dicing trench prior to anodization.

[0009] Figure 5 is a schematic diagram of a process of irradiating the sidewall of a dicing trench during anodization.

[0010] Figure 6 is a schematic diagram of a process of irradiating the sidewall of a dicing trench during anodization.

[0011] Figure 7 isFigure 6 Enlarged view of the circled detail.

[0012] Figure 8 is a cross-sectional view of an exemplary semiconductor chip having an anodization layer at its sidewalls.

[0013] Figure 9 is a cross-sectional view of an exemplary semiconductor chip having an anodization layer at its sidewalls and having a solder deposit(ies) over its main surface(s). DETAILED DESCRIPTION

[0014] It is to be understood that features of the various exemplary embodiments and examples described herein can be combined with each other, unless specifically noted otherwise.

[0015] Wafer dicing is the process of dividing a semiconductor wafer into chips, which are also referred to as dies in the art. Various techniques have been developed for wafer dicing. In particular, the fabrication of thin chips for power applications, e.g. of semiconductor wafers, is a challenging task. Conventional dicing methods often result in unprotected chip edges and can further cause defects at the edges (sidewalls) of the separated chips.

[0016] Reference is made to Figure 1 A method of fabricating a semiconductor chip having sidewall sealing is described by way of example. At S1, a dicing trench is formed in a semiconductor wafer. The dicing trench can be formed mechanically, e.g. by blade dicing, chemically, e.g. by etching and / or by laser beam ablation, for example.

[0017] At S2, the sidewalls of the dicing trench are anodized to generate an anodization layer at the sidewalls of the dicing trench. The anodization of the sidewalls results in a sidewall sealing. As will be further described below, the sidewall sealing resulting from this electrochemical process is of high quality in terms of uniformity, consistency and sealing capability.

[0018] At S3, the semiconductor chip is separated from the semiconductor wafer. Separating the semiconductor chip from the semiconductor wafer can involve various different techniques, including thinning, laser separation, etc., for example.

[0019] Reference is made to Figure 2 The process of anodizing the sidewalls of the dicing trench at S2 is described in more detail by way of example. In Figure 2 The semiconductor wafer 210 (only a portion of which is shown) is immersed in an electrolyte 250 contained in an electrolytic cell 260. The electrolytic cell 260 further contains a cathode 262 (negative electrode) and an anode 264 (positive electrode), where the semiconductor wafer 210 acts as the anode 264. Figure 2 ​

[0020] As already mentioned, prior to performing the anodization process, a dicing trench 220 has been formed in the semiconductor wafer 210. The dicing trench 220 can have a depth D (measured between the upper surface 210A of the semiconductor wafer 210 and the bottom surface 220A of the dicing trench 220) equal to or smaller than 50 pm, 70 pm, 90 pm, 1 10 pm, 130 pm or 150 pm. In particular, D can be equal to or larger than the thickness of a semiconductor chip to be produced from the semiconductor wafer 210.

[0021] The semiconductor wafer 210 can be front-end processed, i.e. integrated circuits (not shown) can be monolithically integrated in each semiconductor wafer region delimited by the dicing trench 220. The integrated circuits (ICs) can represent power ICs. In particular, the ICs can comprise or represent power transistors, power diodes, etc.

[0022] For example, electrodes such as gate electrodes 212 and / or source electrodes 214 can be arranged at the upper surface 210A of the semiconductor wafer 210. Note that the gate electrodes 212 and source electrodes 214 depicted in Figure 2 are merely examples and other electrodes such as one and / or more drain electrodes of a logic or analog IC can be provided at the upper surface 210A of the semiconductor wafer 210.

[0023] In the example shown in Figure 2 the electrodes (e.g. gate electrodes 212 and source electrodes 214) are covered by a masking material 218, e.g. photoresist.

[0024] The masking material 218 can cover surface regions of the semiconductor wafer 210 which are not intended to be exposed to the electrochemical anodization process. In the example shown in Figure 2 the masking material 218 completely covers the upper surface 210A of the semiconductor wafer 210 laterally outside of the dicing trench 220 and can completely cover the electrodes (e.g. gate electrodes 212 and source electrodes 214) at the upper surface 210A of the semiconductor wafer 210. However, as will be described in more detail below, the masking material 218 layer can also terminate at a certain offset from the rim of the dicing trench 220 in order to provide a frame-shaped exposed region at the upper surface 210A of the semiconductor wafer 210 adjacent to the rim of the dicing trench 220.

[0025] In addition to covering the upper surface 210A and the electrodes during the anodization process, the mask material 218 can have one or more additional functions. According to a first possibility, a mask layer of the mask material 218 can be generated on top of the semiconductor wafer 210 before the dicing trenches 220 are formed. The mask layer can then be patterned to expose the dicing lanes on the semiconductor wafer 210. The patterned mask layer can then be used to form the dicing trenches 220 by plasma dicing. In this case, the patterned mask layer can also act as a dicing mask.

[0026] For example, the plasma dicing can be performed by deep reactive ion etching (DRIE). DRIE is a dry plasma process that can etch very narrow, deep, vertical dicing trenches 220 into the semiconductor wafer 210.

[0027] According to a second possibility, a mask layer of the mask material 218 can be generated on top of the semiconductor wafer 210 after the dicing trenches 220 are formed. The mask layer can then be patterned to at least expose the dicing trenches 220. As mentioned above, the mask layer can also be patterned to additionally expose a frame-shaped region of the upper surface 210A of the semiconductor wafer that is adjacent to the dicing trenches 220. The patterned mask layer is then used to anodize all exposed surfaces of the semiconductor wafer 210 that are not covered by the patterned mask layer. That is, the sidewalls of the dicing trenches 220 and, optionally, the frame-shaped region adjacent to the dicing trenches 220 are anodized by using the patterned mask layer.

[0028] Returning to Figure 2 The dicing trenches 220, which can have been produced, for example, by a half- blade dicing or plasma dicing, are then anodized to generate an anodization layer 222. The anodization layer 222 can partially or completely cover the sidewalls of the dicing trenches 220.

[0029] The anodization layer 222 is generated by anodization of the wafer material. The wafer material can be, for example, silicon (Si) or other materials such as SiGe, SiC, etc. In the following, without loss of generality and merely for ease of explanation, Si is used as an example of a semiconductor wafer material.

[0030] During anodization, the Si-Si bonds of the Si semiconductor wafer 210 are broken and replaced by Si-O bonds. The following chemical equation can describe the anodization of Si:

[0031] Si + 2H2O + nh→ SiO2+ 4H + + (4-n)e,

[0032] where h denotes a hole, e denotes an electron, and n is an integer.

[0033] That is, the direct current applied between the cathode 262 and the anode 264 passes through the electrolyte 250 and releases hydrogen at the cathode 262 and oxygen at the exposed upper surface 210A of the semiconductor wafer 210, i.e. at the anode 264. The oxygen builds up an accumulation of silicon oxide, i.e. the anodic oxide layer 222. Moreover, from the chemical equation, the anodization is a hole-driven process.

[0034] The electrolyte 250 comprises water, i.e. is an aqueous solution. In an aqueous solution, the anodization process is less dependent on the salt dissolved in the electrolyte 250. Thus, a variety of different electrolytes 250 can be used, in particular deionized water, HNO3, H3PO4, NH4OH, etc.

[0035] It is noted that the anodic oxide layer 222 generated by electrochemical anodization is structurally different from a semiconductor oxide layer generated by a deposition process, e.g. by silane cracking, TEOS (tetraethyl orthosilicate) deposition, or LTO (low temperature oxide) deposition. The anodic oxide has a higher density than a deposited oxide. Moreover, the generation process is self-adjusting and highly conformal. This guarantees that the exposed surface of the semiconductor wafer 210, and in particular the sidewalls of the dicing trenches 220, are completely and hermetically sealed, without any defects or weak spots in the anodic oxide layer 222. In short, the anodic oxide layer 222 is structurally different and of better quality compared to a deposited oxide layer.

[0036] Moreover, it is noted that a high-temperature oxide generation process cannot be used to seal the sidewalls of the dicing trenches 220, because the semiconductor wafer 210 cannot be heated to high temperatures anymore in the later stages of wafer processing, i.e. after wafer metallization.

[0037] Another advantage of the anodic oxide over a deposited oxide is that the anodic oxide is generated selectively, whereas the deposited oxide completely coats the semiconductor wafer 210.

[0038] Figure 3 The properties of the generation of the anodic oxide layer 222 in the electrolytic cell 260 are schematically shown. Figure 3 The left-hand graph in Fig. 2 relates to an n-type semiconductor wafer 210, whereas the right-hand graph relates to a p-type semiconductor wafer 210. With reference to the n-type semiconductor wafer 210, it is assumed that the semiconductor wafer 210 does not have a very high dopant concentration, e.g. equal to or less than about 10 18 cm -3 or 10 19 cm -3 After the initial layer thickness of a few nanometers of the anodic oxide layer 222 is generated, a space charge zone (SCZ) is generated in the n-type semiconductor wafer 210 (see Fig. 2, left-hand graph). The SCZ is a region in the semiconductor wafer 210 where the electric field is zero. The SCZ is generated because the n-type semiconductor wafer 210 is not sufficiently doped to sustain the electric field. The SCZ is a region of high electric field in the p-type semiconductor wafer 210 (see Fig. 2, right-hand graph). Figure 3of the left-hand part of (a) and (b) of Fig. 1 1, the space charge zone (SCZ) suppresses further oxidation even if the voltage is increased. However, only when the breakdown voltage is reached, more anodic oxide is generated by an uncontrolled process. Thus, unlike the case of a p-type semiconductor wafer 210 where almost no SCZ is formed at the initial anodic oxide layer generation (see Figure 3 the right-hand part of (a) and (b) of Fig. 1 1, it is difficult to create an anodic oxide layer 222 of greater thickness by anodization in an n-type semiconductor wafer 210 having a dopant concentration of, for example, equal to or less than about 10 18 cm -3 or 10 19 cm -3 .

[0039] The electrochemically generated anodic oxide acts as an insulator between the applied voltages. During the anodization process, the thinner the anodic oxide layer 222 at a particular location, the higher the electric field E at that location. As a result, the thinner regions of the anodic oxide layer 222 are anodized more strongly, since the process is governed by the field-driven ion motion. This self-adjustment of the anodization process provides a high degree of consistency (e.g., in terms of thickness and / or structure) of the generated anodic oxide layer 222, which is even better than the consistency of thermal oxides generated by diffusion-controlled reactions.

[0040] A method of creating a thicker anodic oxide layer 222 in an n-type semiconductor wafer 210 without very high dopant concentrations is described below.

[0041] According to a first method, the anodic oxide layer formation process can be boosted by implanting n-type or p-type dopants into the sidewalls of the dicing trenches 220 prior to anodization. This method is shown in Figure 4 . The arrows indicate a shallow implant of donors (e.g., phosphorus, arsenic, antimony, etc.) into the sidewalls of the dicing trenches 220. The dopants suppress the formation of a SCZ, thus allowing further anodic oxide growth. Acceptors such as boron can also be used as p-type dopants.

[0042] Since it is no longer possible to activate the dopants at high temperatures, the concentration of the dopants (i.e., the implant dose) should be relatively high.

[0043] Alternatively or additionally, thermal donors can be induced by hydrogen implantation. The advantage of thermal donors is that a temperature of only about 400°C is sufficient for activation. Such temperatures are compatible with wafer processing at the wafer manufacturing stage, in particular with the front-side metallization (electrodes 212, 214) that can already be applied to the semiconductor wafer 210. Thus, the annealing process after the hydrogen implantation (also indicated by the arrows of Fig. 12) can be performed at a suitable temperature of, for example, about 400°C. Figure 4 ​

[0044] As Figure 4 illustrated, the mask material 218 (which can or can not have been used for the trench cut previously) can be used as an implant mask for one or more of the implantation processes described above. The thickness of the mask layer of the mask material 218 can be equal to or larger than several tens of pm. Such a mask layer thickness is sufficient for plasma cutting and also sufficient to act as an implant mask layer during the implantation processes.

[0045] Implanting n-type dopants or p-type dopants or hydrogen into the sidewalls of the cut trench 220 can not only allow for further anodization layer generation, but can also additionally serve as a field stop region for the edge of the semiconductor chip. As is known in the art, semiconductor chips and in particular power semiconductor chips are equipped with a field stop region to prevent the generation of electric fields at the chip edge. Thus, the mask layer of the mask material 218 can also be used as an implant mask for generating a lateral field stop region, avoiding the application of a separate mask and further lithography for generating the field stop region.

[0046] According to a second approach, the generation of SCZs in the n-type semiconductor wafer 210 can be suppressed by illuminating the sidewalls of the cut trench 220 during anodization. In the n-type semiconductor wafer 210, the oxidation rate will be sensitive to illumination, as holes are the minority carriers. When a p-type semiconductor wafer 210 is used, the illumination does not affect the oxidation rate.

[0047] Referring to Figure 5 , one or more light sources 510 can be accommodated in the electrolytic cell 260. The light source(s) are configured to fully illuminate the sidewalls of the cut trench 220, thereby generating electron-hole pairs in the region of the semiconductor wafer 210 adjacent to the sidewalls. The electron-hole pairs are generated from the photons emitted by the light source(s) and have the effect that the electric field E is not depleted by SCZs (as compared to the left side drawing (d) of Figure 3 , where the electric field E is depleted by SCZs without illumination). This allows for the generation of an anodization layer 222 in an n-type doped semiconductor material with a limited dopant concentration having a similar thickness as a p-type semiconductor material or a very highly doped n-type semiconductor material.

[0048] The light source(s) 510 can be arranged below the upper surface 210A of the semiconductor wafer 210 at a short distance. The light source(s) 510 can be implemented, for example, by a diode array or any other light emitting device, for example by a light emitting foil or by a light emitting device array.

[0049] In Figure 5In particular embodiments, the light source(s) 510 are located between the cathode 262 and the semiconductor wafer 210. However, the light source(s) 510 can also be arranged above the cathode 262, which can then be transparent (e.g. can be formed by a transparent conductive foil or by a conductive mesh).

[0050] Although described with respect to examples of n-type semiconductor wafers 210 that do not have a very high dopant concentration, the first and second methods can be applied, e.g. generally, to all semiconductor wafers.

[0051] Furthermore, it has been found that an anodization layer 222 of sufficient thickness can be formed on a damaged surface of a semiconductor wafer 210, e.g. on a silicon surface that was damaged during a wafer cutting process by, e.g., a blade cut to produce the cutting groove 220. In this case, no implantation and / or irradiation process is required to generate an anodization layer 222 of sufficient thickness. Even for an undoped (i.e. intrinsic) semiconductor wafer 210, it is possible to generate an anodization layer 222 of sufficient thickness on a damaged surface. In all cases, the blade cut (to produce a damaged groove sidewall) can be combined with the above-described implantation and / or irradiation process.

[0052] Furthermore, it has been found that, for all anodization processes described herein, the temperature during the anodization process plays an important role for the structural quality of the generated anodization layer 222. At temperatures of the electrolyte 250 equal to or higher than 70°C or 80°C or 90°C, the anodization process provides a completely closed and sealed anodization layer 222 that allows for a high quality sidewall sealing, whereas the anodization layer 222 can become increasingly porous at electrolyte temperatures below 70°C.

[0053] Throughout this specification, the anodization layer 222 can have a thickness equal to or greater than 5 nm, 10 nm, 20 nm, 50 nm, 100 nm, 0.5 pm, 1.0 pm or 2.0 pm. The anodization layer 222 can comprise or have a SiO2or another oxide composition generated by anodization of the semiconductor bulk material of the semiconductor wafer 210 at the sidewall of the cutting groove 220.

[0054] Figure 6 Exemplary processes in a method that can be used to manufacture a semiconductor die with an anodization layer 222 as a sidewall seal are shown. At 610, a so-called half-cut cut (e.g. a blade cut or a plasma cut) is performed. At 620, an implantation and / or irradiation process is performed. At 630, an anodization process is performed. Figure 6 The cutting groove 220 and optional electrode(s) 212, 214 are depicted in particular embodiments.

[0055] Subsequently, at 620, the sidewalls of the dicing trenches 220 are anodized. To build the anodized oxide layer 222, any of the above-described processes can be used. Briefly, at 620_1, a semi-cut semiconductor wafer 210 is shown (as already shown at 610). At 620_2, a mask layer of the masking material 218 is generated over the semiconductor wafer 210, which is then patterned to expose the dicing trenches 220. At 620_3, the sidewalls of the dicing trenches 220 are anodized, and the anodized oxide layer 222 is formed at the sidewalls of the dicing trenches 220. Any of the above-described methods can be used. Further to 620_3, the masking material 218 can then be removed. Figure 6 In the example shown, not only the dicing trenches 220 are exposed, but also a certain frame-like surface area of the semiconductor wafer 210 adjacent to the dicing trenches 220 is exposed. The patterned mask layer can completely cover the electrode(s) 212, 214 (or, in general, the metallization) on the semiconductor wafer 210. The process shown at 620_2 can also be referred to as “cut-on lithography”. As mentioned above, the patterned mask layer of the masking material 218 can further serve as an implantation mask.

[0056] At 620_3, the sidewalls of the dicing trenches 220 are anodized, and the anodized oxide layer 222 is formed at the sidewalls of the dicing trenches 220. Any of the above-described methods can be used. Further to 620_3, the masking material 218 can then be removed.

[0057] It is noted that the exemplary processes 620_1, 620_2, 620_3 shown at 620 can be replaced or supplemented by any of the aforementioned processes and variations thereof to achieve a semiconductor wafer 210 with dicing trenches 220 having sidewalls coated by a low-temperature anodized oxide layer 222.

[0058] At 630, the dicing trenches 220 are (optionally) filled with an organic resin 632. The organic resin 632 can form a continuous layer covering the upper surface 210A of the semiconductor wafer 210. If desired, a lithography process can be performed on the organic resin 632 layer after filling the dicing trenches 220 with the organic resin 632.

[0059] At 640, the semiconductor wafer 210 can be attached to a temporary carrier 642. The temporary carrier 642 can for example comprise a holder or support member 642_1 (e.g. a glass plate) and an adhesive film 642_2.

[0060] The temporary carrier 642 with the attached semiconductor wafer 210 can then be flipped upside down. At 650, the semiconductor wafer 210 can be thinned at the semiconductor wafer surface 210B opposite the dicing trenches 220, i.e. thinning can be performed from the backside of the semiconductor wafer 210. Thinning can include grinding and / or etching. The thinning process is illustrated by the arrow at 650. As a result of the thinning process, dies embedded in an organic resin matrix are generated. That is, the thinning process can completely separate the semiconductor wafer 210 into individual semiconductor dies, however, these semiconductor dies are still connected to each other by the organic resin matrix.

[0061] The process from 610 to 650 can be referred to as a die before grind (DBG) process.

[0062] At 660, an electrode metal material 662 can be deposited on the backside of the semiconductor wafer 210 (however, now also referred to as an artificial wafer, since it can comprise separated semiconductor dies embedded in an organic resin matrix). The deposition of the electrode metal material 662 can be performed by electroless plating or galvanic plating. By way of example, a Ti / Cu seed layer 661 can be applied to the surface of the (artificial) semiconductor wafer 210 and copper or any other electrode metal can be deposited on the seed layer 661 to provide the electrode metal material 662 layer.

[0063] At 670, the electrode metal material 662 layer can be structured. Structuring can be done by any available process, for example by etching.

[0064] It is noted that the exemplary steps shown at 660 and 670 can be replaced or supplemented by other method steps, for example, depositing a solder material on top of the (artificial) semiconductor wafer 210. In this case, the solder material can be deposited (e.g. printed) directly on the backside of the (artificial) semiconductor wafer 210 to form a patterned electrode metal material layer as shown at 670. For example, a solder material configured for diffusion soldering can be used, for example, AuSn or other solder materials.

[0065] During the application of the electrode metal material 662 and / or the solder material at 660, 670, the sidewalls of the dicing trenches 220 are not only protected by the (optional) organic resin 632, but also by the anodic oxide layer 222. While the organic resin 632 typically does not provide a reliable protection of the sidewalls of the dicing trenches 220, an effective sidewall sealing is obtained by the anodic oxide layer 222. Thus, the risk of contaminating the sidewalls of the semiconductor dies by metal, for example solder, during or after the die manufacturing process is greatly reduced or completely excluded.

[0066] The temporary carrier 642 can then be removed from the (artificial) semiconductor wafer 210. The (artificial) semiconductor wafer 210 can be flipped upside down and placed on a support member 684. A laser beam 682 can be used to separate the (artificial) semiconductor wafer 210 into individual semiconductor chips by organic resin laser separation. At 680, the left-hand fill of organic resin 632 is shown as being separated by the laser beam 682, while the right-hand fill of organic resin 632 remains intact.

[0067] Figure 7 is Figure 6 an enlarged view of the detail circled at 680 in Figure 7 It is apparent from

[0068] Referring to Figure 8 , the exemplary semiconductor chip 800 includes an anodization layer 222 at its sidewalls. The semiconductor chip 800 can be provided with a backside electrode formed of electrode metal material 662 and / or with frontside electrodes (e.g., gate electrodes 212 and / or source electrodes 214). The thickness T of the anodization layer 222 can be equal to or greater than 5 nm, 10 nm, 20 nm, 50 nm, 100 nm, 0.5 pm, 1.0 pm, or 2.0 pm. The thickness D of the semiconductor chip 800 can be equal to or less than 150 pm, 130 pm, 110 pm, 90 pm, 70 pm, or 50 pm. The semiconductor chip 800 can be a power semiconductor chip, such as a power transistor or a power diode.

[0069] As shown in Figure 8 , the anodization layer 222 can completely cover the entire surface of the sidewalls of the semiconductor chip 800.

[0070] Referring to Figure 9 , the semiconductor chip 900 can be designed the same as the semiconductor chip 800, except that the semiconductor chip 900 is provided with regions 910 adjacent to the sidewalls of the semiconductor chip 900, which are n-doped or p-doped. As previously described, in the case of an n-type semiconductor wafer that does not have a very high dopant concentration, n-type dopant implantation and / or p-type dopant implantation at the sidewalls of the semiconductor chip 900 can provide a sufficient thickness T of the anodization layer 222, and can optionally further serve as a field stop for device fabrication. The regions 910 can also be intrinsic and damaged by blade dicing.

[0071] Furthermore, Figure 9Deposition of solder material 920 is shown over the backside and / or frontside of semiconductor chip 900. During this process or a subsequent process such as solder reflow, the sidewalls of semiconductor chip 920 are effectively sealed to prevent solder material contamination.

[0072] The following examples pertain to further aspects of the present disclosure.

[0073] Example 1 is a method of fabricating a semiconductor chip with sidewall sealing, the method comprising: forming a dicing trench in a semiconductor wafer; anodizing sidewalls of the dicing trench to generate an anodized layer at the sidewalls of the dicing trench; and separating the semiconductor chip from the semiconductor wafer.

[0074] In Example 2, the subject matter of Example 1 can optionally include implanting an n-type dopant or a p-type dopant into the sidewalls of the dicing trench prior to the anodizing.

[0075] In Example 3, the subject matter of Example 1 or 2 can optionally include implanting hydrogen into the sidewalls of the dicing trench prior to the anodizing.

[0076] In Example 4, the subject matter of any of the preceding examples can optionally include irradiating the sidewalls of the dicing trench during the anodizing.

[0077] In Example 5, the subject matter of any of the preceding examples can optionally include: wherein a temperature of the electrolyte during the anodizing is equal to or greater than 70 °C or 80 °C or 90 °C.

[0078] In Example 6, the subject matter of any of the preceding examples can optionally include: wherein the separating comprises thinning the semiconductor wafer after the anodizing at a surface of the semiconductor wafer opposite the dicing trench.

[0079] In Example 7, the subject matter of any of the preceding examples can optionally further include filling the dicing trench with an organic resin after the anodizing.

[0080] In Example 8, the subject matter of any of the preceding examples can optionally further include: wherein the separating comprises singulating the semiconductor chip by laser cutting through the organic resin.

[0081] In Example 9, the subject matter of any of the preceding examples can optionally include depositing an electrode metal material or a solder material over the semiconductor wafer after the anodizing.

[0082] In Example 10, the subject matter of any of the preceding examples can optionally include: wherein forming the dicing trench comprises blade dicing or plasma dicing.

[0083] In Example 11, the subject matter of any of the preceding Examples can optionally include generating a mask layer over the semiconductor wafer after forming the dicing streets; patterning the mask layer to expose the dicing streets; and anodizing sidewalls of the dicing streets using the patterned mask layer.

[0084] In Example 12, the subject matter of any of Examples 1-9 can optionally include generating a mask layer over the semiconductor wafer before forming the dicing streets; patterning the mask layer to expose the dicing street lanes of the semiconductor wafer; forming the dicing streets by plasma dicing using the patterned mask layer; and anodizing sidewalls of the dicing streets using the patterned mask layer.

[0085] Example 13 is a semiconductor chip comprising an anodized oxide layer at sidewalls thereof.

[0086] In Example 14, the subject matter of Example 13 can optionally include wherein the anodized oxide layer completely covers an entire surface of the sidewalls of the semiconductor chip.

[0087] In Example 15, the subject matter of Example 13 or 14 can optionally include wherein a thickness of the anodized oxide layer is equal to or greater than 5 nm, 10 nm, 20 nm, 50 nm, 100 nm, 0.5 pm, 1.0 pm, or 2.0 pm.

[0088] In Example 16, the subject matter of any of Examples 13-15 can optionally include wherein a region of the semiconductor chip adjacent to the sidewalls is n-doped or p-doped or is intrinsic and is damaged by the blade dicing.

[0089] While the application has been described with reference to illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the application, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims

1. A method for manufacturing a semiconductor chip with sidewall sealing, the method comprising: To form dicing grooves in a semiconductor wafer; After the cleavage is formed and before anodizing, an n-type dopant or a p-type dopant is injected into the sidewall of the cleavage. The sidewall of the cutting groove is anodized to form an anodic oxide layer on the sidewall of the cutting groove, wherein the temperature of the electrolyte is equal to or higher than 70°C during anodizing, and the sidewall of the cutting groove is irradiated during anodizing. as well as Separate the semiconductor chip from the semiconductor wafer.

2. The method according to claim 1, further comprising: Hydrogen is injected into the sidewall of the cutting groove prior to anodizing.

3. The method according to claim 1, wherein, The temperature of the electrolyte during anodizing is equal to or higher than 80°C or 90°C.

4. The method according to claim 1, wherein, Separation includes: After anodizing the semiconductor wafer surface opposite the dicing groove, the semiconductor wafer is thinned.

5. The method according to claim 1, further comprising: The cutting groove is filled with organic resin after anodizing.

6. The method according to claim 5, wherein, Separation includes: The semiconductor chip is individualized by laser cutting through the organic resin.

7. The method according to any one of claims 1 to 6, further comprising: Electrode metal material or solder material is deposited on the semiconductor wafer after anodizing.

8. The method according to any one of claims 1 to 6, wherein, The cutting groove is formed by blade cutting or plasma cutting.

9. The method according to any one of claims 1 to 6, further comprising: After the dicing grooves are formed, a mask layer is generated on the semiconductor wafer; Pattern the mask layer to expose the cut groove; as well as The sidewalls of the cut groove are anodized using a patterned mask layer.

10. The method according to any one of claims 1 to 6, further comprising: Before forming the dicing groove, a mask layer is formed on the semiconductor wafer; Pattern the mask layer to expose the dicing channels of the semiconductor wafer; The cutting groove is formed by plasma cutting using a patterned mask layer; as well as The sidewalls of the cut groove are anodized using the patterned mask layer.

11. The method according to any one of claims 1 to 6, wherein, The anodic oxide layer completely covers the entire surface of the sidewalls of the semiconductor chip.

12. The method according to any one of claims 1 to 6, wherein, The thickness of the anodic oxide layer is equal to or greater than 5 nm, 10 nm, 20 nm, 50 nm, 100 nm, 0.5 μm, 1.0 μm or 2.0 μm.

13. The method according to claim 11, wherein, The region of the semiconductor chip adjacent to the sidewall of the semiconductor chip is n-type doped or p-type doped, or intrinsic, and is damaged by cutting with a blade.

Images