Camera device

Abstract

A camera device is provided, which includes: a first semiconductor substrate of a first conductivity type, which includes a first surface and a second surface on the opposite side of the first surface; a photoelectric conversion unit of a second conductivity type, which is embedded in the first surface of the first semiconductor substrate and generates a charge corresponding to the amount of received light through photoelectric conversion; a first charge storage unit and a second charge storage unit, both of which are of the second conductivity type, which are embedded in parallel in the second surface of the first semiconductor substrate and store the charge generated in the photoelectric conversion unit; a first charge transfer unit, which transfers the charge from the photoelectric conversion unit to the first charge storage unit; and a second charge transfer unit, which transfers the charge from the photoelectric conversion unit to the second charge storage unit.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims the benefit of Japanese Priority Patent Application JP 2019-207287 filed on Nov. 15, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to an image pickup device that captures an image by performing photoelectric conversion. Background Art

[0004] So far, solid-state image sensors that realize global shutter by providing a charge holding unit (storage unit) between a photoelectric conversion unit and a floating diffusion have been proposed. For example, Patent Document 1 discloses an image pickup device in which two holding units are provided in a unit pixel, wherein the image pickup device realizes storage of signal charge for a long time by performing charge transfer from the photoelectric conversion unit to the holding unit multiple times for each holding unit during an exposure period. For example, Patent Document 2 discloses an image sensor in which two or more charge storage units are provided for a single photoelectric conversion unit, wherein the image sensor is capable of capturing a high dynamic range image by repeatedly transferring charge at different exposure times.

[0005] [Citation list]

[0006] [Patent Document]

[0007] [Patent Document 1]: JP 2017-220896A

[0008] [Patent Document 2]: JP 2016-574723A Summary of the invention

[0009] [Technical issues]

[0010] On the other hand, in an image pickup device, a larger saturation charge and improved sensitivity are required.

[0011] It is desirable to provide an image pickup device capable of having a large saturation charge and also having improved sensitivity.

[0012] [Technical solution to the problem]

[0013] According to one embodiment of the present disclosure, there is provided an imaging device, which includes: a first semiconductor substrate of a first conductivity type, which includes a first surface and a second surface on an opposite side of the first surface; a photoelectric conversion unit of a second conductivity type, which is embedded in the first surface of the first semiconductor substrate and generates a charge corresponding to the amount of received light through photoelectric conversion; a first charge storage unit and a second charge storage unit, both of which are of the second conductivity type, which are embedded in parallel in the second surface of the first semiconductor substrate and store the charge generated in the photoelectric conversion unit; a first charge transfer unit, which transfers the charge from the photoelectric conversion unit to the first charge storage unit; and a second charge transfer unit, which transfers the charge from the photoelectric conversion unit to the second charge storage unit.

[0014] In an image pickup device according to an embodiment of the present disclosure, two charge storage units (a first charge storage unit and a second charge storage unit) are provided for a single photoelectric conversion unit, the photoelectric conversion unit is arranged on a first surface of a semiconductor substrate, and the two charge storage units are arranged on a second surface of the semiconductor substrate. With this arrangement, the area of ​​the photoelectric conversion unit and the two charge storage units within a sensor pixel is expanded. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] [ Figure 1A ] Figure 1A : is a block diagram showing an exemplary functional configuration of the image pickup apparatus according to the first embodiment of the present disclosure.

[0016] [ Figure 1B ] Figure 1B is a block diagram showing an exemplary functional configuration of an image pickup apparatus as a first modification of the first embodiment.

[0017] [ Figure 1C ] Figure 1C is a block diagram showing an exemplary functional configuration of an image pickup apparatus as a second modification of the first embodiment.

[0018] [ Figure 2 ] Figure 2 It shows Figure 1A A schematic cross-sectional view of an example of the configuration of the imaging device shown.

[0019] [ Figure 3 ] Figure 3 It shows Figure 1A Schematic plan view of an example of the configuration of a sensor pixel in the imaging device shown.

[0020] [ Figure 4 ] Figure 4 It shows Figure 1AA circuit diagram showing the circuit configuration of the imaging device.

[0021] [ Figure 5 ] Figure 5 It shows Figure 1A A timing chart showing an example of the operation of the imaging device shown.

[0022] [ Figure 6 ] Figure 6 : is a schematic cross-sectional view showing a configuration example of an image pickup device according to a second embodiment of the present disclosure.

[0023] [ Figure 7 ] Figure 7 It shows Figure 6 Schematic plan view of an example of the configuration of a sensor pixel in the imaging device shown.

[0024] [ Figure 8 ] Figure 8 : is a schematic cross-sectional view showing a configuration example of an image pickup device according to Modification 1 of the present disclosure.

[0025] [ Fig. 9 ] Fig. 9 It shows Figure 8 Schematic plan view of an example of the configuration of a sensor pixel in the imaging device shown.

[0026] [ Fig.10 ] Fig.10 : is a schematic cross-sectional view showing a configuration example of an image pickup device according to Modification 2 of the present disclosure.

[0027] [ Fig.11 ] Fig.11 It shows Fig.10 Schematic plan view of an example of the configuration of a sensor pixel in the imaging device shown.

[0028] [ Fig.12 ] Fig.12 It shows Fig.10 A circuit diagram showing the circuit configuration of the imaging device.

[0029] [ Fig.13 ] Fig.13 It shows Fig.10 A timing chart showing an example of the operation of the imaging device shown.

[0030] [ Fig.14 ] Fig.14 : is a schematic cross-sectional view showing a configuration example of an image pickup device according to Modification 3 of the present disclosure.

[0031] [ Fig.15 ] Fig.15 It shows Fig.14Schematic plan view of an example of the configuration of a sensor pixel in the imaging device shown.

[0032] [ Fig.16 ] Fig.16 : is a schematic plan view showing one example of the configuration of a sensor pixel in an image pickup device according to Modification 4 of the present disclosure.

[0033] [ Fig.17 ] Fig.17 It shows Fig.16 A circuit diagram showing the circuit configuration of the imaging device.

[0034] [ Fig.18 ] Fig.18 It shows Fig.16 A timing chart showing an example of the operation of the imaging device shown.

[0035] [ Fig.19 ] Fig.19 : is a schematic cross-sectional view showing another example of the configuration of the image pickup device according to Modification 4 of the present disclosure.

[0036] [ Fig. 20 ] Fig. 20 It shows Fig.19 Schematic plan view of an example of the configuration of a sensor pixel in the imaging device shown.

[0037] [ Fig.21 ] Fig.21 : is a schematic plan view showing one example of the configuration of a sensor pixel in an image pickup device according to Modification 5 of the present disclosure.

[0038] [ Fig. 22 ] Fig. 22 It shows Fig.21 A circuit diagram showing the circuit configuration of the imaging device.

[0039] [ Fig.23 ] Fig.23 It shows Fig.21 A timing chart showing an example of the operation of the imaging device shown.

[0040] [ Fig.24 ] Fig.24 : is a schematic plan view showing one example of the configuration of a sensor pixel in an image pickup device according to Modification 6 of the present disclosure.

[0041] [ Fig.25 ] Fig.25 It shows Fig.24 A circuit diagram showing the circuit configuration of the imaging device.

[0042] [ Fig.26 ] Fig.26: is a schematic plan view showing one example of the configuration of a sensor pixel in an image pickup device according to Modification 7 of the present disclosure.

[0043] [ Fig. 27 ] Fig. 27 : is a schematic plan view showing one example of the configuration of a sensor pixel in an image pickup device according to Modification 8 of the present disclosure.

[0044] [ Fig.28 ] Fig.28 It shows Fig.26 Circuit diagram of the circuit structure of the camera device shown in FIG.

[0045] [ Fig.29 ] Fig.29 It shows Fig.26 A timing diagram of an operation example of the imaging device shown in FIG. 1 .

[0046] [ Fig.30 ] Fig.30 : is a schematic plan view showing one example of the configuration of a sensor pixel in an image pickup device according to Modification 9 of the present disclosure.

[0047] [ Fig.31 ] Fig.31 It shows Fig.30 A circuit diagram showing the circuit configuration of the imaging device.

[0048] [ Fig.32 ] Fig.32 : is a schematic plan view showing another example of the configuration of a sensor pixel in the image pickup device according to Modification 9 of the present disclosure.

[0049] [ Fig.33 ] Fig.33 It shows Fig.32 A circuit diagram showing the circuit configuration of the imaging device.

[0050] [ Fig.34 ] Fig.34 is a schematic diagram showing an exemplary overall configuration of an electronic device (camera).

[0051] [ Fig.35 ] Fig.35 : is a schematic diagram showing an exemplary overall configuration of an electronic device (distance measuring device).

[0052] [ Fig.36 ] Fig.36 It shows Fig.35 A circuit diagram showing the circuit configuration in the sensor unit of the distance measuring device.

[0053] [ Fig.37 ] Fig.37 It shows Fig.35 A timing diagram showing an example of the operation of the ranging device shown.

[0054] [ Fig.38 ] Fig.38 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0055] [ Fig.39 ] Fig.39 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging section. DETAILED DESCRIPTION

[0056] Hereinafter, embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the following manner. In addition, the present disclosure is not limited to the characteristics such as the arrangement, size and size ratio of the components shown in the accompanying drawings. Hereinafter, the description will be given in the following order.

[0057] 1. First Embodiment

[0058] (Example of a semiconductor device in which one photoelectric conversion unit and two charge storage units are stacked in a semiconductor substrate)

[0059] 1-1. Schematic Structure of Image Capture Device

[0060] 1-2. Specific structure of the camera device

[0061] 1-3. Operation of the camera device

[0062] 1-4. Actions and effects

[0063] 2. Second Embodiment

[0064] (Example of a semiconductor device in which pixel transistors other than transfer transistors are formed on a separate substrate and stacked)

[0065] 3. Modifications

[0066] 3-1. Modification 1 (Example of bonding two semiconductor substrates face to back)

[0067] 3-2. Modification 2 (Example of Providing a Third Transfer Transistor Including a Vertical Transistor)

[0068] 3-3. Modification 3 (Example in which the First Transfer Transistor is Formed as a Vertical Transistor)

[0069] 3-4. Modification 4 (Example of additionally providing a discharge transistor)

[0070] 3-5. Modification 5 (Example in which a fourth transfer transistor is additionally provided)

[0071] 3-6. Modification 6 (Example of Sharing Two FDs Between Adjacent Sensor Pixels)

[0072] 3-7. Modification 7 (Example of Providing Two MEMs Having Different Areas)

[0073] 3-8. Modification 8 (Example of forming one MEM using FD)

[0074] 3-9. Modification 9 (Example of providing four MEMs in one PD)

[0075] 4. Application examples

[0076] 5. Application examples

[0077] <1. First Embodiment>

[0078] (1-1. Schematic Configuration of Image Capture Device)

[0079] Figure 1A : is a block diagram showing an exemplary functional configuration of the image pickup apparatus 100A according to the first embodiment of the present disclosure.

[0080] For example, the imaging device 100A is a so-called global shutter back-illuminated image sensor, such as a complementary metal-oxide semiconductor (CMOS) image sensor, and captures an image by receiving light from a subject, performing photoelectric conversion, and generating an image signal.

[0081] The global shutter method refers to a method of performing global exposure, in which exposure is started for all pixels substantially at the same time and exposure is ended for all pixels at the same time. Here, all pixels refer to all pixels in the portion where the image appears, excluding areas such as virtual pixels. In addition, if the time difference and image distortion are small enough not to cause problems, the global shutter method includes a method of moving the global exposure area while performing global exposure in units of multiple rows (for example, tens of rows) instead of performing global exposure for all pixels at the same time. In addition, the global shutter method includes a method of performing global exposure not for all pixels in the portion where the image appears but for pixels in a predetermined area.

[0082] A back-illuminated image sensor refers to an image sensor constructed in such a way that a photoelectric conversion unit such as a photodiode that receives light from the subject and converts the light into an electrical signal is provided between a light receiving surface onto which light from the subject is incident and an interconnection layer provided with wiring elements such as transistors for driving each pixel.

[0083] For example, the image pickup apparatus 100A is provided with a pixel array unit 111 , a vertical drive unit 112 , a column signal processing unit 113 , a data storage unit 119 , a horizontal drive unit 114 , a system control unit 115 , and a signal processing unit 118 .

[0084] In the image pickup device 100A, a pixel array unit 111 is formed on a semiconductor substrate 10 (described later). For example, peripheral circuits such as a vertical drive unit 112, a column signal processing unit 113, a data storage unit 119, a horizontal drive unit 114, a system control unit 115, and a signal processing unit 118 are formed on the same semiconductor substrate 10 as the pixel array unit 111.

[0085] The pixel array unit 111 includes a plurality of sensor pixels 110, each of which includes a photoelectric conversion unit 11 (described later) that generates and stores charges corresponding to the amount of incident light from a subject. As shown in FIG. 1 , the sensor pixels 110 are arranged in the horizontal direction (row direction) and the vertical direction (column direction), respectively. In the pixel array unit 111, a pixel driving line 116 is arranged in the row direction for each pixel row including the sensor pixels 110 arranged in a row in the row direction, and a vertical signal line (VSL) 117 is arranged in the column direction for each pixel column including the sensor pixels 110 arranged in a column in the column direction.

[0086] The vertical driving unit 112 includes components such as a shift register and an address decoder, etc. The vertical driving unit 112 provides information such as signals to the plurality of sensor pixels 110 through the plurality of pixel driving lines 116, and drives all the plurality of sensor pixels 110 in the pixel array unit 111 simultaneously or in units of pixel rows.

[0087] The signals output from the unit pixels of the pixel row selectively scanned by the vertical driving unit 112 are provided to the column signal processing unit 113 through each VSL 117. For each pixel column of the pixel array unit 111, the column signal processing unit 113 performs predetermined signal processing on the signals output from the unit pixels of the selected row through the VSL 117, and also temporarily holds the processed pixel signals.

[0088] Specifically, for example, the column signal processing unit 113 includes components such as a shift register and an address decoder, performs processing such as noise removal processing, correlated double sampling processing, and analog-to-digital (A / D) conversion processing on the analog pixel signal, and generates a digital pixel signal. The column signal processing unit 113 provides the generated pixel signal to the signal processing unit 118.

[0089] The horizontal driving unit 114 includes components such as a shift register and an address decoder, and sequentially selects unit circuits corresponding to pixel columns of the column signal processing unit 113. Pixel signals processed by the unit circuits in the column signal processing unit 113 selectively scanned by the horizontal driving unit 114 are sequentially output to the signal processing unit 118.

[0090] The system control unit 115 includes components such as a timing generator that generates various timing signals. The system control unit 115 controls driving of the vertical driving unit 112, the column signal processing unit 113, and the horizontal driving unit 114 based on the timing signals generated by the timing generator.

[0091] The signal processing unit 118 performs signal processing such as arithmetic processing on the pixel signal supplied from the column signal processing unit 113 while temporarily storing the data in the data storage unit 119 as necessary, and outputs an image signal containing each pixel signal.

[0092] During signal processing by the signal processing unit 118 , the data storage unit 119 temporarily stores data necessary for the signal processing.

[0093] Note that the camera device of the present disclosure is not limited to Figure 1A The camera device 100A shown in FIG. 1 may also have, for example, Figure 1B The camera device 100B shown in FIG. Figure 1C The imaging device 100C shown has the same structure. Figure 1B : is a block diagram showing an exemplary functional configuration of an image pickup apparatus 100B as a first modification example according to the first embodiment of the present disclosure. Figure 1C : is a block diagram showing an exemplary functional configuration of an image pickup apparatus 100C as a second modification example according to the first embodiment of the present disclosure.

[0094] exist Figure 1B In the image pickup device 100B, the data storage unit 119 is arranged between the column signal processing unit 113 and the horizontal driving unit 114 , and the pixel signal output from the column signal processing unit 113 is supplied to the signal processing unit 118 via the data storage unit 119 .

[0095] In addition, Figure 1C In the image pickup device 100C, the data storage unit 119 and the signal processing unit 118 are arranged in parallel between the column signal processing unit 113 and the horizontal driving unit 114. In the image pickup device 100C, the column signal processing unit 113 performs A / D conversion that converts analog pixel signals of one column of the pixel array unit 111 at a time or a plurality of columns of the pixel array unit 111 at a time into digital pixel signals.

[0096] (1-2. Specific Structure of the Camera Device)

[0097] For example, Figure 2 yes Figure 1A Schematic diagram of an example of a cross-sectional configuration of a pixel array unit 111 in an image pickup device 100A shown. Figure 3 For example Figure 1A For example, in the pixel array unit 111 of the imaging device 100A shown in FIG. Figure 2 The Sec1( Figure 3 (A)) and Sec2( Figure 3 Schematic diagram of an example of a planar configuration of four sensor pixels 110 (sensor pixels 1100, 1101, 1102, and 1103) in (B). Note that Figure 2 The cross-sectional view in corresponds to Figure 3 Shown are line II' and line II-II'. Figure 4 For example Figure 1A FIG. 1 is a diagram showing an example of a circuit configuration of a sensor pixel 110 in an image pickup device 100A shown in FIG. Figure 4 Shows Figure 3 Example circuit configurations of sensor pixel 1100 and sensor pixel 1102 are shown.

[0098] The sensor pixels 110 in the pixel array unit 111 implement a memory retention type global shutter. Each sensor pixel 110 of the present embodiment includes two charge storage units (MEM) 12A and 12B for one photoelectric conversion unit (PD) 11, and the photoelectric conversion unit and the two charge storage units are stacked in the semiconductor substrate 10. Specifically, the photoelectric conversion unit 11 is formed to be embedded in the first surface (back surface: surface S1) of the semiconductor substrate 10, and the charge storage units 12A and 12B are formed to be embedded in the second surface (front surface: surface S2) of the semiconductor substrate 10. The charge storage units 12A and 12B are arranged along Figure 3 The directions of the lines II' are shown arranged in parallel.

[0099] Although it will be described in detail later, in this embodiment, the photoelectric conversion unit 11 and the charge storage units 12A and 12B are arranged in a Figure 3 The pitch in the direction of the line II-II' shown is formed so that the photoelectric conversion unit 11 has a pitch (W), and the charge storage units 12A and 12B have approximately half the pitch (1 / 2W). On the second surface (surface S2) of the semiconductor substrate 10, the pixel transistors described later are arranged in parallel with the charge storage units 12A and 12B at approximately half the pitch of the photoelectric conversion unit 11, for example, in one direction (the direction of the line II-II') across two adjacent sensor pixels. Therefore, Figure 3 and Figure 4In order to distinguish the components of each sensor pixel 110 from each other, an identification number (0, 1, 2, 3) is added after the symbol of the component of each sensor pixel 110. However, as an exception to the above, since two transfer transistors (a first transfer transistor TRY and a second transistor TRG) are provided for each sensor pixel 110, respectively, the identification number (0, 1, 2, 3) is pre-added to the symbol. In the following, in the case where it is necessary to distinguish the components of each sensor pixel 110, the identification number will be pre-added or attached to the symbol of the component of each sensor pixel 110, but in the case where it is not necessary to distinguish the components of each sensor pixel 110, the identification number will be omitted at the end of the symbol of the component of each sensor pixel 110.

[0100] First, refer to Figure 4 An exemplary configuration of a circuit (pixel circuit) of each sensor pixel 110 provided in the pixel array unit 111 is described. For example, each sensor pixel 110 includes power supply lines VDD1 and VDD2, a photoelectric conversion unit (PD), two charge storage units (MEM1 and MEM2), two charge-voltage conversion units (floating diffusion FD), and a pixel transistor. The pixel transistor forms a readout circuit for reading out a signal output from the floating diffusion FD, and the pixel transistor includes, for example, first transfer transistors TRY1 and TRY2, second transfer transistors TRG1 and TRG2, a reset transistor RST, a selection transistor SEL, and an amplifier transistor AMP.

[0101] In this example, the first transfer transistors TRY1 and TRY2, the second transfer transistors TRG1 and TRG2, the amplifying transistor AMP, the selecting transistor SEL, and the reset transistor RST are all N-type MOS transistors, and each gate electrode is formed using polysilicon (poly-Si), for example. Based on the drive control of the system control unit 115, the respective gate electrodes of the first transfer transistors TRY1 and TRY2, the second transfer transistors TRG1 and TRG2, the amplifying transistor AMP, the selecting transistor SEL, and the reset transistor RST are respectively provided with corresponding drive signals from the vertical drive unit 112 and the horizontal drive unit 114. These drive signals are pulse signals that enter an active state (on state) at a high level and enter an inactive state (off state) at a low level.

[0102] The PD (photoelectric conversion unit 11) is a photoelectric conversion element including, for example, a PN junction photodiode and is configured to receive light from a subject and generate and store a charge corresponding to the amount of light received by photoelectric conversion. As described above, the PD is formed to be embedded in the first surface (surface S1) of the semiconductor substrate 10, but a portion of the PD (convex portion 11X) extends toward the second surface (surface S2).

[0103] MEM1 (charge storage unit 12A) is provided between the convex portion 11X of the PD and one of the two FDs (e.g., floating diffusion FD13), while MEM2 (charge storage unit 12B) is provided between the convex portion 11X of the PD and the other of the two FDs (e.g., floating diffusion FD14). In order to realize the global shutter function, MEM1 and MEM2 temporarily hold the charge while the charge generated and stored in the PD is transferred to the two FDs. MEM1 corresponds to a specific example of the “first charge storage unit” of the present disclosure, while MEM2 corresponds to a specific example of the “second charge storage unit” of the present disclosure. In addition, the two FDs correspond to specific examples of the “first charge-voltage conversion unit” and the “second charge-voltage conversion unit” of the present disclosure.

[0104] The first transfer transistor TRY1 is arranged between the convex portion 11X of the PD and MEM1, and the second transfer transistor TRG1 is arranged between MEM1 and one floating diffusion portion FD. The first transfer transistor TRY2 is arranged between the convex portion 11X of the PD and MEM2, and the second transfer transistor TRG2 is arranged between MEM2 and another floating diffusion portion FD. The first transfer transistors TRY1 and TRY2 are configured to transfer the charge stored in the PD to MEM1 and MEM2, respectively, according to the drive signal applied to the gate electrodes of the first transfer transistors TRY1 and TRY2. The second transfer transistors TRG1 and TRG2 are configured to transfer the charge temporarily held in MEM1 and MEM2 to the respectively connected FDs according to the drive signal applied to the gate electrodes of the second transfer transistors TRG1 and TRG2. The first transfer transistor TRY1 and the second transfer transistor TRG1 correspond to a specific example of the “first charge transfer unit” of the present disclosure, and the first transfer transistor TRY2 and the second transfer transistor TRG2 correspond to a specific example of the “second charge transfer unit” of the present disclosure. In each sensor pixel 110 , for example, when the first transfer transistors TRY1 and TRY2 are turned off and the second transfer transistors TRG1 and TRG2 are turned on, charges stored in MEM1 and MEM2 are transferred to each FD through the second transfer transistors TRG1 and TRG2 .

[0105] The two FDs are floating diffusion regions that convert charges transferred from the PD through the first transfer transistor TRY1, MEM1, and the second transfer transistor TRG1 or charges transferred from the PD through the first transfer transistor TRY2, MEM2, and the second transfer transistor TRG2 into electrical signals (eg, voltage signals) and output the electrical signals.

[0106] In this embodiment, two FDs are shared by sensor pixels 110 that are two pixels away from each other. Figure 3 1100 and sensor pixel 1102 are shown for illustration. The cathode of PD0 of sensor pixel 1100 is electrically connected to the source of each of the first transfer transistors TRY01 and TRY02, and the anode of PD0 is electrically connected to a reference potential line (e.g., ground). The drains of the first transfer transistors TRY01 and TRY02 are electrically connected to the sources of the second transfer transistors TRG01 and TRG02, respectively. The drain of the second transfer transistor TRG01 is electrically connected to FD0, and the drain of the second transfer transistor TRG02 is electrically connected to FD1. The cathode of PD2 of sensor pixel 1102 is electrically connected to the source of each of the first transfer transistors TRY21 and TRY22, and the anode of PD2 is electrically connected to the reference potential line (e.g., ground). The drains of the first transfer transistors TRY21 and TRY22 are electrically connected to the sources of the second transfer transistors TRG21 and TRG22, respectively. The drain of the second transfer transistor TRG21 is electrically connected to FD1, and the drain of the second transfer transistor TRG22 is electrically connected to FD2. In other words, FD1 is shared by sensor pixel 1100 and sensor pixel 1102. Figure 4 Although not shown in the figure, FD0 is shared by sensor pixel 1100 and an adjacent sensor pixel (hereinafter referred to as sensor pixel-1102 for convenience) at a distance of two pixels on the opposite side of sensor pixel 1102. FD2 is shared by sensor pixel 1102 and an adjacent sensor pixel (hereinafter referred to as sensor pixel 1104 for convenience) at a distance of two pixels on the opposite side of sensor pixel 1100.

[0107] A reset transistor RST is connected to each of the two FDs, and in addition, an amplification transistor AMP and a selection transistor SEL are connected to each of the two FDs through a VSL (VSL 117).

[0108] The reset transistor RST has a drain connected to the power supply line VDD1 and a source connected to one of the FDs. The reset transistor RST initializes or in other words resets the FD according to a drive signal applied to the gate electrode of the reset transistor RST. For example, when the reset transistor RST is turned on, the potential of the FD is reset to the voltage level of the power supply line VDD1. In other words, the FD is initialized.

[0109] The amplifier transistor AMP outputs an electric signal corresponding to the potential of the FD. The amplifier transistor AMP forms a source follower circuit together with a constant current source provided in the column signal processing unit 113, for example.

[0110] The selection transistor SEL is turned on when the sensor pixel 110 is selected, and the selection transistor SEL outputs the electric signal from the FD through the amplification transistor AMP to the column signal processing unit 113 via the VSL 117 .

[0111] Next, Figure 2 , Figure 3 A and Figure 3 B will be used to describe the settings in Figure 1A Detailed description of the drawings hereinafter. Detailed description of the drawings hereinafter.

[0112] Each sensor pixel 110 includes, for example, a semiconductor substrate 10 formed using a semiconductor material such as silicon (Si), a photoelectric conversion unit 11, and two charge storage units 12A and 12B. The semiconductor substrate 10 is, for example, a P-type (first conductivity type), while the photoelectric conversion unit 11 and the charge storage units 12A and 12B are N-type (second conductivity type). The photoelectric conversion unit 11 is formed so as to be embedded in a first surface (surface S1) of the semiconductor substrate 10, while the two charge storage units 12A and 12B are formed so as to be embedded in a second surface (surface S2) of the semiconductor substrate 10, for example, along Figure 3 The photoelectric conversion unit 11 is arranged in parallel in the direction of the line II' shown. In other words, the photoelectric conversion unit 11 is stacked with the two charge storage units 12A and 12B in the semiconductor substrate 10. Specifically, the charge storage units 12A and 12B are formed to be embedded in parallel along the line II', for example, with the convex portion 11X of the photoelectric conversion unit 11 placed between them. The charge generated by the photoelectric conversion unit 11 advances along the convex portion 11X toward the second surface (surface S2) of the semiconductor substrate 10 due to the potential gradient, and is distributed to the charge storage units 12A and 12B. In other words, the charge generated by the photoelectric conversion unit 11 is transmitted in the opposite direction, with the convex portion 11X of the photoelectric conversion unit 11 interposed between the two.

[0113] Furthermore, on the second surface (surface S2) of the semiconductor substrate 10, floating diffusions FD13 and FD14, a VDD contact region 15A connected to a power line VDD, a VSS contact region 15B connected to a power line VSS, and a VSL contact region 16 connected to VSL are provided.

[0114] In addition, as pixel transistors on the second surface (surface S2) side, each sensor pixel 110 includes, for example, first transfer transistors 22A (TRY1) and 23A (TRY2), second transfer transistors 22B (TRG1) and 23B (TRG2), a reset transistor 24 (RST), a selection transistor 25 (SEL), and an amplifier transistor 26 (AMP). As with the charge storage units 12A and 12B, the first transfer transistors 22A and 23A, the second transfer transistors 22B and 23B, the reset transistor 24, the selection transistor 25, and the amplifier transistor 26 are arranged, for example, along the line II-II' across two adjacent sensor pixels.

[0115] Specifically, the first transfer transistor 22A is arranged between the convex portion 11X of the photoelectric conversion unit 11 and the charge storage unit 12A, and the second transfer transistor 22B is arranged between the charge storage unit 12A and the floating diffusion FD13. The first transfer transistor 23A is arranged between the convex portion 11X of the photoelectric conversion unit 11 and the charge storage unit 12B, and the second transfer transistor 23B is arranged between the charge storage unit 12B and the floating diffusion FD14. The reset transistor 24 is arranged next to the second transfer transistor 23B, with the floating diffusion FD14 located between them. The amplification transistor 26 and the selection transistor 25 are arranged next to the reset transistor 24 in this order, with the VDD contact area 15A located between the amplification transistor 26 and the reset transistor 24.

[0116] In the present embodiment, as described above, the charge storage units 12A and 12B and the pixel transistors are formed at approximately half the pitch (1 / 2W) relative to the pitch (W) of the photoelectric conversion unit 11, and the pixel transistors are arranged across two adjacent sensor pixels. Figure 3 As shown, the pixel transistors (TRY01, TRY02, TRG01, TRG02, RST01, AMP01 and SEL01) of the sensor pixel 1100 are arranged across the sensor pixel 1100 and the sensor pixel 1101 in the area X1 obtained by dividing the plurality of sensor pixels 110 into two parts in the direction of line I-I', and the pixel transistors (TRY11, TRY12, TRG11, TRG12, RST11, AMP11 and SEL11) of the sensor pixel 1101 are arranged across the sensor pixel 1100 and the sensor pixel 1101 in the area X2 obtained by dividing the plurality of sensor pixels 110 into two parts in the direction of line I-I'. In addition, the pixel transistors (TRY21, TRY22, TRG21, TRG22, RST21, AMP21, and SEL21) of the sensor pixel 1102 are arranged across the sensor pixel 1101 and the sensor pixel 1102 in the region X1 obtained by dividing the plurality of sensor pixels 110 into two parts in the direction of the line II'. In other words, the pixel transistors of the sensor pixels 110 adjacent to each other in the direction of the line II' are respectively arranged alternately between one region and the other region obtained by dividing the plurality of sensor pixels 110 into two parts in the direction of the line II', and are staggered by one sensor pixel.

[0117] For example, an insulating film 21 including oxide or the like is provided between the semiconductor substrate 10 and the pixel transistor. An interconnection layer (for example, an interconnection layer 20 described later; see Figure 6). Inside the interconnection layer, in addition to the gate electrode of the pixel transistor, for example, an interconnection line M1 for applying a drive signal to the gate electrode is provided. In addition, the semiconductor substrate 10 is provided with, for example, a pixel isolation portion 17 surrounding the photoelectric conversion unit 11 and an isolation film 18 for shielding light between the photoelectric conversion unit 11 and the charge storage units 12A and 12B.

[0118] The pixel isolation section 17 is used to optically and electrically isolate adjacent sensor pixels 110 from each other, and is provided between adjacent photoelectric conversion units 11 in a manner extending from the first surface (surface S1) to the second surface (surface S2) of the semiconductor substrate 10. For example, the pixel isolation section 17 includes a metal film such as tungsten (W) surrounded by an oxide film, and the oxide is, for example, silicon oxide (SiO2), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), or tantalum oxide (Ta2O5). With this arrangement, oblique incident light that may be incident from adjacent pixels P is blocked by the metal film, thereby achieving optical isolation, and in addition, adjacent sensor pixels are electrically isolated from each other by the oxide film.

[0119] The isolation film 18 electrically and optically isolates the photoelectric conversion unit 11 from the charge storage units 12A and 12B. For example, like the pixel isolation unit 17, the isolation film 18 includes a metal film of tungsten (W) or the like surrounded by an oxide film of silicon oxide (SiO2) or the like. By providing the isolation film 18 between the photoelectric conversion unit 11 and the charge storage units 12A and 12B, light is suppressed from entering the charge storage units 12A and 12B, and noise can be reduced. With this arrangement, the parasitic light sensitivity (PLS) characteristic is improved.

[0120] Furthermore, each sensor pixel 110 may further include a color filter 31 and an on-chip lens 32 located on the first surface (surface S1 ) of the semiconductor substrate 10 , or in other words, on the light incident side.

[0121] For example, the color filter 31 includes a red filter that transmits light in a red wavelength band, a green filter that transmits light in a green wavelength band, and a blue filter that transmits light in a blue wavelength band, and these filters are arranged in a regular color array (e.g., a Bayer array) in the pixel array unit 111. For example, a light shielding portion may also be provided between adjacent pixels of the color filter 31.

[0122] The on-chip lens 32 focuses light incident from the first surface (surface S1) side of the semiconductor substrate 10 onto the photoelectric conversion unit 11. For example, the on-chip lens 32 is formed using a material with a high refractive index, specifically an inorganic material such as silicon oxide (SiO2) or silicon nitride (SiN). In addition, an organic material with a high refractive index, such as an episulfide resin or a titanium compound and its resin, can be used. There is no particular limitation on the shape of the on-chip lens 32, and any of various lens shapes such as a hemispherical shape and a semi-cylindrical shape can be used. Figure 2 As shown, for example, an on-chip lens 32 may be provided for each sensor pixel 110 , or one on-chip lens may be provided for a plurality of sensor pixels 110 .

[0123] (1-3. Operation of the imaging device)

[0124] Figure 5 An example of a timing chart for driving the sensor pixels 110 of the image pickup device 100A is shown.

[0125] In the imaging device 100A of the present embodiment, the resetting of the PD is performed, for example, by MEM2. First, after the first transfer transistor TRY2 is turned off, the exposure in the sensor pixel 1100 starts, and the generation and storage of the charge in the PD starts. Thereafter, by turning on the first transfer transistor TRY1 after t1 seconds, the charge is transferred from the PD to the MEM1. Next, after the first transfer transistor TRY1 is turned off, the exposure in the sensor pixel 1100 starts, and the generation and storage of the charge in the PD restarts. Thereafter, by turning on the first transfer transistor TRY2 after t2 seconds, the charge is transferred from the PD to the MEM2. This series of driving processes is repeated within the global transfer period.

[0126] After the global transfer period ends, the charges stored in each of MEM1 and MEM2 are transferred to each FD and sequentially output to VSL as voltage signals according to rolling readout. At this time, a pseudo sensitivity ratio can be given to the two units MEM1 and MEM2 according to the time difference between t1 and t2. With this arrangement, signals of different sensitivities can be stored simultaneously and read out separately.

[0127] (1-4. Actions and Effects)

[0128] In the image pickup device 100A of the present embodiment, two units MEM1 (charge storage unit 12A) and MEM2 (charge storage unit 12B) are provided for one PD (photoelectric conversion unit 11), the PD is arranged on the first surface (surface S1) of the semiconductor substrate 10, and the two units MEM1 and MEM2 are arranged on the second surface (surface S2) of the semiconductor substrate 10. With this arrangement, the area efficiency of the PD and the two units MEM1 and MEM2 in each sensor pixel 110 is increased. Hereinafter, the above aspects will be described.

[0129] As described above, in an image sensor implementing a global shutter, a structure has been proposed in which two or more charge storage units (MEM) are provided for one photoelectric conversion unit (PD). In the image sensor, by transferring charges multiple times for each MEM during an exposure period, charges are stored for a long time, or in other words, a high dynamic range image is captured.

[0130] However, in the above image sensor, since the PD and two MEMs are arranged on the same plane, the area of ​​the PD and MEM in a single pixel is reduced, which causes problems such as reduced saturation charge (Qs), reduced sensitivity, and reduced freedom of layout.

[0131] In contrast, in the present embodiment, the PD is formed to be embedded in the first surface (plane S1) of the semiconductor substrate 10, and the two cells MEM1 and MEM2 are formed to be embedded in the second surface (plane S2) of the semiconductor substrate 10. In other words, one PD is stacked with the two cells MEM1 and MEM2 in the semiconductor substrate 10. This arrangement can increase the area of ​​the PD and the two cells MEM1 and MEM2 in each sensor pixel 110.

[0132] According to the above, in the image pickup device 100A of the present embodiment, the saturation charge (Qs) can be increased and the sensitivity can be improved. Therefore, an image pickup device having a large saturation charge and a high sensitivity can be provided.

[0133] Furthermore, in the imaging device 100A of the present embodiment, the degree of freedom in layout can be increased.

[0134] Furthermore, in the image pickup device 100A of the present embodiment, by providing the light shielding isolation film 18 between the PD (photoelectric conversion unit 11) stacked in the semiconductor substrate 10 and the two units MEM1 (charge storage unit 12A) and MEM2 (charge storage unit 12B), the light incident on MEM1 and MEM2 through the PD is reduced. Therefore, the occurrence of erroneous signals in MEM1 and MEM2 can be reduced.

[0135] Next, a second embodiment of the present disclosure and Modifications 1 to 9 will be described. Hereinafter, components similar to those of the above-described first embodiment are denoted by the same reference numerals, and descriptions of these components are appropriately omitted.

[0136] <2. Second Embodiment>

[0137] Figure 6 1 is a schematic diagram of an example of a cross-sectional configuration of a pixel array unit 111 in an image pickup device 100D according to the second embodiment of the present disclosure. Figure 7 is Figure 6 For example, in the pixel array unit 111 of the imaging device 100D shown in FIG. Figure 6 The Sec2 ( Figure 7 (A)) and Sec3( Figure 7 Schematic diagram of an example of a planar configuration of four sensor pixels 110 (sensor pixels 1100, 1101, 1102, and 1103) in (B). Note that Figure 6 The cross-sectional view in corresponds to Figure 7 Shown are line II' and line II-II'.

[0138] In the imaging device 100A of the first embodiment described above, pixel transistors, namely, first transfer transistors 22A (TRY1) and 23A (TRY2), second transfer transistors 22B (TRG1) and 23B (TRG2), reset transistor 24 (RST), selection transistor 25 (SEL), and amplifier transistor 26 (AMP) are provided on the second surface (surface S2) of the semiconductor substrate 10. In contrast, in the imaging device 100D of the present embodiment, among the above-mentioned pixel transistors, the reset transistor 24 (RST), the selection transistor 25 (SEL), and the amplifier transistor 26 (AMP) are provided on a substrate separate from the semiconductor substrate 10, for example, a semiconductor substrate 40, and the semiconductor substrates are bonded together, for example, by Cu-Cu bonding.

[0139] Specifically, as in the above-described first embodiment, the photoelectric conversion unit 11 is formed to be embedded in the first surface (surface S1) of the semiconductor substrate 10, and the charge storage units 12A and 12B are formed to be embedded in the second surface (surface S2) of the semiconductor substrate 10. In addition, an insulating film 21 is provided on the second surface (surface S2) of the semiconductor substrate 10. Through the insulating film 21, first transfer transistors 22A (TRY1) and 23A (TRY2) and second transfer transistors 22B (TRG1) and 23B (TRG2) are provided on the second surface (surface S2) of the semiconductor substrate.

[0140] In addition to the gate electrodes of the first transfer transistors 22A (TRY1) and 23A (TRY2) and the second transfer transistors 22B (TRG1) and 23B (TRG2), an interconnection layer 20 including an insulating film 21 and a plurality of interconnections is provided on the second surface (surface S2) of the semiconductor substrate 10. In the interconnection layer 20, the interconnections M1, M2, and M3 are formed as a plurality of interconnections within the interlayer insulating film 27. A plurality of pad electrodes 28 including, for example, copper (Cu) are exposed on the surface of the interlayer insulating film 27.

[0141] The semiconductor substrate 40 is formed using a semiconductor material such as silicon (Si), for example, and has a first surface (front surface: surface S3) and a second surface (back surface: surface S4) facing each other. On the first surface (surface S3) of the semiconductor substrate, for example, a reset transistor 24 (RST), a selection transistor 25 (SEL), and an amplifier transistor 26 (AMP) are provided via an insulating film 51 containing a material such as oxide.

[0142] On the first surface (surface S3) of the semiconductor substrate 40, in addition to the gate electrodes of the reset transistor 24 (RST), the selection transistor 25 (SEL), and the amplifier transistor 26 (AMP), an interconnection layer 50 including an insulating film 51 and a plurality of interconnections is provided. In the interconnection layer 50, the interconnections M4, M5, and M6 are formed as a plurality of interconnections within the interlayer insulating film 52. A plurality of pad electrodes 53 including, for example, copper (Cu) are exposed on the surface of the interlayer insulating film 52.

[0143] The semiconductor substrate 10 and the semiconductor substrate 40 are bonded together by making the second surface (surface S2) of the semiconductor substrate 10 and the first surface (surface S3) of the semiconductor substrate 40 face each other and bonding the plurality of pad electrodes 28 disposed on and exposed on the surface of the interconnect layer 20 and the plurality of pad electrodes disposed on and exposed on the surface of the interconnect layer 50, respectively. In other words, the semiconductor substrate 10 and the semiconductor substrate 40 are bonded together in a so-called face-to-face configuration.

[0144] As in the first embodiment described above, the charge storage units 12A and 12B and the pixel transistors are formed at approximately half the pitch (1 / 2W) relative to the pitch (W) of the photoelectric conversion unit 11. In addition, in the present embodiment, the first transfer transistors 22A (TRY1) and 23A (TRY2) and the second transfer transistors 22B (TRG1) and 23B (TRG2) formed on the semiconductor substrate 10 are arranged in parallel across two adjacent sensor pixels. Similarly, the reset transistor 24 (RST), the selection transistor 25 (SEL), and the amplifier transistor 26 (AMP) formed on the semiconductor substrate 40 are also arranged in parallel across two adjacent sensor pixels. In other words, the areas of the first transfer transistors 22A (TRY1) and 23A (TRY2) and the second transfer transistors 22B (TRG1) and 23B (TRG2) can be increased. This arrangement can maximize the areas of the charge storage units 12A and 12B.

[0145] In this way, in the image pickup device 100D of the present embodiment, among the pixel transistors, the reset transistor 24 (RST), the selection transistor 25 (SEL) and the amplifier transistor 26 (AMP) other than the first transfer transistors 22A (TRY1) and 23A (TRY2) and the second transfer transistors 22B (TRG1) and 23B (TRG2) are arranged on a separate substrate (semiconductor substrate 40), so that the area of ​​the two units MEM1 (charge storage unit 12A) and MEM2 (12B) can be further increased. Therefore, compared with the image pickup device 100A of the first embodiment described above, the saturation charge (Qs) can be further increased and the sensitivity can be further improved. In addition, the degree of freedom of layout can be further improved.

[0146] <3. Modifications>

[0147] (3-1. Modification 1)

[0148] Figure 8 1 is a schematic diagram of an example of a cross-sectional configuration of a pixel array unit 111 in an image pickup device 100E according to Modification 1 of the present disclosure. Fig. 9 In e.g. Figure 8 The pixel array unit 111 of the camera device 100E shown in FIG. Figure 8 The Sec2 ( Fig. 9 (A)) and Sec3( Fig. 9 Schematic diagram of an example of a planar configuration of four sensor pixels 110 (sensor pixels 1100, 1101, 1102, and 1103) in (B). Note that Figure 8 The cross-sectional view in corresponds to Fig. 9 Shown are line II' and line II-II'.

[0149] As in the imaging device 100D of the second embodiment described above, in the imaging device 100E of the present embodiment, among the pixel transistors, the reset transistor 24 (RST), the selection transistor 25 (SEL), and the amplifier transistor 26 (AMP) are provided on a substrate (semiconductor substrate 40) separate from the semiconductor substrate 10 provided with the photoelectric conversion unit 11 (PD), the charge storage units 12A (MEM1) and 12B (MEM2), the first transfer transistors 22A (TRY1) and 23A (TRY2), and the second transfer transistors 22B (TRG1) and 23B (TRG2). As in the second embodiment described above, among the pixel transistors, the reset transistor 24 (RST), the selection transistor 25 (SEL), and the amplifier transistor 26 (AMP) are formed on the first surface (surface S3) of the semiconductor substrate 40. The camera device 100E of this variant example differs from the above-mentioned second embodiment in that the semiconductor substrate 10 and the semiconductor substrate 40 are bonded together in a so-called face-to-back configuration, wherein the second surface (front surface: surface S2) of the semiconductor substrate 10 and the second surface (back surface: surface S4) of the semiconductor substrate 40 are opposite to each other.

[0150] For example, the imaging device 100E can be formed as follows. First, gate electrodes of the first transfer transistors 22A (TRY1) and 23A (TRY2) and the second transfer transistors 22B (TRG1) and 23B (TRG2) are formed on the second surface (surface S2) of the semiconductor substrate 10. Thereafter, the interconnection layer 20 is formed by covering the gate electrodes with an interlayer insulating film 27. Next, after flattening the surface of the interconnection layer 20, the semiconductor substrate 40 is adhered to the semiconductor substrate 10 using the second surface (surface S4) as a bonding surface, and the semiconductor substrate 40 is thinned. Thereafter, components such as a reset transistor 24 (RST), a selection transistor 25 (SEL), and an amplifier transistor 26 (AMP) are formed on the first surface (surface S3) of the semiconductor substrate. Note that an electrical connection between the semiconductor substrate 10 and the semiconductor substrate 40 is formed using, for example, a through hole 54. With this arrangement, the completion is completed. Figure 8 The camera device 100E is shown.

[0151] In this manner, in the present modification, since the semiconductor substrate 10 and the semiconductor substrate 40 are bonded together in a so-called face-to-back configuration, the length of the interconnection line to the floating diffusion FD can be shortened, for example, compared to the image pickup device 100D of the second embodiment described above. Therefore, in addition to the effects of the first and second embodiments described above, the FD conversion efficiency can be improved.

[0152] (3-2. Modification 2)

[0153] Fig.102 is a schematic diagram of an example of a cross-sectional configuration of a pixel array unit 111 in an image pickup device 100F according to Modification 2 of the present disclosure. Fig.11 In e.g. Fig.10 The pixel array unit 111 of the camera device 100F shown in FIG. Fig.10 The Sec1( Fig.11 (A)) and Sec2( Fig.11 Schematic diagram of an example of a planar configuration of four sensor pixels 110 (sensor pixels 1100, 1101, 1102, and 1103) in (B). Note that Fig.10 The cross-sectional view in corresponds to Fig.11 Shown are line II' and line II-II'. Fig.12 yes Fig.10 FIG. 2 is a diagram showing an example of a circuit configuration of a sensor pixel 110 in an image pickup device 100F shown in FIG.

[0154] The image pickup device 100F of the present modification example is different from the above-described second embodiment in that a so-called vertical third transfer transistor (TRZ) is provided between the first transfer transistor 22A (TRY1) and the first transfer transistor 23A (TRY2).

[0155] In the imaging device 100F, the gate electrode (transfer gate electrodes 19A and 19B) of the third transfer transistor 29 (TRZ) extends to the photoelectric conversion unit 11, which is formed to be embedded in the first surface (surface S1) of the semiconductor substrate 10. For example, the charge generated by the photoelectric conversion unit 11 is distributed to the charge storage unit 12A (MEM1) through the transfer gate electrode 19A and to the charge storage unit 12B (MEM2) through the transfer gate electrode 19B. In other words, within the photoelectric conversion unit 11, the charge can be transferred without forming a potential gradient that changes from the first surface (surface S1) to the second surface (surface S2) of the semiconductor substrate 10. Therefore, the potential of the photoelectric conversion unit 11 can be deepened, so that the saturation charge (Qs) can be increased.

[0156] Note that the transfer gate electrodes 19A and 19B are formed so that the line connecting the two to each other is orthogonal to the arrangement direction of the two charge storage units 12A (MEM1) and 12B (MEM2), for example.

[0157] Fig.13An example of a timing chart for driving the sensor pixel 110 of the image pickup device 100F is shown. Since the charge readout from the photoelectric conversion unit PD is performed by the third transfer transistor TRZ, the exposure period of the photoelectric conversion unit PD is synonymous with the off period of the third transfer transistor TRZ. Therefore, it is difficult to make the exposure period t2 shorter than the period in which the drive pulse of the third transfer transistor TRZ completely falls and then completely rises again.

[0158] In this way, in the image pickup device 100F of the present modification, the charge generated by the photoelectric conversion unit 11 is distributed to the charge storage units 12A and 12B using the vertical transistor (the third transfer transistor 29 (TRZ)), so it is possible to deepen the potential of the photoelectric conversion unit 11. Therefore, in addition to the effects of the first and second embodiments described above, the saturation charge (Qs) can be further increased.

[0159] (3-3. Modification 3)

[0160] Fig.14 1 is a schematic diagram of an example of a cross-sectional configuration of a pixel array unit 111 in an image pickup device 100G according to Modification 3 of the present disclosure. Fig.15 In e.g. Fig.14 The pixel array unit 111 of the camera device 100G shown in FIG. Fig.14 The Sec1( Fig.15 (A)) and Sec2( Fig.15 Schematic diagram of an example of a planar configuration of four sensor pixels 110 (sensor pixels 1100, 1101, 1102, and 1103) in (B). Note that Fig.14 The cross-sectional view in corresponds to Fig.15 Shown are line II' and line II-II'.

[0161] The above modification 2 shows an example of distributing the charge generated by the photoelectric conversion unit 11 to the charge storage units 12A and 12B by providing a so-called vertical third transfer transistor (TRZ) between the first transfer transistor 22A (TRY1) and the first transfer transistor 23A (TRY2), but the first transfer transistors 22A (TRY1) and 23A (TRY2) can also be used as the third transfer transistor (TRZ). This modification is different from the above modification 2 in that the first transfer transistors 22A (TRY1) and 23A (TRY2) are formed as vertical transistors.

[0162] In the imaging device 100G, the gate electrodes (transfer gate electrodes 19C (19Ca and 19Cb) and 19D (19Da and 19Db)) of the first transfer transistor 22A (TRY1) and the first transfer transistor 23A (TRY2) extend to the photoelectric conversion unit 11 embedded in the first surface (surface S1) of the semiconductor substrate 10.

[0163] Note that the timing chart for driving the sensor pixels 110 in the image pickup device 100G of this modification is similar to the timing chart of the first embodiment described above ( Figure 5 In other words, the exposure periods t1 and t2 are determined according to the conduction intervals of the first transfer transistors 22A (TRY1) and 23A (TRY2).

[0164] As described above, in the image pickup device 100G of the present modification, the first transfer transistors 22A (TRY1) and 23A (TRY2) are formed as vertical transistors, so that the exposure periods t1 and t2 can be determined according to the conduction intervals of the first transfer transistors 22A (TRY1) and 23A (TRY2). Therefore, in addition to the effects of the first and second embodiments described above, the saturation charge (Qs) can be further increased while also shortening the conduction intervals of the first transfer transistors 22A (TRY1) and 23A (TRY2), respectively, so that the charge can be stored and distributed in a shorter time.

[0165] (3-4. Modification 4)

[0166] Fig.16 1 is a schematic diagram of an example of a planar configuration of four sensor pixels 110 (sensor pixels 1100 , 1101 , 1102 , and 1103 ) of a pixel array unit 111 in an image pickup device 100H according to Modification 4 of the present disclosure. Fig.17 yes Fig.16 FIG. 2 is a diagram showing an example of a circuit configuration of a sensor pixel 110 in an image pickup device 100H shown in FIG. Fig.18 An example of a timing chart for driving the sensor pixels 110 of the image pickup device 100H is shown.

[0167] The image pickup device 100H of this modification is different from the second embodiment described above in that a discharge transistor OFG (discharge transistor 33) for initializing, or in other words, resetting, PD is additionally provided as a pixel transistor. Note that resetting PD means depleting PD.

[0168] The discharge transistor OFG is disposed between the first transfer transistor TRY1 and the first transfer transistor TRY2 and has, for example, a drain connected to the power supply line VDD and sources connected to the first transfer transistors TRY1 and TRY2. The discharge transistor OFG resets the PD according to a driving signal applied to a gate electrode.

[0169] In this manner, in the image pickup device 100H of this modification, by providing the discharge transistor OFG for resetting the PD, the PD can be reset without passing through MEM1 and MEM2. Therefore, in addition to the effects of the first and second embodiments described above, pipeline exposure can be performed when the two units MEM1 and MEM2 are in the charge storage state.

[0170] Furthermore, in the image pickup device 100H of this modification, by turning on the discharge transistor OFG outside the global transfer period, the charge overflowing from the PD is selectively discarded to the drain of the discharge transistor OFG without causing overflow in MEM1 and MEM2. Therefore, the occurrence of erroneous signals can be reduced.

[0171] Note that in the image pickup device 100H of this modification, the third transfer transistor TRZ may be formed using a vertical transistor as in the above-described modification 2, or alternatively, the first transfer transistors TRY1 and TRY2 may be formed vertically as in the modification 3. For example, in the case where the first transfer transistors TRY1 and TRY2 are formed vertically, for example Fig.19 , Fig. 20 A and Fig. 20 As shown in FIG. 8B , similar to the first transfer transistors TRY1 and TRY2 , the discharge transistor OFG is also formed as a vertical transistor reaching the discharge gate electrode 19E of the PD.

[0172] (3-5. Modification 5)

[0173] Fig.21 1 is a schematic diagram of an example of a planar configuration of four sensor pixels 110 (sensor pixels 1100 , 1101 , 1102 , and 1103 ) of a pixel array unit 111 in an image pickup device 100I according to Modification 5 of the present disclosure. Fig. 22 yes Fig.21 A diagram showing an example of a circuit configuration of a sensor pixel 110 in an image pickup device 100I shown. Fig.23 An example of a timing chart for driving the sensor pixels 110 of the image pickup device 100I is shown.

[0174] The image pickup device 100I of this modification example is different from the second embodiment in that fourth transfer transistors TRX1 and TRX2 are provided between the first transfer transistor TRY1 and the second transfer transistor TRG1 and between the first transfer transistor TRY2 and the second transfer transistor TRG2 , respectively.

[0175] The fourth transfer transistors TRX1 and TRX2 are used to hold charges in MEM1 and MEM2 and also transfer charges to the second transfer transistors TRG1 and TRG2 , respectively.

[0176] In this way, in the image pickup device 100I of the present modification, by providing the fourth transfer transistors TRX1 and TRX2 between the first transfer transistor TRY1 and the second transfer transistor TRG1 and between the first transfer transistor TRY2 and the second transfer transistor TRG2, respectively, it is possible to deepen the potential of MEM1 and MEM2 away from each FD (for example, FD0 and FD1). Therefore, in addition to the effects of the first and second embodiments described above, the MEM saturation charge (Qs) can be increased.

[0177] Note that although the present modification shows an example in which one of each of the fourth transfer transistors TRX1 and TRX2 is provided, two or more transistors may be formed as the fourth transfer transistors TRX1 and TRX2 .

[0178] (3-6. Modification 6)

[0179] Fig.24 1 is a schematic diagram of an example of a planar configuration of four sensor pixels 110 (sensor pixels 1100 , 1101 , 1102 , and 1103 ) of a pixel array unit 111 in an image pickup device 100J according to Modification 6 of the present disclosure. Fig.25 yes Fig.24 FIG. 2 is a diagram showing an example of a circuit configuration of a sensor pixel 110 in an image pickup device 100J shown.

[0180] In the first and second embodiments described above, the charges generated by the photoelectric conversion unit 11 are transferred in opposite directions, and the two FDs to which the charges are transferred are respectively shared by the sensor pixels 110 that are two pixels away from each other. In contrast, in the image pickup device 100J of the present modification, two FDs (e.g., FD0 and FD1) are shared by two adjacent sensor pixels 110 (e.g., sensor pixels 1100 and 1101). This point is different from the second embodiment described above.

[0181] In this modification, two units MEM1 and MEM2 are arranged in parallel in each sensor pixel 110, and the charges generated by the PDs are transmitted in the same direction. In addition, in this modification, as described above, two FDs (e.g., FD0 and FD1) are shared by two adjacent sensor pixels 110 (e.g., sensor pixels 1100 and 1101). With this arrangement, in adjacent sensor pixels 110 (e.g., sensor pixel 1100 and sensor pixel 1101), the charges generated by each PD (e.g., PD0 and PD1) are transmitted in opposite directions. In addition, in this modification, since the two units MEM1 and MEM2 are arranged in parallel in each sensor pixel 110, the spacing between the two units MEM1 and MEM2 is the same spacing as the spacing between the PDs.

[0182] In this way, even in the case where the two units MEM1 and MEM2 are arranged in parallel within the pitch of the PD, the same effect as that of the above-described second embodiment can be obtained.

[0183] (3-7. Modification 7)

[0184] Fig.26 1 is a schematic diagram of an example of a planar configuration of four sensor pixels 110 (sensor pixels 1100 , 1101 , 1102 , and 1103 ) of a pixel array unit 111 in an image pickup device 100K according to Modification 7 of the present disclosure.

[0185] The above-described first and second embodiments and the like show examples in which the two cells MEM1 and MEM2 have the same area, but the two cells MEM1 and MEM2 may also have different sizes.

[0186] By this arrangement, in the image pickup device 100K of this modification, it is possible to provide a capacity ratio for the two units MEM1 and MEM2. In other words, for example, in the case where there is a sensitivity difference (e.g., a difference in exposure time) between MEM1 and MEM2, the MEM saturation charge (Qs) can be changed according to the sensitivity difference. Therefore, in addition to the effects of the first and second embodiments described above, a signal with a higher sensitivity can be maintained.

[0187] (3-8. Modification 8)

[0188] Fig. 27 1 is a schematic diagram of an example of a planar configuration of four sensor pixels 110 (sensor pixels 1100 , 1101 , 1102 , and 1103 ) of a pixel array unit 111 in an image pickup device 100L according to Modification 8 of the present disclosure. Fig.28 yes Fig. 27 A diagram showing an example of a circuit configuration of a sensor pixel 110 in an image pickup device 100L shown. Fig.29An example of a timing chart for driving the sensor pixels 110 of the image pickup device 100L is shown.

[0189] The first and second embodiments described above etc. show an example in which two units MEM1 and MEM2 are provided, but for example, one MEM (e.g., MEM2) may also be used as an FD (e.g., FD1). In other words, in the image pickup device 100L of this modification, a part of the charge generated by the photoelectric conversion unit 11 is directly transferred to the floating diffusion FD.

[0190] Furthermore, in the image pickup device 100L of the present modification, for example, FD1 to which the charge in the sensor pixel 1100 is directly transferred from PD0 is a destination to which the charge is transferred from PD1 via the MEM (e.g., MEM12) in the adjacent sensor pixel 1101. In this case, for example, the charge generated by PD0 and PD1 is stored in MEM01 and FD1, respectively. In the rolling shutter readout period, first, the potential of FD0 is output in a state where the charge from PD1 is stored in FD0. Thereafter, the potential is output after the potential is reset, and finally the potential is output after the charge stored in MEM01 is transferred.

[0191] In this way, in the image pickup device 100L of this modification, since one of the two units MEM1 and MEM2 is also used as the floating diffusion FD, the area of ​​the other MEM can be maximized. With this arrangement, in addition to the effects of the first and second embodiments described above, it is possible to simultaneously store signals of different sensitivities and read them out separately.

[0192] (3-9. Modification 9)

[0193] Fig.30 1 is a schematic diagram of an example of a planar configuration of four sensor pixels 110 (sensor pixels 1100 , 1101 , 1102 , and 1103 ) of a pixel array unit 111 in an image pickup device 100M according to Modification 9 of the present disclosure. Fig.31 yes Fig.30 A diagram showing an example of a circuit configuration of a sensor pixel 110 in an image pickup device 100M shown.

[0194] The first and second embodiments described above show an example in which two units MEM1 and MEM2 are provided for one PD, but the number of MEMs is not limited to the above number. Fig.30 As shown, four units MEM1, MEM2, MEM3, and MEM4 may be provided for one photoelectric conversion unit PD.

[0195] Fig.321 is a schematic diagram of another example of the planar configuration of the four sensor pixels 110 (sensor pixels 1100 , 1101 , 1102 , and 1103 ) of the pixel array unit 111 in the image pickup device 100M according to Modification 9 of the present disclosure. Fig.33 yes Fig.32 A diagram showing an example of a circuit configuration of a sensor pixel 110 in an image pickup device 100M shown.

[0196] like Fig.32 As shown, in the image pickup device 100M of this modification, for example, two adjacent FDs (for example, FD0 and FD1, or FD2 and FD3) can be short-circuited by the vertical signal line VSL. Fig.32 and Fig.33 An example of short-circuiting two adjacent FDs is shown, but for example, four FDs may be short-circuited. With this arrangement, the number of vertical signal lines VSL per pixel can be reduced, thereby increasing the degree of freedom in interconnection line layout. In addition, the occurrence of short-circuit failures between interconnections can be reduced, thereby increasing the yield rate.

[0197] <4. Application Examples>

[0198] Fig.34 is a block diagram showing a configuration example of a camera 2000 as an electronic device to which the present technology is applied.

[0199] The camera 2000 includes an optical unit 2001 including a lens group and the like, an image pickup device (image pickup device) 100A to which the above-described image pickup device (e.g., 100A and the like) is applied, and a digital signal processor (DSP) circuit 2002 as a camera signal processing circuit. In addition, the camera 2000 includes a frame memory 2003, a display unit 2004, a recording unit 2005, an operation unit 2006, and a power supply unit 2007. The DSP circuit 2002, the frame memory 2003, the display unit 2004, the recording unit 2005, the operation unit 2006, and the power supply unit 2007 are connected to each other via a bus 2008.

[0200] The optical unit 2001 acquires incident light (image light) from the subject to form an image on the imaging surface of the imaging device 100A. The imaging device 100A converts the light intensity of the incident light formed by the optical unit 2001 on the imaging surface into an electrical signal in units of pixels, and outputs the converted signal as a pixel signal.

[0201] The display unit 2004 includes a panel-type display device such as a liquid crystal panel or an organic EL panel, and displays a moving image or a still image captured by the camera 100A. The recording unit 2005 records the moving image or the still image captured by the camera 100A in a recording medium such as a hard disk or a semiconductor memory.

[0202] The operation unit 2006 issues operation commands regarding various functions of the camera 2000 according to operations performed by the user. The power supply unit 2007 supplies various power sources as operation power sources of the DSP circuit 2002, frame memory 2003, display unit 2004, recording unit 2005, and operation unit 2006 to these supply targets as appropriate.

[0203] As described above, by using the above-described imaging device 100A or the like as an imaging device, it is expected that a good image can be obtained.

[0204] Fig.35 : is a block diagram showing an exemplary configuration of a distance measuring device 3000 as an electronic device to which the present technology is applied.

[0205] The distance measuring device 3000 measures the distance according to a method of measuring the spatial propagation time of light (time of flight; TOF). The distance measuring device 3000 includes a light source unit 3001, a sensor unit 3002, a signal processing unit 3003, a timing adjustment circuit 3004, and a controller 3005.

[0206] For example, the light source unit 3001 includes a light source 3011 and a driving circuit 3012. For example, the sensor unit 3002 includes a light receiving unit 3021 and a driving circuit 3022. For example, the signal processing unit 3003 includes a control unit 3031, a timing generation unit 3032, and a distance image output unit 3033. The control unit 3031 includes a distance calculation unit 3131 and a distance correction unit 3132.

[0207] In the distance measuring device 3000, the driving of the light source unit 3001 and the sensor unit 3002 is synchronized by the timing generation unit 3032. In the light source unit 3001, the target object 4000 is irradiated with illumination light based on the trigger from the timing adjustment circuit 3004. In the sensor unit 3002, when the target object 4000 is irradiated with illumination light, the intensity of the reflected light reflected from the target object 4000 is received by the light receiving unit 3021. The intensity of the reflected light is associated with the driving timing of the sensor unit 3002 and the distance to the target object 4000. The sensor unit 3002 outputs a signal voltage corresponding to the intensity of the reflected light incident on the sensor unit 3002 to the control unit 3031 as an output signal. In the control unit 3031, the distance to the target object 4000 is calculated in the distance calculation unit 3131 based on the output signal and the driving timing, the distance is corrected in the distance correction unit 3132, and the distance image data is output. The distance image output unit 3033 outputs the distance image data obtained from the control unit 3031 to the controller 3005 .

[0208] Fig.36 One example of a circuit configuration of a sensor pixel included in the sensor unit 3002 of the distance measuring device 3000 is shown. Fig.37 1 shows a timing diagram for driving the sensor pixels included in the sensor unit 3002. The illumination light radiated from the light source unit 3001 is reflected on the target object 4000. The reflected light reflected from the target object 4000 is incident on the sensor unit 3002 after a delay t1. At this time, for example, the charge generated by PD0 is distributed to MEM01 and MEM02 in a ratio corresponding to t2 and t3. According to the outputs of MEM01 and MEM02 and the driving timing of the first transfer transistor TRY01 and the first transfer transistor TRY02, the distance to the target object 4000 can be calculated.

[0209] <5. Application Examples>

[0210] The technology according to the embodiments of the present disclosure (the present technology) is applicable to various products. For example, the technology according to the embodiments of the present disclosure is implemented as a device installed on any type of mobile body, such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0211] Fig.38 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0212] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.38 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as the functional configuration of the integrated control unit 12050.

[0213] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating a drive force for the vehicle; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating a braking force for the vehicle, etc.

[0214] The body system control unit 12020 controls the operation of various devices provided to the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a taillight, a brake light, a turn signal light, or a fog light. In this case, radio waves transmitted from a portable device as a substitute for a key or signals of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, and lights of the vehicle.

[0215] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle having the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform detection processing on objects such as people, vehicles, obstacles, signs, or symbols on the road surface, or detection processing of the distance to these objects.

[0216] The imaging unit 12031 is an optical sensor for receiving light and outputting an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0217] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that takes a picture of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0218] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside or outside of the vehicle (the information is obtained by the outside information detection unit 12030 or the inside information detection unit 12040), and output the control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform the coordinated control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes: collision avoidance or collision mitigation of the vehicle, following driving based on the vehicle-to-vehicle distance, vehicle speed maintenance driving, vehicle collision warning or vehicle lane departure warning, etc.

[0219] In addition, the microcomputer 12051 can perform collaborative control intended for autonomous driving, which enables the vehicle to drive autonomously by controlling a driving force generating device, a steering mechanism, or a braking device, etc. based on information about the interior or exterior of the vehicle (the information is obtained by the exterior information detection unit 12030 or the interior information detection unit 12040), without relying on the driver's operation.

[0220] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information about the exterior of the vehicle, which is obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the preceding vehicle or the oncoming vehicle detected by the exterior information detection unit 12030.

[0221] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device that can visually or auditorily notify the vehicle's passengers or the outside of the vehicle of information. Fig.38 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are illustrated as output devices. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0222] Fig.39 12031 is a diagram showing an example of the installation position of the camera unit 12031.

[0223] exist Fig.39 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0224] The camera units 12101, 12102, 12103, 12104 and 12105 are, for example, located at the front nose, rearview mirror, rear bumper, rear door, and the upper portion of the windshield in the vehicle compartment of the vehicle 12100. The camera unit 12101 disposed on the front nose and the camera unit 12105 disposed on the upper portion of the windshield inside the vehicle mainly obtain images in front of the vehicle 12100. The camera units 12102 and 12103 disposed on the rearview mirror mainly obtain images of the side areas of the vehicle 12100. The camera unit 12104 disposed on the rear bumper or rear door mainly obtains images of the rear of the vehicle 12100. The camera unit 12105 disposed on the upper portion of the windshield inside the vehicle is mainly used to detect vehicles in front, pedestrians, obstacles, signals, traffic signs or lanes, etc.

[0225] in addition, Fig.39 An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided to the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided to the side mirrors. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided to the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above is obtained.

[0226] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0227] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting the nearest three-dimensional object as the leading vehicle, in particular, the three-dimensional object exists on the driving path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). In addition, the microcomputer 12051 can pre-set the inter-vehicle distance to be maintained in front of the leading vehicle, and perform automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control), etc. Therefore, cooperative control intended for automatic driving can be performed, which allows the vehicle to travel autonomously without relying on the driver's operation, etc.

[0228] For example, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into three-dimensional object data of other three-dimensional objects such as two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians and utility poles based on the distance information obtained from the camera units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually identify. Then, the microcomputer 12051 determines the collision risk representing the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collision.

[0229] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the camera units 12101 to 12104. For example, such identification of pedestrians is performed by a program that extracts feature points in the captured images of the camera units 12101 to 12104 that are infrared cameras and a program that determines whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the camera units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square contour line for emphasis is displayed in a manner superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon or the like representing a pedestrian is displayed at a desired position.

[0230] The above describes an example of a vehicle control system to which the technology related to the present technology can be applied. The technology according to the present disclosure can be applied to the camera unit 12031 in the above-mentioned structure. Specifically, the camera device 100A shown in FIG. 1 and the like can be applied to the camera unit 12031. By applying the technology of the present disclosure to the camera unit 12031, an excellent operation of the vehicle control system can be expected.

[0231] The present disclosure is described above by referring to the first and second embodiments, variants 1 to 9, applicable examples, and application examples, but the present disclosure is not limited to the above embodiments, etc., and various modifications can be made. For example, although the first embodiment, etc., describes an example of a back-illuminated image sensor of a global shutter method, the camera device of the present disclosure is not limited to a back-illuminated image sensor, and is also applicable to a front-illuminated image sensor.

[0232] Furthermore, the imaging device of the present disclosure may take the form of a module in which an imaging section and a signal processing unit or an optical system are packaged together.

[0233] Note that the effects described in this specification are merely examples, and the effects are not limited to those described in this specification. There may be effects other than those described in this specification.

[0234] In addition, the present technology can also be configured as follows. According to an embodiment of the present technology having the following configuration, the photoelectric conversion unit is arranged on the first surface of the semiconductor substrate, and the two charge storage units are arranged on the second surface of the semiconductor substrate, thereby expanding the area of ​​the photoelectric conversion unit and the two charge storage units within the sensor pixel. Therefore, an imaging device with a larger saturation charge and a higher sensitivity can be realized.

[0235] (1) A camera device comprising:

[0236] a first semiconductor substrate of a first conductivity type including a first surface and a second surface on an opposite side of the first surface;

[0237] a second conductivity type photoelectric conversion unit embedded in the first surface of the first semiconductor substrate and generating charges corresponding to the amount of received light by photoelectric conversion;

[0238] a first charge storage unit and a second charge storage unit, both of the second conductivity type, which are embedded in parallel in the second surface of the first semiconductor substrate and store the charges generated in the photoelectric conversion unit;

[0239] a first charge transfer unit that transfers the charges from the photoelectric conversion unit to the first charge storage unit; and

[0240] A second charge transfer unit transfers the charges from the photoelectric conversion unit to the second charge storage unit.

[0241] (2) The image pickup device according to (1), wherein a pitch between the first charge storage unit and the second charge storage unit in the first direction is substantially half a pitch between the photoelectric conversion units in the first direction.

[0242] (3) The imaging device according to (1) or (2), wherein a transfer direction of the charge from the photoelectric conversion unit to the first charge storage unit is opposite to a transfer direction of the charge from the photoelectric conversion unit to the second charge storage unit.

[0243] (4) The imaging device according to any one of (1) to (3), further comprising:

[0244] a first charge-voltage conversion unit to which the charge is transferred from the first charge storage unit; and

[0245] a second charge-voltage conversion unit, the charge is transferred from the second charge storage unit to the second charge-voltage conversion unit.

[0246] (5) The imaging device according to (2) or (3), further comprising:

[0247] a first charge-voltage conversion unit to which the charge is transferred from the first charge storage unit; and

[0248] a second charge-to-voltage conversion unit, the charge is transferred from the second charge storage unit to the second charge-to-voltage conversion unit, wherein,

[0249] The plurality of photoelectric conversion units are arranged along a second direction orthogonal to the first direction,

[0250] The plurality of photoelectric conversion units include a first photoelectric conversion unit, a second photoelectric conversion unit, a third photoelectric conversion unit, and a fourth photoelectric conversion unit which are sequentially arranged, and

[0251] The first charge-voltage conversion unit is shared by the first photoelectric conversion unit and the third photoelectric conversion unit, and the second charge-voltage conversion unit is shared by the second photoelectric conversion unit and the fourth photoelectric conversion unit.

[0252] (6) The image pickup device according to (5), wherein the first photoelectric conversion unit and the second photoelectric conversion unit share the first charge-voltage conversion unit and the second charge-voltage conversion unit with each other.

[0253] (7) The imaging device according to (6), wherein a pitch between the first charge storage unit and the second charge storage unit in the first direction is the same pitch as a pitch between the photoelectric conversion units in the first direction.

[0254] (8) The imaging device according to any one of (1) to (7), wherein a portion of the photoelectric conversion unit extends toward the second surface.

[0255] (9) The imaging device according to any one of (1) to (8), wherein the first semiconductor substrate further includes one or more vertical transistors that are provided on the first surface and reach the photoelectric conversion unit.

[0256] (10) The imaging device according to (9), wherein:

[0257] The first semiconductor substrate includes a first vertical transistor and a second vertical transistor as the plurality of vertical transistors, and

[0258] A line connecting the first vertical transistor and the second vertical transistor is orthogonal to an arrangement direction of the first charge storage unit and the second charge storage unit.

[0259] (11) The imaging device according to any one of (1) to (10), wherein:

[0260] The first semiconductor substrate further includes a plurality of vertical transistors disposed on the first surface and reaching the photoelectric conversion unit, and

[0261] The plurality of vertical transistors function as a part of both the first charge transfer unit and the second charge transfer unit.

[0262] (12) The imaging device according to any one of (1) to (11), further comprising:

[0263] A discharge transistor for resetting the photoelectric conversion unit.

[0264] (13) The imaging device according to (12), wherein a transfer direction of the charge from the photoelectric conversion unit to the first charge storage unit and the second charge storage unit is orthogonal to a transfer direction of the charge from the photoelectric conversion unit to the discharge transistor.

[0265] (14) The image pickup device according to any one of (1) to (13), wherein the first charge storage unit and the second charge storage unit have sizes different from each other.

[0266] (15) The imaging device according to any one of (4) to (14), wherein the first charge-voltage conversion unit also serves as the first charge storage unit.

[0267] (16) The imaging device according to any one of (4) to (15), wherein the first semiconductor substrate further includes a readout circuit that reads out signals output from the first charge-voltage conversion unit and the second charge-voltage conversion unit.

[0268] (17) The imaging device according to any one of (4) to (16), further comprising:

[0269] A second semiconductor substrate is provided with a pixel circuit that reads out signals output from the first charge-voltage conversion unit and the second charge-voltage conversion unit, wherein:

[0270] The second semiconductor substrate is stacked on the second surface of the first semiconductor substrate via an interlayer insulating film.

[0271] Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations may be made according to design requirements and other factors, as long as these modifications, combinations, sub-combinations and alterations are within the scope of the appended claims or the equivalents thereof.

[0272] [reference numerals list]

[0273] 10,40 Semiconductor substrate

[0274] 11 Photoelectric conversion unit (PD)

[0275] 12A,12B Charge storage unit (MEM)

[0276] 13,14 Floating Diffusion (FD)

[0277] 15 VDD contact area

[0278] 16 VSL contact area

[0279] 17 Pixel Isolation

[0280] 18 Isolation film

[0281] 19A, 19B, 19C, 19D Transfer gate electrode

[0282] 19E Discharge grid electrode

[0283] 20,50 Interconnection layers

[0284] 21,51 Insulation film

[0285] 22A, 23A First transfer transistor (TRY)

[0286] 22B, 23B Second transfer transistor (TRG)

[0287] 24 Reset transistor (RST)

[0288] 25 Select transistor (SEL)

[0289] 26 Amplifier transistor (AMP)

[0290] 27,52 Interlayer insulation film

[0291] 28,53 pad electrode

[0292] 54 Through Holes

[0293] 31 Color Filters

[0294] 32 On-chip lens

[0295] 100A to 100M Camera Device

[0296] 110,1100,1101,1102,1103 sensor pixels

[0297] 111 pixel array unit

[0298] 112 Vertical drive unit

[0299] 113 columns signal processing unit

[0300] 114 Horizontal drive unit

[0301] 115 System control unit

[0302] 116 pixel drive lines

[0303] 117 Vertical signal line (VSL)

[0304] 118 Signal Processing Unit

[0305] 119 Data storage unit

Claims

1. A camera device, comprising: a first semiconductor substrate of a first conductivity type including a first surface and a second surface on an opposite side of the first surface; a second conductivity type photoelectric conversion unit embedded in the first surface of the first semiconductor substrate and generating charges corresponding to the amount of received light by photoelectric conversion; a first charge storage unit and a second charge storage unit, both of the second conductivity type, which are embedded in parallel in the second surface of the first semiconductor substrate and store the charges generated in the photoelectric conversion unit; a first charge transfer unit, which transfers the charges from the photoelectric conversion unit to the first charge storage unit; a second charge transfer unit, which transfers the charge from the photoelectric conversion unit to the second charge storage unit; a first charge-to-voltage conversion unit, the charge is transferred from the first charge storage unit to the first charge-to-voltage conversion unit; and a second charge-to-voltage conversion unit, the charge is transferred from the second charge storage unit to the second charge-to-voltage conversion unit, wherein, The spacing between the first charge storage unit and the second charge storage unit in the first direction is substantially half of the spacing between the photoelectric conversion units in the first direction, The plurality of photoelectric conversion units are arranged along a second direction orthogonal to the first direction, The plurality of photoelectric conversion units include a first photoelectric conversion unit, a second photoelectric conversion unit, a third photoelectric conversion unit, and a fourth photoelectric conversion unit which are sequentially arranged, and The first charge-voltage conversion unit is shared by the first photoelectric conversion unit and the third photoelectric conversion unit, and the second charge-voltage conversion unit is shared by the second photoelectric conversion unit and the fourth photoelectric conversion unit.

2. The imaging device according to claim 1, wherein: A transfer direction of the charges from the photoelectric conversion unit to the first charge storage unit is opposite to a transfer direction of the charges from the photoelectric conversion unit to the second charge storage unit.

3. The imaging device according to claim 1, wherein: The first photoelectric conversion unit and the second photoelectric conversion unit share the first charge-voltage conversion unit and the second charge-voltage conversion unit with each other.

4. The imaging device according to claim 1, wherein: A portion of the photoelectric conversion unit extends toward the second surface.

5. The imaging device according to claim 1, wherein: The first semiconductor substrate further includes one or more vertical transistors disposed on the first surface and reaching the photoelectric conversion unit.

6. The imaging device according to claim 5, wherein: The first semiconductor substrate includes a first vertical transistor and a second vertical transistor as the plurality of vertical transistors, and A line connecting the first vertical transistor and the second vertical transistor is orthogonal to an arrangement direction of the first charge storage unit and the second charge storage unit.

7. The imaging device according to claim 1, wherein: The first semiconductor substrate further includes a plurality of vertical transistors disposed on the first surface and reaching the photoelectric conversion unit, and The plurality of vertical transistors function as a part of both the first charge transfer unit and the second charge transfer unit.

8. The camera device according to claim 1, further comprising: A discharge transistor for resetting the photoelectric conversion unit.

9. The imaging device according to claim 8, wherein: A transfer direction of the charges from the photoelectric conversion unit to the first charge storage unit and the second charge storage unit is orthogonal to a transfer direction of the charges from the photoelectric conversion unit to the discharge transistor.

10. The imaging device according to claim 1, wherein: The first charge storage unit and the second charge storage unit have sizes different from each other.

11. The imaging device according to claim 1, wherein: The first charge-voltage conversion unit also serves as the first charge storage unit.

12. The imaging device according to claim 1, wherein: The first semiconductor substrate further includes a readout circuit that reads out signals output from the first charge-voltage conversion unit and the second charge-voltage conversion unit.

13. The camera device according to claim 1, further comprising: A second semiconductor substrate is provided with a pixel circuit that reads out signals output from the first charge-voltage conversion unit and the second charge-voltage conversion unit, wherein: The second semiconductor substrate is stacked on the second surface of the first semiconductor substrate via an interlayer insulating film.

Images